DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the application filed 20 June 2025.
Claims 1-20 are pending and have been presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8, 16 and 20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by LEE-774 (U.S. Patent Application Publication #2019/0080774).
1. LEE-774 discloses A storage system comprising: a first memory set including a plurality of first nonvolatile memory devices (see figure 2, element 120) and configured to communicate through a first channel (see figure 2, elements 163 and 165); a second memory set including a plurality of second nonvolatile memory devices (see figure 2, element 130) and configured to communicate through a second channel (see figure 2, elements 173 and 175); and a storage controller including a first interface circuit connected to the first channel and a second interface circuit connected to the second channel (see figure 2, element 110), wherein the storage controller is configured to measure, under a preset channel operating condition, a first signal integrity (SI) state of the first channel (see [0035]: read a training pattern and detect a center of a data signal window, this read would take place using the current settings, the current settings would be the preset channel operating condition) and a second SI state of the second channel (see [0035]: read a training pattern and detect a center of a data signal window, this read would take place using the current settings, the current settings would be the preset channel operating condition; [0042]: training is performed on each group), set, based on a first adjustment channel value, a first channel operating condition of the first channel, the first adjustment channel value being based on the first SI state (see [0041]: adjustment of an offset value of a DLL and/or PLL), and set, based on a second adjustment channel value, a second channel operating condition of the second channel, the second adjustment channel value being based on the second SI state (see [0041]: adjustment of an offset value of a DLL and/or PLL; [0042]: training is performed on each group).
2. The storage system of claim 1, wherein for measuring the first SI state and the second SI state, the storage controller is configured to set an initial channel operating condition (see [0028]: an offset is adjusted based on the training pattern, the values used to initially read the training pattern would be the initial channel operating condition) and measure a value of an eye diagram for a respective signal during an operation of each of the first channel and the second channel (see [0027]: adjustment of sampling time point of the eye pattern of the data signal).
8. LEE-774 discloses A storage system comprising: a plurality of memory sets each including a plurality of nonvolatile memory devices (see figure 2, element 120 and 130), the plurality of nonvolatile memory devices of each memory set being connected to one another through a respective channel of a plurality of channels (see figure 2, elements 163, 165, 173, 175); and a storage controller including a plurality of interface circuits respectively connected to the plurality of channels (see figure 2, element 110), the storage controller being configured to set each of the plurality of interface circuits based on a corresponding adjustment channel value of adjustment channel values (see [0041]: configure offset for the group of memory devices; [0042]: offset is configured for each group of devices), wherein each of the adjustment channel values is based on a difference between a respective signal integrity (SI) state during an operation of a respective channel of the plurality of channels and a preset minimum SI state based on a preset channel operating condition (see [0027]-[0028]: calculate offset to align the sampling time point with the center of the eye pattern).
16. LEE-774 discloses An operating method of a storage controller, the storage controller including a first interface circuit connected to a first channel (see figure 2, elements 163 and 165) that is configured to perform communication with a plurality of first nonvolatile memory devices (see figure 2, element 120) and a second interface circuit connected to a second channel (see figure 2, elements 173 and 175) that is configured to perform communication with a plurality of second nonvolatile memory devices (see figure 2, element 130), the operating method comprising: measuring signal integrity (SI) states based on at least one channel operating condition of each of the first channel and the second channel (see [0027]-[0028]: sampling time point in relation to the center of the eye pattern); outputting a first adjustment channel value based on a first difference level between a first SI state of the first channel of the SI states and a preset minimum SI state (see [0041]: offset to align the center of the data signal to the sampling time point; offset value is set for each group of memory devices); outputting a second adjustment channel value based on a second difference level between a second SI state of the second channel of the SI states and the preset minimum SI state (see [0041]: offset to align the center of the data signal to the sampling time point; offset value is set for each group of memory devices); setting the first interface circuit for the first channel to the first adjustment channel value; and setting the second interface circuit for the second channel to the second adjustment channel value (see [0041]: the offset value sets the interface circuit to align the sampling time with the center of the data signal).
20. The operating method of claim 16, wherein the first adjustment channel value and the second adjustment channel value are different, and the first adjustment channel value and the second adjustment channel value are based on the SI states of the first and second channels, respectively (see [0069]-[0070]: the length of the data lines will vary for each group, resulting in different offset values).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE-774 (U.S. Patent Application Publication #2019/0080774) in view of TANG (U.S. Patent Application Publication #2024/0185900).
3. The storage system of claim 2, wherein the value of the eye diagram comprises a unit time value based on a phase locked loop (PLL), a delay locked loop (DLL) and/or a phase (see LEE-774 [0041]: offset value of a DLL and/or PLL), and a range of a voltage swing width of the respective signal (see TANG below).
TANG discloses the following limitations that are not taught by LEE-774: a range of a voltage swing width of the respective signal (see [0179]-[0180]: reference voltage detection circuit to determine the optimal reference voltage). Calibrating the voltage generator to utilize the optimal reference voltage allows the system to fully utilize the data eye window (see [0180]). LEE-774 already discloses a system that uses a voltage generator (see LEE-774 [0057]) and uses the data eye to calibrate communication with the non-volatile memory devices (see LEE-774 [0041]). Performing the training disclosed by TANG would be compatible with the system of LEE-774 to calibrate the voltage generator already used by LEE-774 and ensure the data eye window is fully utilized by the training performed by LEE-774.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LEE-774 to calibrate the voltage swing of the signal, as disclosed by TANG. One of ordinary skill in the art would have been motivated to make such a modification to fully utilize the data eye window, as taught by TANG. LEE-774 and TANG are analogous/in the same field of endeavor as both references are directed to calibrating the interface used to communicate with a memory.
19. The operating method of claim 16, wherein the first and second SI states include: a unit time value based on a phase locked loop (PLL), a delay locked loop (DLL),and/or a phase of an eye diagram of each of the first and second channels (see LEE-774 [0041]: offset value of a DLL and/or PLL); and a voltage level range of a voltage swing width of a signal during an operation (see TANG below).
TANG discloses the following limitations that are not taught by LEE-774: a range of a voltage swing width of the respective signal (see [0179]-[0180]: reference voltage detection circuit to determine the optimal reference voltage). Calibrating the voltage generator to utilize the optimal reference voltage allows the system to fully utilize the data eye window (see [0180]). LEE-774 already discloses a system that uses a voltage generator (see LEE-774 [0057]) and uses the data eye to calibrate communication with the non-volatile memory devices (see LEE-774 [0041]). Performing the training disclosed by TANG would be compatible with the system of LEE-774 to calibrate the voltage generator already used by LEE-774 and ensure the data eye window is fully utilized by the training performed by LEE-774.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LEE-774 to calibrate the voltage swing of the signal, as disclosed by TANG. One of ordinary skill in the art would have been motivated to make such a modification to fully utilize the data eye window, as taught by TANG. LEE-774 and TANG are analogous/in the same field of endeavor as both references are directed to calibrating the interface used to communicate with a memory.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE-774 (U.S. Patent Application Publication #2019/0080774) in view of LEE-890 (U.S. Patent Application Publication #2022/0214890).
4. The storage system of claim 1, wherein the storage controller comprises: a memory configured to store the first and second SI states (see LEE-890 below); and an SI quality manager configured to set the first interface circuit by transmitting the first adjustment channel value (see LEE-774 [0041]: training manager setting the offset value of the storage controller), and set the second interface circuit by transmitting the second adjustment channel value (see LEE-774 [0041]: training manager setting the offset value of the storage controller).
LEE-890 discloses the following limitations that are not taught by LEE-774: a memory configured to store the first and second SI states (see [0046]: calibration code stored in a register). LEE-890 discloses training memory channels in a DRAM system, evaluating the signal integrity and configuring the channel based on the signal integrity (see [0035]). The configuration data is stored in a register (see [0041]). LEE-774 discloses configuring an offset, but is silent about a memory for storing SI states. LEE-890 discloses the use of a register to store the configuration information, which would be the SI states. “When there is a design need for market pressure to solve a problem and there are a finite number if identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 82 USPQ2d at 1397.
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify LEE-774 to include a memory to store the SI states, as disclosed by LEE-890. One of ordinary skill in the art would have been motivated to make such a modification as this would be obvious to try based on the limited number of identified, predicable solutions. LEE-774 and LEE-890 are analogous/in the same field of endeavor as both references are directed to configuring memory channels based on signal integrity.
5. The storage system of claim 4, wherein the SI quality manager is configured to calculate the first adjustment channel value based on a first difference level between the first SI state and a preset minimum SI state (see [0027]-[0028]: calculate offset to align the sampling time point with the center of the eye pattern), and calculate the second adjustment channel value based on a second difference level between the second SI state and the preset minimum SI state (see [0027]-[0028]: calculate offset to align the sampling time point with the center of the eye pattern).
Allowable Subject Matter
Claims 6, 7, 9-15, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 6 and 9: the state of the art fails to anticipate, or render obvious, “… the storage controller includes an optimal value storage device configured to store a plurality of adjustment channel values corresponding to a plurality of tiers of operating conditions, the plurality of tiers of operating conditions being based on different levels of deviation from a preset minimum SI state.”
With respect to claim 11: the state of the art fails to anticipate, or render obvious, “… set a channel operating condition of a first channel of the plurality of channels; set a variable of the SI state of the first channel as a preset minimum value; preset expected data in a first memory set that is connected to the first channel; perform an access operation to the expected data in the first memory set; compare a first test data received from the first memory set to the expected data; measure a first SI state of the first channel based on a result of the comparison; and record the first SI state of the first channel mapping with the set channel operating condition based on the result of the comparison.”
With respect to claim 17: the state of the art fails to anticipate, or render obvious, “… setting a first channel operating condition in the first channel and a second channel operating condition in the second channel; presetting expected data in at least one of the plurality of first nonvolatile memories and at least one of the plurality of second nonvolatile memories; receiving test data by the at least one of the plurality of first nonvolatile memories and the at least one of the plurality of second nonvolatile memories; and measuring and storing the first SI state corresponding to the first channel operating condition of the first channel and the second SI state corresponding to the second channel operating condition of the second channel.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MUKHERJEE [2020/0293415] discloses calibrating a memory device and training each interface to the memory. [0045], [0054]
EUGENIO [2018/0136866] discloses adjusting the data signals for a memory device based on the data eye. [0033]-[0037]
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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