DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8-9, 11, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jung et al (US 2019/0318693 A1).
Claim 1, Jung (Fig. 1-14) discloses a display substrate (SUB; Fig. 1-3), comprising:
a substrate (SUB; Fig. 1-3) and a gate driving circuit (SDV; Fig.1 and 2; SST; Fig. 3) provided on the substrate (SUB; Fig. 1-3);
the gate driving circuit (SST1; Fig. 5) comprises:
a frame start signal line (Paragraph [0091]; wherein discloses “For example, the first scan stage circuit SST1 may be supplied with the start pulse”; Paragraph [0293]), a clock signal line (1002 or 1003; Fig. 6; Paragraph [0293]), a first level signal line (1004; Fig. 6; Paragraph [0294]), a second level signal line (1005; Fig. 6; Paragraph [0294]) and a plurality of shift register units (SST1-SST17; Fig. 3);
wherein each of the plurality of shift register units (SST; Fig. 3, 5, and 6) comprises a plurality of transistors (T1-T8; Fig. 5), the plurality of transistors (T1-T8; Fig. 5) comprises a second transistor (T2; Fig. 5), a fifth transistor (T4; Fig. 5) and an eighth transistor (T6; Fig. 5);
an active layer (ACT4; Fig. 6) of the fifth transistor (T4; Fig. 6) comprises two fifth conductive portions arranged opposite to each other (SE4 and DE4; Fig. 6), and a fifth channel portion (GE4; Fig. 6) located between the two fifth conductive portions (SE4 and DE4; Fig. 6);
one of the two fifth conductive portions (DE4; Fig. 6) is coupled to a common connection terminal (Fig. 6; wherein figure clearly shows a single electrode connected between GE2 and GE6; see figure 6 below) through a first conductive connection portion (Fig. 6; wherein figure shows a connection portion between DE4 and single electrode connected between the two gate electrode GE2 and GE6);
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the common connection terminal (Fig. 6; wherein figure clearly shows a single electrode connected between GE2 and GE6) comprises a gate electrode of the second transistor (GE2; Fig. 6), a gate electrode of the eighth transistor (GE6; Fig. 6), and a fourth conductive connection portion (Fig. 6; wherein figure shows electrodes of GE6 and GE2 are connected through a conductive connection portion);
the fourth conductive connection portion (Fig. 6; wherein figure shows electrodes of GE6 and GE2 are connected through a conductive connection portion) is used to couple the gate electrode of the eighth transistor (GE6; Fig. 6) and the gate electrode of the second transistor (GE2; Fig. 6);
the first conductive connection portion (Fig. 6; wherein figure shows a connection portion between DE4 and single electrode connected between the two gate electrode GE2 and GE6) extends along a first direction (DR2; Fig. 6); and
the clock signal line (1002 or 1003; Fig. 6; Paragraph [0293]) extends along the first direction (DR2; Fig. 6).
Claim 11, Jung (Fig. 1-14) discloses a display substrate (SUB; Fig. 1-3), comprising:
a substrate (SUB; Fig. 1-3) and a gate driving circuit (SDV; Fig.1 and 2; SST; Fig. 3) provided on the substrate (SUB; Fig. 1-3);
the gate driving circuit (SST1; Fig. 5) comprises:
a frame start signal line (Paragraph [0091]; wherein discloses “For example, the first scan stage circuit SST1 may be supplied with the start pulse”; Paragraph [0293]), a clock signal line (1002 or 1003; Fig. 6; Paragraph [0293]), a first level signal line (1004; Fig. 6; Paragraph [0294]), a second level signal line (1005; Fig. 6; Paragraph [0294]) and a plurality of shift register units (SST1-SST17; Fig. 3);
wherein each of the plurality of shift register units (SST; Fig. 3, 5, and 6) comprises a plurality of transistors (T1-T8; Fig. 5), the plurality of transistors (T1-T8; Fig. 5) comprises a second transistor (T2; Fig. 5), a fifth transistor (T4; Fig. 5) and an eighth transistor (T6; Fig. 5);
an active layer (ACT4; Fig. 6) of the fifth transistor (T4; Fig. 6) comprises two fifth conductive portions arranged opposite to each other (SE4 and DE4; Fig. 6), and a fifth channel portion (GE4; Fig. 6) located between the two fifth conductive portions (SE4 and DE4; Fig. 6);
one of the two fifth conductive portions (DE4; Fig. 6) is coupled to a common connection terminal (Fig. 6; wherein figure clearly shows a single electrode connected between GE2 and GE6; see figure 6 above) through a first conductive connection portion (Fig. 6; wherein figure shows a connection portion between DE4 and single electrode connected between the two gate electrode GE2 and GE6);
the common connection terminal (Fig. 6; wherein figure clearly shows a single electrode connected between GE2 and GE6) comprises a gate electrode of the second transistor (GE2; Fig. 6), a gate electrode of the eighth transistor (GE6; Fig. 6), and a fourth conductive connection portion (Fig. 6; wherein figure shows electrodes of GE6 and GE2 are connected through a conductive connection portion);
the fourth conductive connection portion (Fig. 6; wherein figure shows electrodes of GE6 and GE2 are connected through a conductive connection portion) is used to couple the gate electrode of the eighth transistor (GE6; Fig. 6) and the gate electrode of the second transistor (GE2; Fig. 6);
the first conductive connection portion (Fig. 6; wherein figure shows a connection portion between DE4 and single electrode connected between the two gate electrode GE2 and GE6) extends along a first direction (DR2; Fig. 6);
the gate electrode (GE6; Fig. 6) of the eighth transistor (T6; Fig. 6) extends along a second direction (DR1; Fig. 6), and the second direction (DR1; Fig. 6) intersects the first direction (DR2; Fig. 6).
Claim 2, Jung (Fig. 1-14) discloses wherein an extension direction (DR2; Fig. 6) of an orthographic projection (Fig. 6; wherein figure shows a plan view of scan stage circuit) of the first conductive connection portion (See highlighted figure 6 above in relation to the first conductive connection portion) onto the substrate (SUB; Fig. 1-3), is substantially perpendicular to an extension direction (DR1; Fig. 6) of an orthographic projection (Fig. 6; wherein figure shows a plan view of scan stage circuit) of the common connection terminal (See highlighted figure 6 above in relation to the common connection terminal) onto the substrate (SUB; Fig. 1-3).
Claim 3, Jung (Fig. 1-14) discloses wherein the first conductive connection portion (See highlighted figure 6 above in relation to the first conductive connection portion) is coupled to the common connection terminal (See highlighted figure 6 above in relation to the common connection terminal) through a via hole (Fig. 6; wherein figure shows the connection between the elements is through a via hole).
Claim 5, Jung (Fig. 1-14) discloses wherein each of the plurality of shift register units (SST1-SST17; Fig. 3) further comprises a sixth transistor (T8; Fig. 5 and 6);
the sixth transistor (T8; Fig. 6) comprises a sixth active pattern (ACT8; Fig. 6), the sixth active pattern (ACT8; Fig. 6) extends along the first direction (DR2; Fig. 6), and the sixth active pattern (ACT8; Fig. 6) comprises two sixth conductive portions (DE8 and SE8; Fig. 6) arranged opposite to each other along the first direction (DR2; Fig. 6), and a sixth channel portion (GE8; Fig. 6) located between the two sixth conductive portions (DE8 and SE8; Fig. 6),
wherein the shift register unit (SST1; Fig. 6) further comprises a fifth conductive connection portion (See figure 6 below which highlights the 5th conductive connection) extending along a second direction (DR1; Fig. 6);
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an orthographic projection (Fig. 6) of an input electrode (SE8; Fig. 6) of the sixth transistor (T8; Fig. 6) onto the substrate (SUB; Fig. 1-3) and an orthographic projection (Fig. 6) of one of the sixth conductive portions (ACT8; Fig. 6) onto the substrate (SUB; Fig. 1-3) have an eighth overlapping area (See figure 6 below which highlights the overlapping area), the input electrode (SE8; Fig. 6) of the sixth transistor (T8; Fig. 6) is coupled to one of the sixth conductive portions (ACT6; Fig. 6) through an eighth via hole (Fig. 6; wherein figure shows connection through via holes) provided in the eighth overlapping area (See figure 6 below which highlights the overlapping area);
the fifth conductive connection portion (See figure 6 above which highlights the 5th conductive connection) is coupled to the input electrode (SE8; Fig. 6) of the sixth transistor (T8; Fig. 6) through a via hole (Fig. 6; wherein figure shows connection through via holes).
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Claim 6, Jung (Fig. 1-14) discloses wherein the sixth transistor (T8; Fig. 6) further comprises an output electrode (DE8; Fig. 6);
an orthographic projection (Fig. 6) of the output electrode (DE8; Fig. 6) of the sixth transistor (T8; Fig. 6) onto the substrate (SUB; Fig. 1-3) and an orthographic projection (Fig. 6) of the other of sixth conductive portions (ACT8; Fig. 6) onto the substrate (SUB; Fig. 6) have a ninth overlapping area (See figure 6 below which highlights the overlapping area); and
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the output electrode (SE8; Fig. 6) of the sixth transistor (T8; Fig. 6) is coupled to the other of sixth conductive portions (ACT8; Fig. 6) through a ninth via hole (Fig. 6; wherein figure shows connection through via holes) provided in the ninth overlapping area (See figure 6 above which highlights the overlapping area);
the shift register unit (SST1; Fig. 5 and 6) further includes a seventh transistor (T7; Fig. 5 and 6);
a gate electrode (GE7; Fig. 6) of the seventh transistor (T7; Fig. 6) is coupled to the output electrode (DE68; Fig. 6) of the sixth transistor (T8; Fig. 6) through a via hole (Fig. 6; wherein figure shows connection through via holes).
Claim 8, Jung (Fig. 1-14) discloses wherein the shift register unit (SST1; Fig. 6) further includes a seventh transistor (T7; Fig. 5 and 6) and an eighth transistor (T6; Fig. 5 and 6) arranged along the first direction (DR2; Fig. 6), an output electrode (SE7; Fig. 6) of the seventh transistor (T7; Fig. 6) and an output electrode (DE6; Fig. 6) of the eighth transistor (T6; Fig. 6) are both coupled to a gate driving signal output terminal (1006; Fig. 6; Paragraphs [0197] and [0200]);
the seventh transistor (T7; Fig. 6) includes two seventh active patterns (Fig. 6; wherein figure shows two active patterns) arranged along the second direction (DR1; Fig. 6);
the eighth transistor (T6; Fig. 6) includes two eighth active patterns (Fig. 6; wherein figure shows two active patterns) arranged along the second direction (DR1; Fig. 6);
the shift register unit (SST1; Fig. 6) includes two third semiconductor layers (Fig. 6; wherein figure shows two semiconductor layers with respect to transistors T7 and T6), the two third semiconductor layers (Fig. 6; wherein figure shows two semiconductor layers with respect to transistors T7 and T6) are arranged along the second direction (DR1; Fig. 6), and each third semiconductor layer (Fig. 6; wherein figure shows two semiconductor layers with respect to transistors T7 and T6) extends along the first direction (DR2; Fig. 6);
a seventh conductive portion (SE7 and DE7; Fig. 6), a seventh channel portion GE7; Fig. 6), an eighth conductive portion (DE6 and SE6; Fig. 6), and an eighth channel portion (GE6; Fig. 6) included in each of the third semiconductor layers (Fig. 6) all extend along the second direction (DR1; Fig. 6).
Claim 9, Jung (Fig. 1-14) discloses wherein the shift register unit (SST1; Fig. 5 and 6) further comprises a second capacitor (C2; Fig. 5 and 6);
in the two third semiconductor layers (Fig. 6; wherein figure shows two semiconductor layers with respect to transistors T7 and T6), the third semiconductor layer closer to the second capacitor has a larger area (Fig. 6; wherein the semiconductor layer with respect to transistor T7 and T6 which is closer to capacitor C2 is larger than the semiconductor layer closer to capacitor C1).
Claim 14, Jung (Fig. 1-14) discloses a display device (Fig. 1; Paragraph [0048]; wherein discloses a display device), comprising:
the display substrate (SUB; Fig. 1-3) according to claim 1 (See rejection to claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al (US 2019/0318693 A1) in view of Wang et al (US 2019/0304374 A1).
Claim 4, Jung (Fig. 1-14) discloses wherein the plurality of transistors (T1-T8; Fig. 5) further comprises a first transistor (T1; Fig. 5) and a third transistor (T3; Fig. 5);
the first semiconductor layer (ACT1a and ACT1b; Fig. 6; ACT2 and ACT3; Fig. 6; wherein figure shows active patterns for the claimed first through third transistors which are continuously arranged for more than one transistor both extend in the direction DR2) extends along a first direction (DR2; Fig. 6), the at least three channel portions (ACT1a, ACT1b, ACT3, and ACT2; Fig. 6) are arranged along the first direction (DR2; Fig. 6).
Jung does not expressly disclose an active layer of the first transistor, an active layer of the second transistor and active layer of the third transistor are formed by a continuous first semiconductor layer;
the first semiconductor layer includes at least three channel portions corresponding to the first transistor, the second transistor and the third transistor, and a conductive portion provided between adjacent channel portions, the transistors corresponding to the adjacent channel portions are coupled to each other through a corresponding conductive portion.
Wang (Fig. 1-18) discloses an active layer (Paragraph [0081]) of the first transistor (TE12; Fig. 4), an active layer (Paragraph [0081]) of the second transistor (TE8; Fig. 2) and an active layer (Paragraph [0081]) of the third transistor (TE9; Fig. 4) are formed by a continuous first semiconductor layer (Fig. 4; wherein shows doted region as a continuous first semiconductor layer for the transistors TE12, TE9, and TE8);
the first semiconductor layer (Fig. 4; wherein shows doted region as a continuous first semiconductor layer for the transistors TE12, TE9, and TE8) includes at least three channel portions (Paragraph [0081]; wherein discloses channel region for each transistor) corresponding to the first transistor (TE12; Fig. 4), the second transistor (TE8; Fig. 4) and the third transistor (TE9; Fig. 4), and a conductive portion (Paragraph [0081]; wherein discloses junction) provided between adjacent channel portions (Fig. 4), transistors (TE12, TE9, and TE8; Fig. 4) corresponding to the adjacent channel portions (Paragraph [0081]) are coupled to each other through a corresponding conductive portion (Paragraph [0089]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jung’s scan driving circuit by applying a continuous semiconductor layer, as taught by Wang, so to use a scan driving circuit with a continuous semiconductor layer for providing a display device using a sub-gate electrode, thus preventing current leakage, and reducing a dead space (Paragraph [0192]).
Claim 7, Jung (Fig. 1-14) discloses wherein the shift register unit (SST1; Fig. 5 and 6) further includes a fifth conductive connection portion (See figure 6 below which shows the 5th conductive connection) extending along a second direction (DR1; Fig. 6);
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an output electrode (DE1b; Fig. 6) of the first transistor (T1b; Fig. 6) is coupled to one conductive portion (ACT1b; Fig. 6) of the first transistor (T1b; Fig. 6) through a via hole (Fig. 6; wherein figure shows connection through a via hole); and
the fifth conductive connection portion (See figure 6 above which shows the 5th conductive connection) is coupled to the output electrode (DE1b; Fig. 6) of the first transistor (T1b; Fig. 6) through a via hole (Fig. 6; wherein figure shows connection through a via hole).
Claim 10, Jung (Fig. 1-14) discloses wherein the clock signal line (1003; Fig. 6) is coupled to the gate electrode (GE1a; Fig. 6) of the first transistor (T1a; Fig. 6) through two via holes (Fig. 6; wherein figure shows a connected to gate electrode GE1a though two via holes to a clock line 1003).
Allowable Subject Matter
Claims 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. If claim 12 is added to the independent claims, the claims would need to be rejected under nonstatutory double patenting and would still need the filing of terminal disclaimer (with respect to US 11721267 and US 12039911) to overcome nonstatutory double patenting.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 12 is directed to elements T4 and T5 which are formed by a continuous semiconductor layer as shown in Applicant’s figure 4. The Examiner believes this limitation is not specifically taught or disclosed by the cited prior art references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM J SNYDER whose telephone number is (571)270-3460. The examiner can normally be reached Monday-Friday 8am-4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh D Nguyen can be reached at (571)272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam J Snyder/Primary Examiner, Art Unit 2623 01/28/2026