DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guimont et al. (U.S. Patent 8,963,590, hereafter Guimont).
Claim 1: Guimont teaches a chip power-on reset module (Figure 3), comprising:
a power supply state inspection circuit (310, 306, 308, 314), a signal amplification shaping circuit (316), an output driving circuit (322, 332, 334), and a dynamic response enhancement circuit (324, 328, 326, 330),
wherein the power supply state inspection circuit (310, 306, 308, 314) is configured to detect a chip power supply (VDD), and when a power voltage state is reversed (at power-on), an analog signal corresponding to a current power supply status is generated (signal at 312);
the signal amplification shaping circuit (316, 318) is configured to perform hysteretic amplification (Schmitt trigger) on the analog signal output by the power supply state inspection circuit (input is 312), and then shape the amplified signal to output a digital signal (to 319);
the output driving circuit (322, 332, 334) is configured to buffer the digital signal (via 318, 320) to drive outputting (NPOR), and generate a power-on reset signal (NPOR) to drive a load (inherent load connected to NPOR); and
the dynamic response enhancement circuit (324, 328, 330, 326) is configured to monitor the power-on reset signal output by the output driving circuit (via 321 and 323), and lock a state of the power-on reset signal when the power-on reset signal is at a high level (column 6 lines 62-65), wherein the dynamic response enhancement circuit comprises a first locking circuit and a second locking circuit, the first locking circuit comprises a PMOS transistor (328) and a first capacitor (324), and the second locking circuit comprises an NMOS transistor (330) and a second capacitor (326).
Claim 9: Guimont further teaches an integrated circuit chip, comprising the chip power-on reset module according to claim 1 (column 1 lines 22-40 and column 2 lines 43-67).
Claim 10: Guimont further teaches an electronic device, comprising the chip power-on reset module according to claim 1 (column 1 lines 22-40 and column 2 lines 43-67).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guimont in view of Wu (U.S. Patent Application Publication 2007/0052465) in view of Hung (U.S. Patent 7,417,476).
Claim 6: Guimont teaches the limitations of claim 1 above. Guimont does not specifically teach the details of the Schmitt trigger circuit 316 and inverter 318.
Wu teaches a Schmitt trigger circuit (Figure 1, corresponding to the signal amplification shaping circuit 316 of Guimont) comprising a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a first NMOS transistor (N2), a second NMOS transistor (N1), a third NMOS transistor (N3), a first resistor (110), and a second resistor (120), wherein gate electrodes of the first PMOS transistor (P1), the second PMOS transistor (P2), the first NMOS transistor (N2), and the second NMOS transistor (N1) are connected to a drain electrode of the PMOS transistor (via VDD to 328 of Guimont);
drain electrodes of the second PMOS transistor (P2) and the second NMOS transistor (N1) are connected to one end of the second capacitor (output of Figure 1 of Wu is connected to 326 of Guimont via 318, 320 and 322 of Guimont) and gate electrodes of the third PMOS transistor and the third NMOS transistor (at Output), and serve as an output end of the signal amplification shaping circuit (at Output).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the Schmitt trigger circuit of Wu as the Schmitt trigger circuit of Guimont to provide ESD protection and increase circuit reliability ([0005]).
Guimont and Wu do not specifically teach the details of the inverter 318 (Figure 3 of Guimont).
Hung teaches an inverter connected to the output of a Schmitt trigger circuit (P3, N3 coupled to the output of 315; Figure 3) comprising a fourth PMOS transistor (P3) and a fourth NMOS transistor (N3) where the gate electrodes of the third PMOS transistor (P3 to Output of Wu) and the third NMOS transistor (N3 to Output of Wu) are connected to gate electrodes of the fourth PMOS transistor (P3 of Hung) and the fourth NMOS transistor (N3 of Hung); and
drain electrodes of the fourth PMOS transistor (P3 of Hung) and the fourth NMOS transistor (N3 of Hung) are connected to each other (at the output of the inverter) and serve as the output end of the signal amplification shaping circuit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the inverter taught by Hung in the circuit of Guimont and Wu to provide a well-known inverter topology.
Claim 7: The combined circuit further teaches a source electrode of the first PMOS transistor (P1 of Wu) is connected to a power supply terminal (VDD), and a drain electrode of the first PMOS transistor (P1) is connected to source electrodes of the second PMOS transistor (P2) and the third PMOS transistor (P3);
a drain electrode of the first NMOS transistor (N2) is connected to source electrodes of the second NMOS transistor (N1) and the third NMOS transistor (N3); a source electrode of the first NMOS transistor (N2) is connected to a ground terminal (VSS);
after being connected to the first resistor (110) in series, a drain electrode of the third PMOS transistor (P3) is connected to the ground terminal (VSS);
after being connected to the second resistor (120) in series, a drain electrode of the third NMOS transistor (N3) is connected to the power supply terminal (VDD);
a source electrode of the fourth PMOS transistor (P3 of Hung) is connected to the power supply terminal (VDD); and a source electrode of the fourth NMOS transistor (N3 of Hung) is connected to the ground terminal (VSS).
Claim 8: Guimont teaches the limitations of claim 1 above. Guimont further teaches two-level shaping circuits (322 and 332). Guimont does not specifically teach the details of inverter circuits 322, 332.
Hung teaches well-known inverter topology in a power-on reset circuit (P3 and N3 form an inverter). Therefore, the combined circuit teaches the output driving circuit is formed by two-level shaping circuits (322 and 332 of Guimont each comprising P3 and N3 of Hung), wherein a first-level shaping circuit is formed by a fifth PMOS transistor (P3 of Hung in 322 of Guimont) and a fifth NMOS transistor (N3 of Hung in 322 of Guimont), and a second-level shaping circuit is formed by a sixth PMOS transistor (P3 of Hung in 332 of Guimont) and a sixth NMOS transistor (N3 of Hung in 332 of Guimont);
gate electrodes of the fifth PMOS transistor and the fifth NMOS transistor (forming the input of inverter 322) are connected to an output end of the signal amplification shaping circuit (connected to 319 via 320 of Guimont);
drain electrodes of the fifth PMOS transistor and the fifth NMOS transistor (forming the output of inverter 322) are connected to gate electrodes of the sixth PMOS transistor and the sixth NMOS transistor (forming the input of inverter 332);
source electrodes of the fifth PMOS transistor and the sixth PMOS transistor (P3 of Hung in each of 322 and 332 of Guimont) are connected to a power supply terminal (VDD);
the source electrodes of the fifth NMOS transistor and the sixth NMOS transistor (N3 of Hung in each of 332 and 332 of Guimont) are connected to a ground terminal (VSS); and
drain electrodes of the sixth PMOS transistor and the sixth NMOS transistor (forming the output of inverter 332) are connected to each other, and serve as an output end of the power-on reset signal (NPOR via 334 of Guimont).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the inverter taught by Hung in the circuit of Guimont and Wu to provide a well-known inverter topology.
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art does not fairly teach or suggest a source electrode of the PMOS transistor is connected to one end of the first capacitor, a drain electrode of the PMOS transistor is used as an output end of the dynamic response enhancement circuit, and a gate electrode of the PMOS transistor is connected to an output end of a first-level shaping circuit of the output driving circuit; and another end of the first capacitor is connected to a power supply terminal in combination with the limitations of claim 2.
Claims 3-5 are objected to merely for being dependent on claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
International Search Report and International Preliminary Report on Patentability for PCT/CN2023/128807 and associated references CN115987259A, CN102111136A, CN102403988A, CN104682931 and CN113821068A.
Conclusion
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
