Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6-9, 14-16, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (PGPUB 2026/0065860 A1) in view of Lin et al (PGPUB 2020/0226978 A1).
As to claim 1, Yamamoto (Figs. 1, 7, 10) teaches, a light emitting display apparatus (display device 10), comprising:
a light emitting display panel (display portion 11) including a pixel driving circuit (pixel circuit 15a) and a light emitting device (organic EL element OL)(¶ 102); and
a gate driver (scanning-side drive circuit 40) configured to supply gate signals 9scanning signals NS 1-n) to the pixel driving circuit (¶ 96),
wherein the pixel driving circuit includes:
a first light emitting transistor (first light emission control transistor T6) connected to the light emitting device (¶ 102);
a driving transistor (driving transistor T4) connected to the first light emitting transistor (¶ 102, Fig. 7);
a first switching transistor (threshold compensation transistor T2) connected to a gate electrode (i.e. via voltage node Vg in Fig. 7) of the driving transistor
and a first terminal (i.e. upper terminal of T4) of the driving transistor (¶ 122, Fig. 7); and
a second switching transistor (write control transistor T3) connected to a first node (i.e. node connecting to lower terminal of T4, right terminal of T3 and upper terminal of T6) between the driving transistor and the first light emitting transistor (Fig. 7),
wherein during a use of the light emitting display apparatus, a period (refresh frame period Trf)(¶ 98) and at least one anode reset period (anode reset period / anode initialization period / display element initialization period)(¶ 106),
wherein the second switching transistor is configured to be turned on only during the at least one refresh period (Fig. 5: i.e. NS2 is applied only during Trf in the embodiment shown in Fig. 10), and
wherein the first switching transistor is formed of an oxide semiconductor ( 103: i.e. T1-T6 are oxide semiconductor transistor).
Yamamoto does not specifically teach “one second” is divided into at least one refresh period and at least one anode reset period.
Lin (Fig. 3) teaches, “one second” (i.e. refresh rate of 1Hz; ¶ 10, which yields of 1 second per frame period) is divided into at least one refresh period and at least one anode reset period (¶ 66, Figs. 4 and 9: Fig. 9 shows a frame with T_refresh period and T_blank period. Fig. 4 shows a portion of T_refresh period).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
As to claim 2, Yamamoto (Fig. 3) teaches, wherein each of the second switching transistor and the first light emitting transistor is formed of a polycrystalline semiconductor (¶ 173: i.e. transistors are polysilicon).
As to claim 3, Yamamoto (Fig. 10) teaches, wherein the gate driver is configured to turn on the first light emitting transistor M times per second (i.e. EM1 is turned on multiple times during a frame Trf and Tnrf and two times during Trf) and to turn on the second switching transistor once only during the at least one refresh period, wherein M is a natural number of 2 or more (Fig. 10: i.e. NS2 is turned on only once during Trf and Trf+Tnrf).
As to claim 4, Yamamoto (Fig. 10) teaches, wherein:
the first light emitting transistor (T6) is configured to be turned on once during the at least one refresh period (Fig. 5: EM1 is turned on during Trf), and
the first light emitting transistor is configured to be turned on M-1 times during the at least one anode reset period, wherein M is a natural number of 2 or more (Fig. 5: i.e. EM1 is turned on at least once, where M is 2).
As to claim 6, Yamamoto (Fig. 7) teaches, wherein the second switching transistor is connected between the first node and a data line (data signal line Dj) to which a data voltage (data signal D(j)) is supplied (¶ 128, Fig. 7).
As to claim 7, Yamamoto (Fig. 7) teaches, wherein:
a first voltage (high level power supply line ELVDD) is supplied to a first electrode (i.e. upper terminal as shown in Fig. 7) of the driving transistor, and a second electrode (i.e. lower terminal) of the driving transistor is connected to the first node (Fig. 7), and
the pixel driving circuit further comprises:
a second light emitting transistor (second light emission control transistor T5), a first electrode (i.e. upper terminal as shown in Fig. 7) of the second light emitting transistor being connected to a first voltage line (i.e. line for providing ELVDD) to which the first voltage is supplied, and a second electrode (i.e. lower terminal) of the second light emitting transistor being connected to the first electrode of the driving transistor (Fig. 7); and
an initialization transistor (first initialization transistor T1), a first electrode (i.e. upper terminal) of the initialization transistor being connected to the light emitting device (i.e. via Va in Fig. 7), and a second electrode (i.e. lower terminal) of the initialization transistor being connected to an initialization line (line Initialization voltage line Lini) to which an initialization voltage (initialization voltage) or a compensation voltage (i.e. initialization voltage compensates transistor state by initializing) is supplied (¶ 93)(Fig. 7).
As to claim 8, Yamamoto teaches the light emitting display apparatus of claim 7 but does not specifically teach wherein the first light emitting transistor and the second light emitting transistor are P-type transistors, and the initializing transistor is an N-type transistor.
Lin (Fig. 3) teaches, wherein the first light emitting transistor and the second light emitting transistor are P-type transistors (i.e. Tem1 and Tem2 are P-type transistors), and the initializing transistor is an N-type transistor (¶ 56: i.e. Tini2 is N-type transistor).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
As to claim 9, Yamamoto (Fig. 21) teaches, wherein the initialization transistor is turned on (i.e. via NS4 in the embodiment as shown in Fig. 20) when the first light emitting transistor is turned off in the at least one anode reset period (Fig. 21: i.e. when NS4 is on during Tanr, EM1 Is off to turn off T6).
As to claim 14, Yamamoto (Fig. 1) teaches, wherein:
each of the driving transistor and the first switching transistor is formed of an oxide semiconductor (¶ 173: i.e. transistors can be polycrystalline), and
each of the second switching transistor, the first light emitting transistor, the second light emitting transistor, and the initializing transistor is formed of a polycrystalline semiconductor (¶ 173: i.e. transistors can be polycrystalline).
As to claim 15, Yamamoto (Fig. 7) teaches, the pixel driving circuit further comprises
an initialization transistor (first initialization transistor T1), a first electrode (i.e. upper terminal) of the initialization transistor being connected to the light emitting device (i.e. via Va in Fig. 7), and a second electrode (i.e. lower terminal) of the initialization transistor being connected to an initialization line (line. Initialization voltage line Lini) to which an initialization voltage (initialization voltage) or a compensation voltage (i.e. initialization voltage compensates transistor state by initializing) is supplied (¶ 93)(Fig. 7).
As to claim 16, Yamamoto teaches light emitting display apparatus of claim 15 but does not specifically teach, wherein the initialization transistor is turned on when the first light emitting transistor is turned off in the at least one anode reset period.
Lin (Fig. 4) teaches, wherein the initialization transistor is turned on when the first light emitting transistor is turned off in the at least one anode reset period (Fig. 4: i.e. during the time period t2 and t3, SCAN2(n-1) is at low logic to turn on Tini2 and EM(n) is at high logic to turn off Tem2).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
As to claim 19, Yamamoto (Fig. 10) teaches, wherein:
in the at least one refresh period, a data voltage (D(j)) is supplied to the driving transistor through a data line (Dj) provided in the light emitting display panel, the second switching transistor, and the first node, and light is output from the light emitting device on a basis of a magnitude of the data voltage (Fig. 8 (B) data writing scenario), and
in the at least one anode reset period, the first light emitting transistor is repeatedly turned on and off (Fig. 10: i.e. EM1 is turned on and off during Tnrf), and light is output from the light emitting device (light emission period Tem extends into Tnrf as shown in Fig. 10).
As to claim 20, Yamamoto (Fig. 6) teaches, wherein the at least one anode reset period is longer than the at least one refresh period (¶ 100, Fig. 6: i.e. duration of refresh period is represented as ACT in Fig. 6. Duration of anode initialization is represented as HiZ in Fig. 10 and ANR in fig. 6. The duration of ANR is represented as about 20 ms in Fig. 6, which is longer than 8ms Trf).
Claim(s) 10-13, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto and Lin as applied to claim 8 above, and further in view of Kim et al (PGPUB 2023/0104904 A1).
As to claim 10, Yamamoto teaches the light emitting display apparatus of claim 8 but does not specifically teach compensation voltage.
Lin (Figs. 10, 16) teaches, wherein: in the at least one anode reset period (anode reset), when the initialization transistor is turned on, a compensation voltage (i.e. anode reset voltage Var before adjustment) is supplied to the light emitting device through the initialization transistor (¶ 103, 107: anode reset voltage Var is provided at the end of end of t5 and adjusted at time t6).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
Lin further teaches two different anode reset voltages can be applied but does not specifically teach, the compensation voltage is different from the initialization voltage supplied to the light emitting device through the initialization transistor in the at least one refresh period.
Kim (Fig. 14) teaches, the compensation voltage (i.e. anode initialization voltage VAINTa at second voltage level V2) is different from the initialization voltage (i.e. anode initialization voltage VAINTa at first voltage level V1) supplied to the light emitting device through the initialization transistor in the at least one refresh period (¶ 160, 161).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel driving method into Yamamoto’s display as modified with the teaching of Lin, so as to reduce power consumption (¶ 5) and improve contrast ratio (¶ 127).
As to claim 11, Yamamoto teaches the light emitting display apparatus of claim 10 but does not specifically teach the compensation voltage.
Lin (Fig. 16) teaches, wherein the compensation voltage is set to a voltage that does not affect a luminance of light output from the light emitting device or a value that has a minimal effect on the luminance of light output from the light emitting device (¶ 107: i.e. adjusted Var is to reduce any mismatch between the active and blanking periods).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
As to claim 12, Yamamoto and Lin teach the light emitting display apparatus of claim 10 but does not specifically teach the compensation voltage is supplied to the light emitting device just before the light is output from the light emitting device.
Kim (Fig. 14) teaches, wherein the compensation voltage (i.e. VAINTa at V2) is supplied to the light emitting device just before the light is output from the light emitting device (Fig. 6: i.e. light emission period at the end of a frame Fs, and VAINTa at V2 is supplied near the end of the frame in F2 in Fig. 14).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel driving method into Yamamoto’s display as modified with the teaching of Lin, so as to reduce power consumption (¶ 5) and improve contrast ratio (¶ 127).
As to claim 13, Yamamoto and Lin teach the light emitting display apparatus of claim 10 but does not specifically teach the compensation voltage is greater than the initialization voltage.
Kim (Fig. 14) teaches, wherein the compensation voltage (V2) is greater than the initialization voltage (Fig. 14: i.e. V2 is higher than V1).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel driving method into Yamamoto’s display as modified with the teaching of Lin, so as to reduce power consumption (¶ 5) and improve contrast ratio (¶ 127).
As to claim 17, Yamamoto teaches the light emitting display apparatus of claim 16 but does not specifically teach the compensation voltage is different from the initialization supplied to the light emitting device through the initialization transistor in the at least one refresh period.
Lin (Figs. 10, 16) teaches, wherein: when the initialization transistor is turned on, the compensation voltage (i.e. anode reset voltage Var before adjustment) is supplied to anode of the light emitting device through the initialization transistor (¶ 103, 107: anode reset voltage Var is provided at the end of end of t5 and adjusted at time t6).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Lin’s driving method into Yamamoto’s display device, so as to improve reliability of the oxide transistor (¶ 76).
Lin further teaches two different anode reset voltages can be applied but does not specifically teach, the compensation voltage is different from the initialization voltage supplied to the light emitting device through the initialization transistor in the at least one refresh period.
Kim (Fig. 14) teaches, the compensation voltage (i.e. anode initialization voltage VAINTa at second voltage level V2) is different from the initialization voltage (i.e. anode initialization voltage VAINTa at first voltage level V1) supplied to the anode of the light emitting device through the initialization transistor in the at least one refresh period (¶ 160, 161).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel driving method into Yamamoto’s display as modified with the teaching of Lin, so as to reduce power consumption (¶ 5) and improve contrast ratio (¶ 127).
As to claim 18, Yamamoto teaches the light emitting display apparatus of claim 1 but does not teach when the first light emitting transistor is turned off in the at least one anode reset period, a compensation voltage is supplied to the light emitting device, and the compensation voltage is different from an initialization voltage supplied to the light emitting device in the at least one refresh period.
Lin (Figs. 15, 16) teaches, when the first light emitting transistor is turned off in the at least one anode reset period, a compensation voltage (Var) is supplied to the light emitting device (i.e. EM is high when Var is applied)(Figs. 15, 16).
Lin does not specifically teach the compensation voltage is different from an initialization voltage supplied to the light emitting device in the at least one refresh period.
Kim (Fig. 14) teaches, the compensation voltage is different from an initialization voltage supplied to the light emitting device in the at least one refresh period
(Fig 14: i.e. V2 and V1 can be applied as VAINTa).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Kim’s pixel driving method into Yamamoto’s display as modified with the teaching of Lin, so as to reduce power consumption (¶ 5) and improve contrast ratio (¶ 127).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/SANGHYUK PARK/Primary Examiner, Art Unit 2623