CTNF 19/245,824 CTNF 90564 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Note It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Information Disclosure Statement 06-52 An information disclosure statement (IDS) was submitted on 23 June 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto- processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-22 rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12340100 and claims 1-32 of U.S. Patent No. 11861190 . Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the limitations of the Patent/Copending Application would anticipate those of the current application as shown in the example claims in the table below . Instant Application U.S. Patent No. 12340100 1. A system comprising: first memory; a controller indirectly connected to the first memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function; and a processor connected between the first memory and the controller, the processor being configured to reconfigure a first map before and during performance of the at least one function by the controller, the reconfiguring of the first map including changing i) a first allocated portion of the first memory for program instructions, and ii) a second allocated portion of the first memory for the data, and based on the first map, i) route the program instructions and the data between the controller and the first memory, ii) store the program instructions at addresses of the first memory allocated for the program instructions, and iii) store the data at addresses of the first memory allocated for the data. 1. A system comprising: first memory; a controller configured to receive program instructions to program the controller to perform at least one function, and handle data as a result of performing the at least one function; and a processor configured to perform an initial configuration of a first map to proportion the first memory including allocating a first portion of the first memory for the program instructions and a second portion of the first memory for the data, the first map being indicative of addresses of the first portion and other addresses of the second portion, subsequent to performing the initial configuration, reconfigure the first map to change an amount of the first memory allocated for the program instructions and an amount of the first memory allocated for the data, and prior to and subsequent to reconfiguring the first map and based on the first map, route the program instructions and the data between the controller and the first memory, store the program instructions at the addresses of the first memory allocated for the program instructions, and store the data at the addresses of the first memory allocated for the data. Instant Application U.S. Patent No. 11861190 1. A system comprising: first memory; a controller indirectly connected to the first memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function; and a processor connected between the first memory and the controller, the processor being configured to reconfigure a first map before and during performance of the at least one function by the controller, the reconfiguring of the first map including changing i) a first allocated portion of the first memory for program instructions, and ii) a second allocated portion of the first memory for the data, and based on the first map, i) route the program instructions and the data between the controller and the first memory, ii) store the program instructions at addresses of the first memory allocated for the program instructions, and iii) store the data at addresses of the first memory allocated for the data. 1. A system comprising: first memory; a controller configured to generate memory access instructions indicating addresses of the first memory to access for transfers of data, the data not being memory access instructions; and a processor connected between the first memory and the controller and configured to perform an initial configuration of at least one map to allocate selected addresses of the first memory for the memory access instructions and allocate other selected addresses of the first memory for the data, the map being indicative of the addresses of the first memory allocated for the memory access instructions and the other selected addresses of the first memory allocated for the data, subsequent to performing the initial configuration, reconfigure the at least one map to change allocations of addresses of the first memory for the memory access instructions and for the data, to change a proportion of the first memory allocated for the memory access instructions in relation to an amount of the first memory allocated for the data, the at least one map being indicative of addresses of the first memory allocated for the memory access instructions and addresses of the first memory allocated for the data due to the change in the proportion of the first memory, and prior to and subsequent to reconfiguring the at least one map and based on the at least one map, route the memory access instructions and the data that is not memory access instructions between the controller and the first memory, store the memory access instructions only at selected addresses of the first memory allocated to memory access instructions and store the data that is not instructions only at selected addresses of the first memory allocated to data. A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804 Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-6 and 10-2 0, and 22 is/are re jected under 35 U.S.C. 102(a)(1)/( a)(2) as being a nticipa ted by Smith ( US 20170315755 A1). Referrin g to claims 1 and 22, taking claim 1 as exemplary, Smith teaches A system comprising: first memory; ([Smith 0028, 0034, Fig. 1] The embedded system 100 comprises a core memory 104 for storing the computer executable instructions and the data elements of the program; and a processor 106 for executing the stored computer executable instructions which cause the processor 106 to access (e.g. write to, and read from) the stored data elements.) a controller indirectly connected to the first memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function; ([Smith 0028, 0034, 0082, Fig. 1, 5] The embedded system 100 comprises a core memory 104 for storing the computer executable instructions and the data elements of the program; and a processor 106 for executing the stored computer executable instructions which cause the processor 106 to access (e.g. write to, and read from) the stored data elements. The processor 106 is configured to execute the computer executable instructions 122 stored in the core memory 104 which causes the processor 106 to access (e.g. write to or read from) the data elements 124 stored in the core memory 104. The processor 106 may be a microprocessor, controller or any other suitable type of processor for processing computer executable instructions to control the operation of the embedded system 100. Computing-based device 500 comprises one or more processors 502 which may be microprocessors, controllers or any other suitable type of processors for processing computer executable instructions to control the operation of the device in order to generate executable code in accordance with the methods and systems described herein. In some examples, for example where a system on a chip architecture is used, the processors 502 may include one or more fixed function blocks (also referred to as accelerators) which implement a part of the methods described herein in hardware (rather than software or firmware). Platform software comprising an operating system 504 or any other suitable platform software may be provided at the computing-based device to enable application software (e.g. a compiler or linker) to be executed on the device.) and a processor connected between the first memory and the controller, the processor being configured to ([Smith 0028, 0034, Fig. 1] The embedded system 100 comprises a core memory 104 for storing the computer executable instructions and the data elements of the program; and a processor 106 for executing the stored computer executable instructions which cause the processor 106 to access (e.g. write to, and read from) the stored data elements.) reconfigure a first map before and during performance of the at least one function by the controller, ([Smith 0059-0060] In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks.) the reconfiguring of the first map including changing i) a first allocated portion of the first memory for program instructions, and ii) a second allocated portion of the first memory for the data, ([Smith 0059-0060, 0072-0073] In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks. By using the linker script generator 306 to generate a linker script 316 that causes the linker 304 to allocate regular data elements addresses in a non-instruction memory block; and allocate non-regular data elements addresses in an instruction memory block, the programmer can simply identify data elements which can be placed in instruction memory blocks (e.g. by identifying them as low priority data elements) and leave the linker script generator 306 to identify the appropriate mappings between the data elements and addresses of the core memory.) and based on the first map, i) route the program instructions and the data between the controller and the first memory, ii) store the program instructions at addresses of the first memory allocated for the program instructions, and iii) store the data at addresses of the first memory allocated for the data ([Smith abstract, 0008, 0031, 0072-0073, Fig. 1,4] A method of storing computer executable instructions and data elements of a program in a plurality of memory blocks of an embedded system. The method includes receiving object code that comprises instructions that symbolically refer to one or more data elements; metadata that identifies the data elements in the object code; and a data element description that identifies each of the data elements as either a regular data element or a non-regular data element. Executable code is generated based the object code, metadata and the data element description that comprises computer executable instructions that refer to the data elements using an address in the memory, wherein the regular data elements are referenced by an address in a non-instruction memory block of the plurality of memory blocks and the non-regular data elements are referenced by an address in an instruction memory block. The executable code is then loaded into the memory of the embedded system. A second aspect provides a system to store computer executable instructions and data elements of a program in a memory of an embedded system, the memory being divided into a plurality of memory blocks, the system comprising: a linker script generator configured to: receive object code comprising instructions that symbolically refer to one or more data elements; receive metadata that identifies the data elements in the object code; receive a data element description that identifies each of the data elements as either a regular data element or a non-regular data element; and generate a linker script to cause a linker to allocate non-regular data elements an address in an instruction memory block of the plurality of memory blocks and to allocate regular data elements an address in a non-instruction memory block of the plurality of memory blocks; a linker configured to: generate, based on the object code, the metadata and the linker script, executable code that comprises computer executable instructions that refer to the one or more data elements using an address of the memory, wherein the regular data elements are referenced by an address in a non-instruction memory block of the plurality of memory blocks and the non-regular data elements are referenced by an address in an instruction memory block of the plurality of memory blocks; and a loader configured to load the executable code into the memory of the embedded system. When the processor 106 is executing the program (via the stored computer executable instructions) there will be many clock cycles in which the processor 106 will want to access both an instruction and a data element stored in the core memory 104. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests.) . Referring to claim 2, Smith teaches The system of claim 1, wherein the first map is indicative of addresses of the first allocated portion and other addresses of the second allocated portion ([Smith 0072-0073, Fig. 1, 4] By using the linker script generator 306 to generate a linker script 316 that causes the linker 304 to allocate regular data elements addresses in a non-instruction memory block; and allocate non-regular data elements addresses in an instruction memory block, the programmer can simply identify data elements which can be placed in instruction memory blocks (e.g. by identifying them as low priority data elements) and leave the linker script generator 306 to identify the appropriate mappings between the data elements and addresses of the core memory.) . Referring to claim 3, Smith teaches The system of claim 1, wherein: during an initial configuration, the processor is configured to configure the first map to allocate first addresses for the program instructions and allocate second addresses for the data; and subsequent to performing the initial configuration and while reconfiguring the first map, the processor is configured to allocate third addresses for the program instructions and allocate fourth addresses for the data ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 4, Smith teaches The system of claim 3, wherein: the third addresses at least one of i) include at least one different address than the first addresses, and ii) do not include at least one address of the first addresses; and the fourth addresses at least one of i) include at least one different address than the second addresses, and ii) do not include at least one address of the second addresses ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 5, Smith teaches The system of claim 1, wherein the controller is configured, when performing the at least one function, to at least one of i) store the data at the addresses of the first memory allocated for the data, ii) retrieve the data from the addresses of the first memory allocated for the data, and iii) modify the data ([Smith 0030, 0032] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block.) . Referring to claim 6, Smith teaches The system of claim 1, further comprising: a first port defining a first channel dedicated to transferring the program instructions; and a second port defining a second channel dedicated to transferring the data, wherein the processor is configured to receive the program instructions from the first memory via the first channel, and to transfer the data between the controller and the processor via the second channel ([Smith 0031, 0058-0060, Fig. 1] When the processor 106 is executing the program (via the stored computer executable instructions) there will be many clock cycles in which the processor 106 will want to access both an instruction and a data element stored in the core memory 104. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests. In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks.) . Referring to claim 10, Smith teaches The system of claim 1, wherein the processor is configured to reconfigure the first map to change a total number of addresses of the first memory allocated for the program instructions and a total number of the addresses of the first memory allocated for the data ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 11, Smith teaches The system of claim 1, wherein: the first memory comprises a plurality of memory blocks; and the first map maps addresses of the first memory to local addresses of the plurality of memory blocks ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 12, Smith teaches The system of claim 1, wherein the processor is configured to receive a first configuration signal from a configuration line and, based on the first configuration signal, to configure the first map to allocate the addresses of the first memory allocated for the program instructions and allocate the addresses of the first memory allocated for the data ([Smith 0031, 0058-0060, Fig.1] When the processor 106 is executing the program (via the stored computer executable instructions) there will be many clock cycles in which the processor 106 will want to access both an instruction and a data element stored in the core memory 104. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests. In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks.) . Referring to claim 13, Smith teaches The system of claim 12, wherein the processor is configured to at least one of: based on the first configuration signal, allocate a first amount of the first memory for storing the program instructions and to allocate a second amount of the first memory for storing the data, the first configuration signal indicative of the first amount of the first memory and the second amount of the first memory; and receive a second configuration signal from the configuration line and, based on the second configuration signal, reconfigure the first map to change the first amount of the first memory allocated for the program instructions and to change the second amount of the first memory allocated for the data ([Smith 0031, 0058-0060, Fig. 1] When the processor 106 is executing the program (via the stored computer executable instructions) there will be many clock cycles in which the processor 106 will want to access both an instruction and a data element stored in the core memory 104. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests. In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks.) . Referring to claim 14, Smith teaches The system of claim 1, wherein: the first memory comprises a plurality of memory blocks; the processor is configured to configure a plurality of maps, the plurality of maps comprising the first map; each of the plurality of maps is allocated to a respective one of the plurality of memory blocks, a one-to-one relationship exists between the plurality of maps and the plurality of memory blocks; and each of the plurality of maps mapping corresponding ones of addresses of the first memory to local addresses within a respective one of the plurality of memory blocks ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 15, Smith teaches The system of claim 1, wherein: the first memory comprises a plurality of memory blocks; and the processor is configured to selectively configure the first map to allocate selected ones of the plurality of memory blocks for storing information provided in the program instructions and to allocate other selected ones the plurality of memory blocks for storing the data ([Smith 0030, 0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle.) . Referring to claim 16, Smith teaches The system of claim 1, wherein the processor is configured i) to receive a configuration signal from a configuration line and, ii) based on the configuration signal, to configure the first map to be in a configuration selected from among a plurality of possible configurations, each of the plurality of possible configurations allocating addresses of the first memory for the program instructions and the data differently, and each of the plurality of possible configurations allocating in different proportions a respective number of addresses of the first memory for the program instructions and a respective number of addresses for the data ([Smith 0031, 0058-0060, Fig. 1] When the processor 106 is executing the program (via the stored computer executable instructions) there will be many clock cycles in which the processor 106 will want to access both an instruction and a data element stored in the core memory 104. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests. In the embodiments described herein a linker script generator 306 generates a linker script that causes the linker 304 to map the regular data elements to non-instruction memory blocks and the non-regular data elements (e.g. low-priority data elements) to instruction memory blocks.) . Referring to claim 17, Smith teaches The system of claim 1, wherein: the first memory comprises a plurality of memory blocks; and the processor comprises a plurality of cross-points and is configured i) to receive a configuration signal from a configuration line separate from the system, and ii) based on the configuration signal, to at least one of set or control the plurality of cross-points, the plurality of cross-points being configured to enable selective routing of the program instructions and the data between the controller and the plurality of memory blocks ([Smith 0095-0096] In other examples, processing of the integrated circuit definition dataset at an integrated circuit manufacturing system may configure the system to manufacture an embedded system without the IC definition dataset being processed so as to determine a circuit layout. For instance, an integrated circuit definition dataset may define the configuration of a reconfigurable processor, such as an FPGA, and the processing of that dataset may configure an IC manufacturing system to generate a reconfigurable processor having that defined configuration (e.g. by loading configuration data to the FPGA). In some embodiments, an integrated circuit manufacturing definition dataset, when processed in an integrated circuit manufacturing system, may cause an integrated circuit manufacturing system to generate a device as described herein. For example, the configuration of an integrated circuit manufacturing system in the manner described above with respect to FIG. 6 by an integrated circuit manufacturing definition dataset may cause an embedded system as described herein to be manufactured.) . Referring to claim 18, Smith teaches The system of claim 17, wherein the plurality of cross-points comprise at least one of configuration pins, integrated programmable fuses, or configuration registers ([Smith 0102] A particular reference to “logic” refers to structure that performs a function or functions. An example of logic includes circuitry that is arranged to perform those function(s). For example, such circuitry may include transistors and/or other hardware elements available in a manufacturing process. Such transistors and/or other elements may be used to form circuitry or structures that implement and/or contain memory, such as registers, flip flops, or latches, logical operators, such as Boolean operations, mathematical operators, such as adders, multipliers, or shifters, and interconnect, by way of example. Such elements may be provided as custom circuits or standard cell libraries, macros, or at other levels of abstraction. Such elements may be interconnected in a specific arrangement. Logic may include circuitry that is fixed function and circuitry can be programmed to perform a function or functions; such programming may be provided from a firmware or software update or control mechanism. Logic identified to perform one function may also include logic that implements a constituent function or sub-process. In an example, hardware logic has circuitry that implements a fixed function operation, or operations, state machine or process.) . Referring to claim 19, Smith teaches The system of claim 1, wherein: the first memory comprises a plurality of memory blocks; the plurality of memory blocks are implemented as a plurality of integrated circuits such that each of the plurality of memory blocks is a distinct memory chip; and the processor comprises a plurality of ports configured to transfer the program instructions and the data between the processor and the plurality of memory blocks data ([Smith 0030-0032 0073, Fig. 1] To reduce access (i.e. read and write) time, the core memory 104 is divided or partitioned into memory blocks 108, 110, 112, 114, 116 (e.g. 64 kB (kilobyte) blocks). Each memory block represents a subset of the total core memory 104. The memory blocks 108, 110, 112, 114 and 116 may be the same size or may be different sizes. The memory blocks 108, 110, 112, 114 and 116 may form a contiguous block of memory; or the memory blocks 108, 110, 112, 114 and 116 may be separated from each other by other memory, modules or components. In the example shown in FIG. 1, the core memory 104 is divided into five equal-sized memory blocks 108, 110, 112, 114, 116 that form a contiguous block. However, it will be evident to a person of skill in the art that this is an example only and that the core memory 104 may be divided into more or fewer memory blocks and may not be contiguous. Since each memory block 108, 110, 112, 114 and 116 can typically only process one access request (e.g. a request to read or write) per clock cycle the computer executable instructions 122 and the data elements 124 are stored in separate memory blocks 108, 110, 112, 114, and 116. In the example of FIG. 1, the computer executable instructions 122 are stored in the first and second memory blocks 108 and 110 and the data elements 124 are stored in the third, fourth and fifth memory blocks 112, 114 and 116. By storing the computer executable instructions 122 in different memory blocks from the data elements 124, no instruction—data element pair will be stored in the same memory block. Accordingly no combination of instruction access request and data element access request cycle will conflict (i.e. attempt to access the same memory block in the same clock cycle). This guarantees that any combination of instruction access request and data element access request will be able to be processed in the same clock cycle. To allow the processor 106 to issue both an instruction access request and a data access request to the core memory 104 in the same clock cycle there are two paths or buses 118 and 120 between the processor 106 and the core memory 104. For example, in FIG. 1 there is an instruction path 118 for sending instruction access requests and a data path 120 for sending data access requests.) . Referring to claim 20, Smith teaches The system of claim 1, further comprising a single printed circuit board, wherein the first memory, the controller and the processor are mounted on the single printed circuit board ([Smith 0012-0013] The embedded system may be embodied in hardware on an integrated circuit. There may be provided a method of manufacturing, at an integrated circuit manufacturing system, an embedded system. There may be provided an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the system to manufacture an embedded system. There may be provided a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed, causes a layout processing system to generate a circuit layout description used in an integrated circuit manufacturing system to manufacture an embedded system.) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim (s) 7-9 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smith (US 20170315755 A1) as applied to claim 1 and 6 above, and further in view of Zamir (US 20190164610 A1) . Referring to claim 7, Smith teaches The system of claim 6 ([see above]) . Smith does not explicitly disclose further comprising a plurality of channels separate from the first port, the second port, the first channel and the second channel and transferring the program instructions and the data between the processor and the first memory. Zamir teaches further comprising a plurality of channels separate from the first port, the second port, the first channel and the second channel and transferring the program instructions and the data between the processor and the first memory ([Zamir 0051, 0084, Fig. 6A-6C] non-volatile memory system 100 includes a single channel between Controller 122 and non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the Controller and the memory die, depending on Controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the Controller and the memory die, even if a single channel is shown in the drawings. FIG. 6A illustrates an example of a non-volatile memory controller, controller 600, that includes an ECC decoder 610 between a host interface 606 and a memory interface 608. ECC decoder 610 is coupled to a dual-port memory 612 (dual-port RAM) so that data generated by ECC decoder 610 when iteratively decoding data may be written and read rapidly. A dual-port memory allows data to be written via one port while data is read via the other port. For example, on a given clock cycle, ECC decoder may write data in dual-port memory 612 through Port A and read data from dual-port memory 612 through Port B. Data stored in dual-port memory 612 is equally accessible through either port so that data can be written to any address in dual-port memory 612 through Port A while any other data in dual-port memory 612 may be read in parallel through Port B. Such parallel access provides high access speeds for a given clock frequency. The term “dual-port” may refer to a memory having two ports where each port can read or write. In contrast, “two-port” may refer to a memory having two ports where one port is a dedicated write port and the other port is a dedicated read port. It will be understood that controller 600 may be implemented with a two-port memory or dual-port memory.) . Smith and Zamir are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Smith and Zamir before him or her to modify the system of Smith to include the multiport/multichannel memory of Zamir, thereafter the system is connected to multiport/multichannel memory. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more flexibility in configuring the memory for access to serve customer and system needs as suggested by Zamir. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Smith with Zamir to obtain the invention as specified in the instant application claims. Referring to claim 8, Smith teaches The system of claim 6 ([see above]) . Smith does not explicitly disclose wherein the processor comprises a plurality of connection points through which the program instructions and the data pass between the controller and the first memory, the plurality of connection points being separate from the first port, the second port, the first channel and the second channel. Zamir wherein the processor comprises a plurality of connection points through which the program instructions and the data pass between the controller and the first memory, the plurality of connection points being separate from the first port, the second port, the first channel and the second channel ([Zamir 0051, 0078, 0084-0086, Fig. 6A-6C] In some embodiments, non-volatile memory system 100 includes a single channel between Controller 122 and non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the Controller and the memory die, depending on Controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the Controller and the memory die, even if a single channel is shown in the drawings. One example of a ReRAM memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. Data stored in dual-port memory 612 is equally accessible through either port so that data can be written to any address in dual-port memory 612 through Port A while any other data in dual-port memory 612 may be read in parallel through Port B. Such parallel access provides high access speeds for a given clock frequency. The term “dual-port” may refer to a memory having two ports where each port can read or write. In contrast, “two-port” may refer to a memory having two ports where one port is a dedicated write port and the other port is a dedicated read port. It will be understood that controller 600 may be implemented with a two-port memory or dual-port memory.) . Smith and Zamir are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Smith and Zamir before him or her to modify the system of Smith to include the multiport/multichannel memory of Zamir, thereafter the system is connected to multiport/multichannel memory. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more flexibility in configuring the memory for access to serve customer and system needs as suggested by Zamir. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Smith with Zamir to obtain the invention as specified in the instant application claims. Referring to claim 9, Smith teaches The system of claim 6 ([see above]) . Smith does not explicitly disclose wherein: the first memory comprises a plurality of distinct memories; and the processor comprises a two-dimensional array of configurable cross-points connected between i) the first port and the second port, and ii) the first memory, the two-dimensional array of configurable cross-points configured to enable selective routing of the program instructions and the data between the controller and the plurality of distinct memories. Zamir teaches wherein: the first memory comprises a plurality of distinct memories; and the processor comprises a two-dimensional array of configurable cross-points connected between i) the first port and the second port, and ii) the first memory, the two-dimensional array of configurable cross-points configured to enable selective routing of the program instructions and the data between the controller and the plurality of distinct memories ([Zamir 0046, 0077-0078, 0086] As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in they direction) with each column having multiple memory cells. The vertical columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory cells, with memory cells on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array. Although the example memory system of FIGS. 4-4F is a three-dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein. For example, floating gate memories (e.g., NAND-type and NOR-type flash memory ReRAM memories, magnetoresistive memory (e.g., MRAM), and phase change memory (e.g., PCRAM) can also be used. FIG. 6C shows another example of a non-volatile memory controller, controller 640, with single-port memory 622a and single-port memory 622b coupled to ECC decoder 620. In controller 640, single-port memories 622a-b are arranged as two memory banks that share two ports, Port A and Port B, through a routing circuit 642 that allows either port A or B to access either single-port memory 622a or 622b. Thus, routing circuit 642 has two switching configurations, a first configuration in which Port A is coupled to single-port memory 622a and Port B is coupled to single-port memory 622b and a second configuration in which Port A is coupled to single-port memory 622b and Port B is coupled to single-port memory 622a.) . Smith and Zamir are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Smith and Zamir before him or her to modify the system of Smith to include the multidimensional memory of Zamir, thereafter the system is connected to multidimensional memory. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more flexibility in configuring the memory for access to serve customer and system needs as suggested by Zamir. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Smith with Zamir to obtain the invention as specified in the instant application claims. Referring to claim 21, Smith teaches The system of claim 1 ([see above]) . wherein: the system is implemented as an integrated circuit or an integrated processor, wherein the integrated circuit comprises a second memory separate from the first memory; and the second memory configured to store the first map ([Zamir 0036, 0046] Memory device 100 includes one or more memory die 108. Each memory die 108 includes a three-dimensional memory structure 126 of memory cells (such as, for example, a 3D array of memory cells), control circuitry 110, and read/write circuits 128. In other embodiments, a two-dimensional array of memory cells can be used. Memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in they direction) with each column having multiple memory cells. The vertical columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory cells, with memory cells on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.) . Smith and Zamir are analogous art because they are from the same field of endeavor in storage devices. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Smith and Zamir before him or her to modify the system of Smith to include the multiport/multichannel memory of Zamir, thereafter the system is connected to multiport/multichannel memory. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the system have more flexibility in configuring the memory for access to serve customer and system needs as suggested by Zamir. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Smith with Zamir to obtain the invention as specified in the instant application claims . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Regarding block allocation and reconfiguration . US 20080130717 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132 Application/Control Number: 19/245,824 Page 2 Art Unit: 2132 Application/Control Number: 19/245,824 Page 3 Art Unit: 2132 Application/Control Number: 19/245,824 Page 4 Art Unit: 2132 Application/Control Number: 19/245,824 Page 5 Art Unit: 2132 Application/Control Number: 19/245,824 Page 6 Art Unit: 2132 Application/Control Number: 19/245,824 Page 7 Art Unit: 2132 Application/Control Number: 19/245,824 Page 8 Art Unit: 2132 Application/Control Number: 19/245,824 Page 9 Art Unit: 2132 Application/Control Number: 19/245,824 Page 10 Art Unit: 2132 Application/Control Number: 19/245,824 Page 11 Art Unit: 2132 Application/Control Number: 19/245,824 Page 12 Art Unit: 2132 Application/Control Number: 19/245,824 Page 13 Art Unit: 2132 Application/Control Number: 19/245,824 Page 14 Art Unit: 2132 Application/Control Number: 19/245,824 Page 15 Art Unit: 2132 Application/Control Number: 19/245,824 Page 16 Art Unit: 2132 Application/Control Number: 19/245,824 Page 17 Art Unit: 2132 Application/Control Number: 19/245,824 Page 18 Art Unit: 2132 Application/Control Number: 19/245,824 Page 19 Art Unit: 2132 Application/Control Number: 19/245,824 Page 20 Art Unit: 2132 Application/Control Number: 19/245,824 Page 21 Art Unit: 2132 Application/Control Number: 19/245,824 Page 22 Art Unit: 2132 Application/Control Number: 19/245,824 Page 23 Art Unit: 2132 Application/Control Number: 19/245,824 Page 24 Art Unit: 2132 Application/Control Number: 19/245,824 Page 25 Art Unit: 2132 Application/Control Number: 19/245,824 Page 26 Art Unit: 2132 Application/Control Number: 19/245,824 Page 27 Art Unit: 2132 Application/Control Number: 19/245,824 Page 28 Art Unit: 2132 Application/Control Number: 19/245,824 Page 29 Art Unit: 2132 Application/Control Number: 19/245,824 Page 30 Art Unit: 2132 Application/Control Number: 19/245,824 Page 31 Art Unit: 2132 Application/Control Number: 19/245,824 Page 32 Art Unit: 2132 Application/Control Number: 19/245,824 Page 33 Art Unit: 2132 Application/Control Number: 19/245,824 Page 34 Art Unit: 2132 Application/Control Number: 19/245,824 Page 35 Art Unit: 2132 Application/Control Number: 19/245,824 Page 36 Art Unit: 2132 Application/Control Number: 19/245,824 Page 37 Art Unit: 2132 Application/Control Number: 19/245,824 Page 38 Art Unit: 2132
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