DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: Regarding claim 2, line 6; which recites “…and disposed in the first direction,” should be corrected to “…and disposed in the first direction.”. Appropriate correction is required. (Note: claim should end with a “period”.).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim comparison table
Claims of Application# 19/246026
Claims of U.S. Patent#12,340,760
1. A display device comprising: a display panel including an active area and a non-active area; a subpixel including a plurality of transistors located in the active area of the display panel; a low voltage line configured to supply a low voltage to the display panel; a scan driver configured to output a scan signal of turning on or turning off the plurality of transistors; a timing controller configured to output a data signal for displaying an image on the display panel; and a data driver configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage, the scan driver including a plurality of shift registers located in the non-active area of the display panel; the low voltage line disposed to surround at least three sides of the active area of the display panel.
1. A display device comprising: a display panel including an active area and a non-active area; a low voltage line configured to supply a low voltage to the display panel; a timing controller configured to output a data signal for displaying an image on the display panel; and a data driver configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage, and output the resultant voltage as a compensation data voltage, wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator, wherein the voltage compensator comprises a first switch located between the low voltage line and the compensator to sense the low voltage; and wherein the first switch operates in response to a first switch signal output from the controller.
2. The display device according to claim 1, wherein the low voltage line comprises: a first low voltage line disposed in a first direction on one side of the non-active area; a second low voltage line located at an upper end of the non-active area, connected to the first low voltage line, and disposed in a second direction perpendicular to the first direction; and a plurality of third low voltage lines located in the active area, connected to the second low voltage line, and disposed in the first direction,
7. The display device according to claim 1, wherein the low voltage line comprises: a first low voltage line disposed in a first direction on one side of the non-active area; a second low voltage line located at an upper end of the non-active area, connected to the first low voltage line, and disposed in a second direction perpendicular to the first direction; and a plurality of third low voltage lines located in the active area, connected to the second low voltage line, and disposed in the first direction, wherein the voltage compensator senses the low voltage supplied through each of the plurality of third low voltage lines.
3. The display device according to claim 2, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage and output the resultant voltage as a compensation data voltage.
1. A display device comprising: a display panel including an active area and a non-active area; a low voltage line configured to supply a low voltage to the display panel; a timing controller configured to output a data signal for displaying an image on the display panel; and a data driver configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage, and output the resultant voltage as a compensation data voltage, wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator, wherein the voltage compensator comprises a first switch located between the low voltage line and the compensator to sense the low voltage; and wherein the first switch operates in response to a first switch signal output from the controller.
4. The display device according to claim 3, wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator.
1. A display device comprising: a display panel including an active area and a non-active area; a low voltage line configured to supply a low voltage to the display panel; a timing controller configured to output a data signal for displaying an image on the display panel; and a data driver configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage, and output the resultant voltage as a compensation data voltage, wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator, wherein the voltage compensator comprises a first switch located between the low voltage line and the compensator to sense the low voltage; and wherein the first switch operates in response to a first switch signal output from the controller.
5. The display device according to claim 4, wherein the voltage compensator comprises a first switch located between the low voltage line and the compensator to sense the low voltage; and wherein the first switch operates in response to a first switch signal output from the controller.
1. A display device comprising: a display panel including an active area and a non-active area; a low voltage line configured to supply a low voltage to the display panel; a timing controller configured to output a data signal for displaying an image on the display panel; and a data driver configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage, and output the resultant voltage as a compensation data voltage, wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator, wherein the voltage compensator comprises a first switch located between the low voltage line and the compensator to sense the low voltage; and wherein the first switch operates in response to a first switch signal output from the controller.
6. The display device according to claim 5, wherein the compensator comprises a plurality of capacitors connected in series to store a voltage for compensating for the rise of the low voltage.
2. The display device according to claim 1, wherein the compensator comprises a plurality of capacitors connected in series to store a voltage for compensating for the rise of the low voltage.
7. The display device according to claim 6, wherein the compensator comprises a second switch configured to operate together with the first switch in response to a second switch signal output from the controller, and wherein the first switch and the second switch are simultaneously turned on to sense the low voltage.
3. The display device according to claim 2, wherein the compensator comprises a second switch configured to operate together with the first switch in response to a second switch signal output from the controller, and wherein the first switch and the second switch are simultaneously turned on to sense the low voltage.
8. The display device according to claim 7, wherein the compensator comprises a third switch configured to operate in response to a third switch signal output from the controller, and wherein the third switch is turned on so that a data voltage output from the controller is applied through an input terminal of the compensator.
4. The display device according to claim 3, wherein the compensator comprises a third switch configured to operate in response to a third switch signal output from the controller, and wherein the third switch is turned on so that a data voltage output from the controller is applied through an input terminal of the compensator.
9. The display device according to claim 8, wherein the compensator operates in response to a compensation control signal output from the controller, and comprises a compensation voltage selector configured to select a voltage stored in at least one of the plurality of capacitors to read the selected voltage as a compensation voltage, and to reflect the read compensation voltage in the data voltage.
5. The display device according to claim 4, wherein the compensator operates in response to a compensation control signal output from the controller, and comprises a compensation voltage selector configured to select a voltage stored in at least one of the plurality of capacitors to read the selected voltage as a compensation voltage, and to reflect the read compensation voltage in the data voltage.
10. The display device according to claim 1, wherein the timing controller analyzes the data signal input from outside to calculate an IR rise rate of different portions of the low voltage line corresponding to each pixel connected thereto, and outputs a control signal for controlling the controller based on the IR rise rate.
6. The display device according to claim 1, wherein the timing controller analyzes the data signal input from outside to calculate an IR rise rate of different portions of the low voltage line corresponding to each pixel connected thereto, and outputs a control signal for controlling the controller based on the IR rise rate.
11. The display device according to claim 3, wherein the voltage compensator senses the low voltage supplied through each of the plurality of third low voltage lines.
7. The display device according to claim 1, wherein the low voltage line comprises: a first low voltage line disposed in a first direction on one side of the non-active area; a second low voltage line located at an upper end of the non-active area, connected to the first low voltage line, and disposed in a second direction perpendicular to the first direction; and a plurality of third low voltage lines located in the active area, connected to the second low voltage line, and disposed in the first direction, wherein the voltage compensator senses the low voltage supplied through each of the plurality of third low voltage lines.
Claims 1-11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12,340,760 in view of Park et al. (2011/0084946). Regarding claim 1, which is similar in scope to claim 1 as shown in the claim comparison table above, except for the claim limitations of, a subpixel including a plurality of transistors located in the active area of the display panel; a scan driver configured to output a scan signal of turning on or turning off the plurality of transistors; the scan driver including a plurality of shift registers located in the non-active area of the display panel; the low voltage line disposed to surround at least three sides of the active area of the display panel; as claimed. Park teaches a display device comprising: a subpixel (50; Fig 1; Fig 2) including a plurality of transistors (Fig 2) located in the active area of the display panel (Fig 1: Fig 2; para [0049]); a scan driver (10; Fig 1) configured to output a scan signal of turning on or turning off the plurality of transistors (para [0038] The scan driver 10 generates scan signals to correspond to the driving powers and control signals supplied from the outside (e.g., an external source) and sequentially supplies the generated scan signals to scan lines S1 to Sn. Then, pixels 50 are selected by the scan signals to sequentially receive data signals.); the scan driver including a plurality of shift registers located in the non-active area of the display panel (para [0079] FIG. 4 is a circuit diagram illustrating an example of a shift register which may be included in the scan driver of FIG. 1 in one embodiment of the present invention. FIG. 5 is a circuit diagram illustrating an example of a shift register which may be included in the emission control driver of FIG. 1. In particular, FIGS. 4 and 5 are circuit diagrams illustrating the structure of the ith stage among a plurality of stages included in the shift register of the scan driver and the shift register of the emission control driver, respectively.); the low voltage line (VGLL; Fig 6) disposed to surround at least three sides of the active area of the display panel (Fig 6; para [0098] The low level voltages of the scan signal and the emission control signal are generated to have the same level due to the same gate low level voltage VGL supplied from the second power source supply line VGLL.). It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device of U.S. Patent # 12,340,760 with the teachings of Park, because the scan driver comprising shit register are well known circuit elements of display device which are used for driving the display device and providing power lines in the manner will yield predictable results for power to different elements of the display for providing desirable output. Regarding claim 2 of instant application is further anticipated by claim 7 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 3 of instant application is further anticipated by claim 1 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 4 of instant application is further anticipated by claim 1 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 5 of instant application is further anticipated by claim 1 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 6 which is similar in scope claim 2 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 7 which is similar in scope claim 3 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 8 which is similar in scope claim 4 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 9 which is similar in scope claim 5 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 10 which is similar in scope claim 6 of U.S. Patent # 12,340,760 as shown in the claim comparison table above. Regarding claim 11 of instant application is further anticipated by claim 7 of U.S. Patent # 12,340,760 as shown in the claim comparison table above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (2016/0005359) in view of Park et al. (2011/0084946).
Regarding claim 1, Kwon teaches a display device comprising: a display panel (150; Fig 1) including an active area (AA; Fig 3; para [0041] As shown in FIG. 3, an active area AA,) and a non-active area (Fig 3; para [0042] A bezel area corresponding to non-active areas NAx, NAy1, and NAy2 are defined outside the active area AA.); a subpixel (SP; Fig 3) including a plurality of transistors located in the active area of the display panel (Fig 3; Fig 4; para [0042] An active area AA comprises subpixels SP.); a low voltage line (ELVSS; Fig 4; VGL; Fig 5) configured to supply a low voltage to the display panel (para [0045] Typically, the timing controller 120, a power supply part, etc. are mounted in the form of an integrated circuit on an external substrate (e.g., printed circuit board). Para [0055]; para [0072]); a scan driver (130; Fig 1) configured to output a scan signal of turning on or turning off the plurality of transistors (para [0037] The scan driver 130 outputs a scan signal while shifting the level of a gate voltage, in response to the gate timing control signal GDC supplied from the timing controller 120. Para [0039] The display panel 150 displays an image in response to a scan signal supplied from the scan driver 130 and a data signal DATA supplied form the data driver 140.); a timing controller (120; Fig 1) configured to output a data signal for displaying an image on the display panel (para [0036] The timing controller 120 receives a data signal, etc from the image processor 110, and outputs a gate timing control signal GDC for controlling the operation timing of the scan driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140. The timing controller 120 supplies the data signal DATA, together with the data timing control signal DDC, to the data driver 140.); and a data driver (140; Fig 1) configured to convert the data signal into a data voltage to be supplied to the display panel and output the converted data voltage (para [0038] The data driver 140 samples and latches a data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, and converts an analog signal into a digital signal and outputs it in response to a gamma reference voltage. The data driver 140 supplies the data signal DATA to the subpixels SP included in the display panel 150 through data lines DL1 to DLn.), the scan driver including a plurality of shift registers located in the non-active area of the display panel (Fig 3; para [0037] The portion formed in the scan driver 130 using the Gate-In-Panel technology is a shift register. Fig 5; para [0054]).
Kwon fails to teach, the low voltage line disposed to surround at least three sides of the active area of the display panel; as claimed.
Park teaches a display device comprising: a display panel (40; Fig 1; Fig 6); a low voltage line configured to supply a low voltage to the display panel (VGLL; Fig 6); a scan driver (10; Fig 6); a data driver (30; Fig 6); the low voltage line disposed to surround at least three sides of the active area of the display panel (Fig 6; para [0012] a second power source supply line surrounding the display unit and coupling the third pad to the fourth pad via the scan driver. para [0098] The low level voltages of the scan signal and the emission control signal are generated to have the same level due to the same gate low level voltage VGL supplied from the second power source supply line VGLL.).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device Kwon with the teachings of Park, because these are well known circuit elements of display device which are used for driving the display device and providing power lines in the manner will yield predictable results for power to different elements of the display for providing desirable output.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (2016/0005359) in view of Park et al. (2011/0084946) as applied to claim 1 above, and further in view of Yang et al. (2021/0391403).
Regarding claim 2, Kwon teaches the display device as explained for claim 1 above.
Kwon fails to teach, wherein the low voltage line comprises: a first low voltage line disposed in a first direction on one side of the non-active area; a second low voltage line located at an upper end of the non-active area, connected to the first low voltage line, and disposed in a second direction perpendicular to the first direction; and a plurality of third low voltage lines located in the active area, connected to the second low voltage line, and disposed in the first direction; ; as claimed.
Park teaches the display device, wherein the low voltage line comprises: a first low voltage line disposed in a first direction on one side of the non-active area (VGLL; Fig 6 which is disposed on the left side of the display panel 40); a second low voltage line located at an upper end of the non-active area (VGLL; Fig 6 which is disposed on the upper side of the display panel 40), connected to the first low voltage line (Fig 6), and disposed in a second direction perpendicular to the first direction (Fig 6).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device Kwon with the teachings of Park, because these are well known circuit elements of display device which are used for driving the display device and providing power lines in the manner will yield predictable results for power to different elements of the display for providing desirable output.
Kwon and Park fails to teach; and a plurality of third low voltage lines located in the active area, connected to the second low voltage line, and disposed in the first direction; as claimed.
Yang teaches a display device comprising: a voltage line (PL; Fig 2) ; wherein the voltage line comprises a second voltage line (Fig 2 which shows PL disposed in horizontal direction connected to ELVDD) and a plurality of third voltage lines located in the active area (Fig 2 which shows plurality of power lines PL disposed in vertical direction connected to ELVDD), connected to the second voltage line (Fig 2), and disposed in a first direction (vertical direction; Fig 2).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the low voltage lines of display device Kwon and Park with the teachings of Yang, because these are well known circuit elements of display device which are used for driving the display device and providing power lines in the manner will yield predictable results for power to different elements of the display for providing desirable output.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (2016/0005359) in view of Park et al. (2011/0084946) as applied to claim 1 above, and further in view of Yang et al. (2021/0391403) as applied to claim 2 above, and further in view of Kim (2020/0082761).
Regarding claim 3, Kwon, Park and Yang teaches the display device as explained for claim 2 above.
Kwon, Park and Yang fails to teach, wherein the data driver comprises a voltage compensator configured to prepare a compensation voltage for compensating for a rise of the low voltage, reflect the compensation voltage in the data voltage and output the resultant voltage as a compensation data voltage; as claimed.
Kim teaches a display device comprising: a data driver (120+200+140; Fig 1); wherein the data driver comprises a voltage compensator (200; Fig 1; para [0066] For example, at least portion of the components in the peak luminance control portion 200 may be located in the timing control circuit 110 or the data driving circuit 120) configured to prepare a compensation voltage for compensating for a rise of the low voltage (para [0070] The compensation value calculation portion 220 may include an IR variation amount derivation portion 221 and a compensation value derivation portion 225. para [0071] The IR variation amount derivation portion 221 may derive an IR variation amount (e.g., an IR drop amount and an IR rise amount) in a column direction, which is an extension direction of the first power line PWL to transfer the first power voltage VDD, as a direction along which the IR variation amount is produced in displaying a picture.), reflect the compensation voltage in the data voltage and output the resultant voltage as a compensation data voltage (para [0079] Thus, in this embodiment, an IR variation amount in a column line direction, along which a driving voltage Id is transferred, may be derived for a picture to be displayed, and based on this, an APL may be compensated and a peak luminance PL may be adjusted. para [0117] The gamma source voltage generation portion 250 may receive a peak luminance PL output from the peak luminance calculation portion 240, and may generate and output a high-potential gamma source voltage VREG corresponding to the peak luminance PL using the peak luminance PL.).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device Kwon, Park and Yang with the teachings of Kim, because this will provide display device which can reduce a power consumption and achieve an effective PLC driving.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (2016/0005359) in view of Park et al. (2011/0084946) as applied to claim 1 above, and further in view of Yang et al. (2021/0391403) as applied to claim 2 above, and further in view of Kim (2020/0082761) as applied to claim 3 above, and further in view of Lim et al. (2024/0096279).
Regarding claim 4, Kwon, Park, Yang and Kim teaches the display device as explained for claim 3 above.
Kwon, Park, Yang and Kim fails to teach wherein the voltage compensator comprises: a compensator configured to store a voltage for compensating for the rise of the low voltage; and a controller configured to control the compensator; as claimed.
Lim teaches a display device comprising: a voltage compensator (320; Fig 3);
wherein the voltage compensator comprises: a compensator (322; Fig 4) configured to store a voltage for compensating for the rise of the low voltage (LUT; Fig 4; para [0068] Referring to FIG. 4, the voltage compensator 322 may include a lookup table LUT for storing the voltage increase amount ?V.sub.EL of the light emitting diode EL and the drain-source voltage increase amount ?V.sub.DS of the first transistor T1 corresponding to each grayscale value GV and each degradation amount DA); and a controller configured to control the compensator (321; Fig 3; para [0066] The voltage compensator 322 may calculate the driving voltage increase amount ?ELVDD based on the degradation amount DA of the maximum degradation pixel and the grayscale value GV applied to the maximum degradation pixel).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device of Kwon, Park, Yang and Kim with the teachings of Lim, because this will result in reduced power consumption of the display device.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (2016/0005359) in view of Park et al. (2011/0084946) as applied to claim 1 above, and further in view of Yang et al. (2021/0391403) as applied to claim 2 above, and further in view of Kim (2020/0082761) (here after referred to as Kim’761) as applied to claim 3 above, and further in view of Kim et al. (2024/0144856) (here after referred to as Kim’856).
Regarding claim 11, Kwon, Park, Yang and Kim’761 teaches the display device as explained for claim 3 above.
Kwon, Park, Yang and Kim’761 fails to teach, wherein the voltage compensator senses the low voltage supplied through each of the plurality of third low voltage lines; as claimed.
Kim’856 teaches a display device comprising: a voltage compensator (DDV; Fig 2); wherein the voltage compensator senses the low voltage supplied through each of the plurality of third low voltage lines (para [0071] The data driver DDV may sense a sensing voltage VSS in the plurality of pixels PX. The sensing voltage VSS may be provided to the timing controller T-CON. The timing controller T-CON may compensate for the pieces of image data DATA applied to the plurality of pixels PX based on the sensing voltage VSS.).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display device of Kwon, Park, Yang and Kim’761 with the teachings of Kim’856, because this will provide display thereby improving the luminance uniformity of a display panel (Kim’856: para [0257]).
Conclusion
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/PREMAL R PATEL/Primary Examiner, Art Unit 2624