DETAILED ACTION
This action responds to Application No. 19/246124, filed 06/23/2025.
Claims 1-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/02/2026 and 06/23/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13, 15, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 13, 15, an 18 recite the limitation “the number of available credits” (e.g. claim 13, line 5). There is insufficient antecedent basis for this limitation in the claim.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3, 4-12, 13-18, 19, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-13, 15-20, 5-6, and 9, of U.S. Patent No. 12360844. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims merely represent a broadened version of the claims of Patent No. 12360844, as follows:
Claim
Instant Application
Patent No. 12360844
1.
A system comprising: a resource associated with a number of available credits; a data path coupled to the resource; a cache configuration register configured to store a setting; and an arbiter circuit configurable to: determine whether 1) the setting stored in the cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determine a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; after receiving the first and second memory access requests, receive a subsequent memory access request to the resource; compare the first priority with a second priority of the subsequent memory access request to determine a third result; determine a final arbitration winner based on the third result; and drive the final arbitration winner to the data path.
A device comprising: a resource associated with a number of available credits; a data path coupled to the resource; a cache configuration register configured to store a setting; and an arbiter circuit, wherein the arbiter circuit is configured to: […] determine whether 1) the setting stored in the cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determine a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; after receiving the first and second memory access requests, receive a subsequent memory access request to the resource; compare the first priority with a second priority of the subsequent memory access request to determine a third result; determine a final arbitration winner based on the third result; and drive the final arbitration winner to the data path. (claim 1)
2.
The system of claim 1, wherein: the cache configuration register is configurable to store the setting as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and wherein the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register.
The device of claim 1, wherein: the cache configuration register is configured to store the setting as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register. (claim 2)
3.
The system of claim 1, wherein: the first priority is based on an indicator in the pre-arbitration winner.
The device of claim 1, wherein: the first priority is based on a first indicator in the first memory access request or a second indicator in the second memory access request. (claim 3)
4.
The system of claim 1, wherein: the arbiter circuit is configurable to: drive the pre-arbitration winner to the data path before to driving the subsequent memory access request to the data path; and in response to a first credit cost associated with the pre-arbitration winner being less than or equal to the number of available credits, decrement the number of available credits by the first credit cost to produce a reduced number of available credits.
The device of claim 1, wherein: the arbiter circuit is configured to:based on the first and second results, drive the first memory access request to the data path prior to driving the second memory access request to the data path; andin response to the first credit cost being less than or equal to the number of available credits, decrement the number of available credits by the first credit cost to produce a reduced number of available credits. (claim 5)
5.
The system of claim 5, wherein: the arbiter circuit is configurable to: drive the subsequent memory access request to the data path after driving the pre-arbitration winner to the data path and before receiving an acknowledgement that the pre-arbitration winner has been processed by the resource; decrement the reduced number of available credits by a second credit cost associated with the subsequent memory access request in response to the second credit cost being less than or equal to the reduced number of available credits.
The device of claim 5, wherein: the arbiter circuit is configured to:drive the second memory access request to the data path subsequent to driving the first memory access request to the data path and prior to receiving an acknowledgement that the first memory access request has been processed by the resource; andin response to the second credit cost being less than or equal to the reduced number of available credits, decrement the reduced number of available credits by the second credit cost. (claim 6)
6.
The system of claim 1, wherein: the arbiter circuit is configurable to increase the number of available credits to the resource by a first amount equal to a first credit cost associated with the pre-arbitration winner in response to receiving an acknowledgement that the pre-arbitration winner has been processed by the resource; and increase the number of available credits to the resource by a second amount equal to a second credit cost associated with the subsequent memory access request in response to receiving an acknowledgement that the subsequent memory access request has been processed by the resource.
The device of claim 1, wherein: the arbiter circuit is configured to increase the number of available credits to the resource by a first amount equal to the first credit cost in response to receiving an acknowledgement that the first memory access request has been processed by the resource; and the arbiter circuit is configured to increase the number of available credits to the resource by a second amount equal to the second credit cost in response to receiving an acknowledgement that the second memory access request has been processed by the resource. (claim 7)
7.
The system of claim 1, wherein: the pre-arbitration winner is associated with a first priority group; the subsequent memory access request is associated with a second priority group; and the first priority group is associated with a higher priority than the second priority group.
The device of claim 1, wherein: the first memory access request is associated with a first priority group; the second memory access request is associated with a second priority group; and the first priority group is associated with a higher priority than the second priority group. (Claim 8)
8.
The system of claim 7, further comprising a starvation register, wherein the arbiter circuit is configurable to promote the subsequent memory access request to the first priority group in response to the subsequent memory access request losing arbitration to the first priority group for a number of clock cycles set in the starvation register.
The device of claim 8, wherein: the arbiter circuit is configured to promote the second memory access request to the first priority group in response to the second memory access request losing arbitration to the first priority group for a number of clock cycles set in a starvation register. (claim 9)
9.
The system of claim 1, wherein: the number of available credits corresponds to available space in one or more queues of the resource.
The device of claim 1, wherein: the number of available credits corresponds to available space in one or more queues of the resource.
(claim 10)
10.
A method comprising: determining whether 1) a setting stored in a cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determining, by the arbiter circuit, a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; receiving a subsequent memory access request to a resource; comparing the first priority with a second priority of the subsequent memory access request to determine a third result; determining a final arbitration winner based on the third result; and driving the final arbitration winner to a data path.
A method comprising: […] determining whether 1) a setting stored in a cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determining, by the arbiter circuit, a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; after receiving the first and second memory access requests, receiving, by the arbiter circuit, a subsequent memory access request to the resource; comparing, by the arbiter circuit, the first priority with a second priority of the subsequent memory access request to determine a third result; determining, by the arbiter circuit, a final arbitration winner based on the third result; and driving, by the arbiter circuit, the final arbitration winner to the data path based. (Claim 11)
11.
The method of claim 10, wherein: the setting is stored in the cache configuration register as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and wherein the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register.
The method of claim 11, wherein: the setting is stored in the cache configuration register as a bit mask indicating that the pre-arbitration winner is the real-time request or the non-real-time request; and the first priority is based on a source of the pre-arbitration winner and the bit mask stored in the cache configuration register. (claim 12)
12.
The method of claim 11, wherein: the first priority is based on an indicator in the pre-arbitration winner.
The method of claim 11, wherein: the first priority is based on a first indicator in the first memory access request or a second indicator in the second memory access request. (claim 13)
13.
The method of claim 10, further comprising: driving the pre-arbitration winner to the data path before driving the subsequent memory access request to the data path; and in response to a first credit cost associated with the pre-arbitration winner being less than or equal to the number of available credits, decrementing the number of available credits by the first credit cost to produce a reduced number of available credits.
The method of claim 11, further comprising: based on the first and second results, driving, by the arbiter circuit, the first memory access request to the data path prior to driving the second memory access request to the data path; and in response to the first credit cost being less than or equal to the number of available credits, decrementing, by the arbiter circuit, the number of available credits by the first credit cost to produce a reduced number of available credits. (claim 15)
14.
The method of claim 13, further comprising: driving the subsequent memory access request to the data path after driving the pre-arbitration winner to the data path and before receiving an acknowledgement that the pre-arbitration winner has been processed by the resource; and decrementing the reduced number of available credits by the second credit cost associated with the subsequent memory access request in response to the second credit cost being less than or equal to the reduced number of available credits.
The method of claim 15, further comprising: driving, by the arbiter circuit, the second memory access request to the data path subsequent to driving the first memory access request to the data path and prior to receiving an acknowledgement that the first memory access request has been processed by the resource; and in response to the second credit cost being less than or equal to the reduced number of available credits, decrementing, by the arbiter circuit, the reduced number of available credits by the second credit cost. (claim 16)
15.
The method of claim 10, further comprising: increasing the number of available credits to the resource by a first amount equal to a first credit cost in response to receiving an acknowledgement that the pre-arbitration winner has been processed by the resource; and increasing the number of available credits to the resource by a second amount equal to a second credit cost associated with the subsequent memory access request in response to receiving an acknowledgement that the subsequent memory access request has been processed by the resource.
The method of claim 11, further comprising: increasing, by the arbiter circuit, the number of available credits to the resource by a first amount equal to the first credit cost in response to receiving an acknowledgement that the first memory access request has been processed by the resource; and increasing, by the arbiter circuit, the number of available credits to the resource by a second amount equal to the second credit cost in response to receiving an acknowledgement that the second memory access request has been processed by the resource. (claim 17)
16.
The method of claim 10, wherein: the pre-arbitration winner is associated with a first priority group; the subsequent memory access request is associated with a second priority group; and the first priority group is associated with a higher priority than the second priority group.
The method of claim 11, wherein: the first memory access request is associated with a first priority group; the second memory access request is associated with a second priority group; and the first priority group is associated with a higher priority than the second priority group. (claim 18)
17.
The method of claim 16, further comprising promoting the subsequent memory access request to the first priority group in response to the subsequent memory access request losing arbitration to the first priority group for a number of clock cycles set in a starvation register.
The method of claim 18, further comprising: promoting, by the arbiter circuit, the second memory access request to the first priority group in response to the second memory access request losing arbitration to the first priority group for a number of clock cycles set in a starvation register. (claim 19)
18
The method of claim 10, wherein: the number of available credits corresponds to available space in one or more queues of the resource.
The method of claim 18, wherein: the number of available credits corresponds to available space in one or more queues of the resource. (claim 20)
19
A system comprising: a resource associated with a number of available credits; a data path coupled to the resource; a cache configuration register configured to store a setting; and an arbiter circuit configurable to: determine whether 1) the setting stored in the cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determine a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; after receiving the first and second memory access requests, receive a subsequent memory access request to the resource; compare the first priority with a second priority of the subsequent memory access request to determine a third result; determine a final arbitration winner based on the third result; and drive the final arbitration winner to the data path.
A device comprising: a resource associated with a number of available credits; a data path coupled to the resource; a cache configuration register configured to store a setting; and an arbiter circuit, wherein the arbiter circuit is configured to: […] determine whether 1) the setting stored in the cache configuration register has a first value indicative that the pre-arbitration winner is a real-time request or 2) the setting stored in the cache configuration register has a second value indicative that the pre-arbitration winner is a non-real-time request; determine a first priority of the pre-arbitration winner based on the determination that the setting stored in the cache configuration register has the first value or the second value and a number of real-time requests that have previously been selected; after receiving the first and second memory access requests, receive a subsequent memory access request to the resource; compare the first priority with a second priority of the subsequent memory access request to determine a third result; determine a final arbitration winner based on the third result; and drive the final arbitration winner to the data path. (claim 1)
decrement the number of available credits by a credit cost associated with the final arbitration winner to produce a reduced number of available credits in response to the credit cost being less than or equal to the number of available credits; and
in response to the first credit cost being less than or equal to the number of available credits, decrement the number of available credits by the first credit cost to produce a reduced number of available credits. (claim 5)
increase the reduced number of available credits to the resource by the credit cost in response to receiving an acknowledgement that the final arbitration winner has been processed by the resource.
The arbiter is configured to increase the reduced number of available credits to the resource by a first amount equal to the first credit cost in response to receiving an acknowledgement that the first memory access has been processed by the resource (claim 7)
20
The system of claim 19, further comprising a starvation register,
The device of claim 8, wherein: […] in a starvation register. (claim 9)
the pre-arbitration winner is associated with a first priority group; the subsequent memory access request is associated with a second priority group; and wherein the first priority group is associated with a higher priority than the second priority group,
the first memory access request is associated with a first priority group; the second memory access request is associated with a second priority group; and the first priority group is associated with a higher priority than the second priority group. (Claim 8)
wherein the arbiter circuit is configurable to promote the subsequent memory access request to the first priority group in response to the subsequent memory access request losing arbitration to the first priority group for a number of clock cycles set in the starvation register.
wherein the arbiter circuit is configurable to promote the subsequent memory access request to the first priority group in response to the subsequent memory access request losing arbitration to the first priority group for a number of clock cycles set in a starvation register (claim 9)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Benisty (US 20180217951 A1). Discloses a credit-aware multi-level arbitration scheme (Figs. 8E-6; ¶ 13 and 124-125);
Takefman (US 20140237205 A1). Discloses a specific timing diagram for DMA arbitration requests (Fig. 27; ¶ 206-208);
Howe (US 5596376 A). Discloses bit masks which indicate whether requests are real-time or not (col. 10, lines 5-29);
Neuman (US 2003/0167294 A1). Discloses a block-out counter for preventing one source from monopolizing real-time resources (Abstract).
It is noted that Examiner attempted to contact Applicant’s attorney of record, Carl Peterson (72674) to resolve the outstanding issues above, but was unsuccessful. Applicant is encouraged to contact Examiner with any questions regarding these outstanding issues.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/
Primary Examiner, Art Unit 2132
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