DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Pub. 2024/0013707 A1 to Wang et al (“Wang”).
As to claim 12, Wang discloses a method of driving a display device, the method comprising:
an initialization operation of initializing a gate node of a driving transistor based on a first initialization voltage (See Fig. 8, Scan(n-1); ¶ 0051);
a sensing and data write operation of initializing an anode of a light-emitting diode based on a second initialization voltage, sampling a threshold voltage of the driving transistor, and storing a data voltage applied through a first data line in a capacitor (See Fig. 8, ScanN; ¶ 0052); and
an emission operation of controlling the light-emitting diode to emit light based on a driving current generated from the driving transistor and blocking a leakage path between the gate node and a drain node of the driving transistor (See Fig. 8, EM(N), VB; ¶ 0053-0055),
wherein the emission operation comprises applying a high-level voltage to a connection point between a first A switching transistor and a first B switching transistor connected between the gate node and the drain node of the driving transistor to block the leakage path (See Fig. 6; VI2 is driven by T81 to node D between T31 and T32; ¶ 0055, “The first anti-leakage transistor T81 and/or the second anti-leakage transistor T82 can be turned on, then the electrical potentials of the gate electrode of the driving transistor T1 and the another one of the source electrode and the drain electrode of the first transistor T31 is close to or equal to each other. At this time, the gate electrode of the driving transistor T1 hardly leaks current”).
As to claim 13, Wang discloses wherein the applying the high- level voltage comprises turning on a compensation transistor (See Fig. 6, T81) having a first electrode connected to a high-level voltage line (VI2) and a second electrode connected to the connection point between the first A switching transistor and the first B switching transistor (T81 is connected between T31 and T32 at node D) and operating in response to an nth control signal applied through an Nth control line (VB).
As to claim 14, Wang discloses wherein the compensation transistor is turned on during an emission period in which the light-emitting diode emits light (See Fig. 6 and 8; EM(N) and VB are low and transistors T81 and T5/T6 are turned on.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Pub. 2024/0013707 A1 to Wang et al (“Wang”) in view of US Patent Pub. 2021/0066429 A1 to Kim et al (“Kim”).
As to claim 1, Wang discloses a display device (See abstract) comprising:
a display panel including a subpixel (100) configured to display an image, wherein the subpixel (See Fig. 6) comprises:
a light-emitting diode (LED1) configured to emit light;
a driving transistor (T1) configured to generate a driving current to be supplied to the light-emitting diode;
a first switching transistor (T31, T32) connected between a gate node and a drain node of the driving transistor, and including a first A switching transistor (T31) and a first B switching transistor (T32) configured to operate in response to an Nth scan signal (Scan (N)) applied through an Nth scan line, where N is a real number (See Fig. 6; T31/T32 are connected to the gate node Q and the drain of driving transistor T1.);
a second switching transistor (T41, T42) connected between the gate node of the driving transistor (Q) and a first initialization voltage line (VI), and configured to operate in response to an (N-1)th scan signal applied through an (N-1)th scan line (Scan (N-1)); and
a compensation transistor (T81) having a first electrode connected to a high-level voltage line (VI2) and a second electrode connected to a connection point between the first A switching transistor and the first B switching transistor (See Fig. 6; T81 connected to D), and operating in response to an Nth control signal applied through an Nth control line (VB).
Wang fails to disclose a display panel including a plurality of subpixels; and a driver configured to drive the display panel.
Kim discloses a display panel (See Fig. 2, 10) including a plurality of subpixels (PX); and
a driver (Fig. 3, 22, 41, 42) configured to drive the display panel.
Before the effective filing date, it would have been obvious to one of ordinary skill in the art to have modified Wang with the teachings of Kim of a display panel including a plurality of subpixels; and a driver configured to drive the display panel, as suggested by Kim thereby similarly using known configurations of display panels and elements required for operation of display devices.
As to claim 2, Wang discloses wherein the compensation transistor is turned on during an emission period in which the light-emitting diode emits light (See Fig. 6 and 8; EM(N) and VB are low and transistors T81 and T5/T6 are turned on.).
As to claim 3, Wang discloses wherein the compensation transistor is turned on during an emission period in which the light-emitting diode emits light so that a high-level voltage is applied to the connection point between the first A switching transistor and the first B switching transistor (See Fig. 6 and 8; EM(N) and VB are low and transistors T81 and T5/T6 are turned on. VI2 is driven to node D between transistors T31 and T32 (¶ 0040).).
As to claim 4, Wang discloses wherein each of the plurality of subpixels comprises:
a first control transistor positioned between a source node of the driving transistor and the high-level voltage line (See Fig. 6, T5 connected between VDD and source of T1); and
a second control transistor positioned between the drain node of the driving transistor and an anode of the light-emitting diode (See Fig. 6, T6 connected to T1 and the anode of LED1).
As to claim 5, Wang discloses wherein the compensation transistor, the first control transistor, and the second control transistor are turned on simultaneously (See Fig. 6 and 8; EM(N) and VB are low and transistors T81 and T5/T6 are turned on.).
As to claim 7, Wang discloses wherein the first A switching transistor (See Fig. 6, T31) has a gate electrode connected to the Nth scan line (T31 connected to ScanN), a first electrode connected to the gate node of the driving transistor (T31 is connected to Q), and a second electrode connected to a first electrode of the first B switching transistor (T31 is connected to D), and wherein the first B switching transistor (T32) has a gate electrode connected to the Nth scan line (T32 connected to ScanN), a first electrode connected to the second electrode of the first A switching transistor (T32 connected to D), and a second electrode connected to the drain node of the driving transistor (T32 connected to drain of T1).
As to claim 8, Wang discloses wherein each of the plurality of subpixels (See Fig. 6) comprises:
a capacitor (Cst) having a first electrode connected to the high-level voltage line (VDD) and a second electrode connected to the gate node of the driving transistor (Q);
a second switching transistor (T41, T42) having a gate electrode connected to the (N-1)th scan line (The gate of T41 and T42 connected to Scan(n-1)), a first electrode connected to the first initialization voltage line (VI), and a second electrode connected to the gate node of the driving transistor and the first electrode of the first A switching transistor (T41/T42 is connected to Q);
a third switching transistor (T5) having a gate electrode connected to the Nth control line (EM(N)), a first electrode connected to the high-level voltage line (VDD), and a second electrode connected to a source node of the driving transistor (T5 connected to T1);
a fourth switching transistor (T6) having a gate electrode connected to the Nth control line (EM(N)), a first electrode connected to the drain node of the driving transistor (T6 connected to T1), and a second electrode connected to an anode of the light-emitting diode (T6 connected to LED1);
a fifth switching transistor (T2) having a gate electrode connected to the Nth scan line (ScanN), a first electrode connected to a first data line (DATA), and a second electrode connected to the second electrode of the third switching transistor and the source node of the driving transistor (T2 connected at node between T5 and T1); and
a sixth switching transistor (T7) having a gate electrode connected to the Nth scan line (ScanN), a first electrode connected to a second initialization voltage line (VI), and a second electrode connected to the second electrode of the fourth switching transistor and the anode of the light-emitting diode (T7 connected to LED1).
As to claim 9, Zhang discloses wherein the driving transistor (See Fig. 6, T1) includes a gate electrode connected to the second electrode of the capacitor (T1 connected to Cst), a first electrode connected to the second electrode of the fifth switching transistor and the second electrode of the third switching transistor (T1 connected to node connecting T5 and T2), and a second electrode connected to a second electrode of the first B switching transistor and the first electrode of the fourth switching transistor (T1 connected node connecting T32 and T6),
wherein the compensation transistor (T81) includes a gate electrode connected to the Nth control line (VB), a first electrode connected to the high-level voltage line (VI2), and a second electrode connected to the connection point between the second electrode of the first A switching transistor and the first electrode of the first B switching transistor (T81 connected between T31 and T32 at node D), and wherein the light-emitting diode includes the anode connected to the second electrode of the fourth switching transistor and the second electrode of the sixth switching transistor, and a cathode connected to a low-level voltage line (The anode of LED1 is connected to T6 and T7 and the cathode is connected to VSS).
As to claim 10, the same rejection or discussion is used as in the rejection of claim 1.
As to claim 11, the same rejection or discussion is used as in the rejection of claim 2.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Pub. 2024/0013707 A1 to Wang et al (“Wang”) in view of US Patent Pub. 2021/0066429 A1 to Kim et al (“Kim”), and further in view of US Patent No. 12,027,080 B1 to Jeon et al (“Jeon”)
As to claim 6, Wang in view of Kim discloses wherein the transistors included in each of the plurality of subpixels are p-type transistors (Wang, ¶ 0048, “p-channel type polysilicon thin film transistor”), but fails to disclose p-type low-temperature polycrystalline silicon (LTPS) transistors.
Jeon discloses p-type low-temperature polycrystalline silicon (LTPS) transistors (col. 13, lines 18-20).
Before the effective filing date, it would have been obvious to one of ordinary skill in the art to have modified Wang in view of Kim with the teachings of Jeon of p-type low-temperature polycrystalline silicon (LTPS) transistors, as suggested by Jeon thereby similarly using known configurations for p-type transistors in the display device of Wang modified.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J LEE whose telephone number is (571)270-7354. The examiner can normally be reached Mon-Fri 10-6PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS J LEE/Primary Examiner, Art Unit 2624