DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang et al (CN 115988905 A (See US 2024/0324295 A1 for official translation and rejection citations)).
Claim 1, Jiang (Fig. 1-9) discloses a pixel structure (Fig. 1; Paragraph [0033]; wherein discloses a pixel structure), comprising:
a drive substrate (10 and 20; Fig. 5; Paragraph [0042]; wherein discloses a base substrate (10); Paragraph [0043]; wherein discloses a driver layer (20));
a first pixel definition layer (71; Fig. 5; Paragraph [0049]; wherein discloses a pixel definition layer), a pixel anode (30; Fig. 5; Paragraph [0045]; wherein discloses an anode layer (30)) and a second pixel definition layer (61; Fig. 5; Paragraph [0052]; wherein discloses an isolation column made of the same material as the pixel definition layer) that are sequentially distributed (Fig. 5; wherein elements 71, 30, and 61 are sequentially distributed along C-C’ line in figure 4) on the drive substrate (10 and 20; Fig. 5; Paragraph [0042]; wherein discloses a base substrate (10); Paragraph [0043]; wherein discloses a driver layer (20)), wherein the first pixel definition layer (71; Fig. 5; Paragraph [0049]; wherein discloses a pixel definition layer) is not in contact with (Fig. 5; wherein figure shows horizontal slice similar to Applicant’s figure 1 in which the two pixel definition layers are separated by a pixel region) the second pixel definition layer (61; Fig. 5; Paragraph [0052]; wherein discloses an isolation column made of the same material as the pixel definition layer), wherein the pixel anode (30; Fig. 5) extends to a corresponding position below (Paragraph [0048]; wherein discloses “The isolation column 61 is located above the anode unit corresponding to the sub-pixel”) the second metal structure (62; Fig. 5) in the second pixel definition layer (61; Fig. 5);
a first metal structure (72; Fig. 4 and 5; Paragraph [0049]; wherein discloses a boundary conducting layer (72)) disposed on the first pixel definition layer (71; Fig. 5) and a second metal structure (62; Fig. 4 and 5; Paragraph [0049]; wherein discloses a conduction unit (62)) disposed on the second pixel definition layer (61; Fig. 5);
a first insulation structure (73; Fig. 5; Paragraph [0073]; wherein discloses a roof structure) disposed on the first metal structure (72; Fig. 5) and a second insulation structure (63; Fig. 5; Paragraph [0050]; wherein discloses a roof structure) disposed on the second metal structure (62; Fig. 5), wherein the first metal structure (72; Fig. 5) with the first insulation structure (73; Fig. 5) and the second metal structure (62; Fig. 5) with the second insulation structure (63; Fig. 5) respectively form an overhang structure (Fig. 5; wherein figure shows similar overhang structure as Applicant’s figure 1);
an electroluminescent layer (40; Fig. 2 and 5; Paragraph [0035]; wherein discloses a luminescent layer), covering a portion of the first pixel definition layer (71; Fig. 2 and 5), a portion of the pixel anode (30; Fig. 2 and 5) and a portion of the second pixel definition layer (61; Fig. 5; Paragraph [0048]), wherein the electroluminescent layer (40; Fig. 2 and 5) is located between the first metal structure (72; Fig. 2 and 5) and the second metal structure (62; Fig. 5); and
a pixel cathode (50; Fig. 2 and 5; Paragraph [0035]; wherein discloses a cathode layer), covering the electroluminescent layer (40; Fig. 2 and 5), wherein two ends of the pixel cathode (50; Fig. 5) are respectively connected to the first metal structure (72; Fig. 2 and 5; Paragraph [0035]) and the second metal structure (62; Fig. 5; Paragraph [0048]).
Claim 2, Jiang (Fig. 1-9) discloses wherein a thickness of the first pixel definition layer (71; Fig. 2 and 5; wherein figures show pixel definition layer having a thickness) and a thickness of the second pixel definition layer (61; Fig. 5; wherein figure shows isolation column having a thickness) are both greater than a thickness of the pixel anode (30; Fig. 2 and 5; wherein figure shows both elements 71 and 61 having greater thickness then element 30);
a thickness of the first metal structure (72; Fig. 2 and 5) or a thickness of the second metal structure (62; Fig. 5) is greater than (Fig. 2 and 5; wherein figures shows elements 72 and 62 having a greater thickness then element 73) a thickness of the first insulation structure (73; Fig. 2 and 5);
the thickness of the first metal structure (72; Fig. 2 and 5) or the thickness of the second metal structure (62; Fig. 5) is greater than a thickness (Fig. 2 and 5; wherein figures shows elements 72 and 62 having a greater thickness then element 63) of the second insulation structure (63; Fig. 5); and
the thickness of the pixel anode (30; Fig. 2) is greater (Fig. 2; wherein figure shows element 30 having a greater thickness then element 50) than a thickness of the pixel cathode (50; Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (CN 115988905 A (See US 2024/0324295 A1 for official translation and rejection citations)) in view of Omoto (US 2012/0175645 A1).
Claim 3, Jiang discloses the pixel structure according to claim 1.
Jiang does not expressly disclose wherein a first patch capacitor is formed by the pixel anode and the pixel cathode, and a second patch capacitor is formed by the pixel anode.
Omoto (Fig. 10 and 11) discloses wherein a first patch capacitor (Coled; Fig. 11A; Paragraph [0135]) is formed by the pixel anode (211; Fig. 10) and the pixel cathode (313; Fig. 4), and a second patch capacitor (Csub; Fig. 10) is formed by the pixel anode (211A; Fig. 10) and the second metal structure (213; Fig. 10).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a layering method, as taught by Omoto, so to use a pixel structure with a layering method for providing an organic EL display device that allows for formation of capacitance elements with reduced layout areas of the pixels and an electronic apparatus having the organic EL display device (Paragraph [0008]).
Claims 4-6 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (CN 115988905 A (See US 2024/0324295 A1 for official translation and rejection citations)) in view of Choi (US 2010/0156762 A1) and Omoto (US 2012/0175645 A1).
Claims 4 and 12, Jiang (Fig. 1-9) discloses a pixel drive circuit (20; Fig. 5; Paragraph [0043]), arranged on the drive substrate (10; Fig. 1) according to claim 1 (see rejection to claim 1 above). Jiang (Fig. 1-9) discloses a display device (Paragraph [0006]; wherein discloses a display panel), comprising a pixel drive circuit (20; Fig. 5; Paragraph [0043]) which is arranged on the drive substrate (10; Fig. 1) according to claim 1 (see rejection to claim 1 above).
Jiang does not expressly disclose the pixel drive circuit comprising:
a first drive module, wherein a control end of the first drive module is configured for receiving a dimming signal, an input end of the first drive module is connected to an operating power line for receiving an operating voltage, and an output end of the first drive module is respectively connected to first ends of multiple pixel circuits and configured for sending the operating voltage to the first ends of the multiple pixel circuits;
a second drive module, wherein a control end of the second drive module is configured for receiving an initial signal, an input end of the second drive module is connected to an initial power line for receiving an initial voltage, and an output end of the second drive module is respectively connected to the first ends of the multiple pixel circuits and configured for sending the initial voltage to the first ends of the multiple pixel circuits;
a scan line, wherein the scan line is respectively connected to second end of each pixel circuit and configured for sending a scanning signal to second ends of the multiple pixel circuits;
multiple data lines corresponding to the multiple pixel circuits, wherein the multiple data lines are respectively connected to corresponding third ends of the multiple pixel circuits for sending a reference voltage or a data voltage to the corresponding third ends of the multiple pixel circuits; and
a common ground line, the common ground line is respectively connected to fourth ends of the multiple pixel circuits and configured for grounding the fourth ends of the multiple pixel circuits;
wherein, each of the multiple pixel circuits comprises:
a third drive module, a control end of the third drive module is connected to the scan line, an input end of the third drive module is connected to a corresponding data line, and an output end of the third drive module is connected to a first node;
a fourth drive module, a control end of the fourth drive module is connected to the first node, an input end of the fourth drive module is connected to a second node, wherein the second node is connected to the output end of the first drive module and the output end of the second drive module, and an output end of the fourth drive module is connected to a third node;
a light-emitting device, an anode of the light-emitting device is connected to the third node, and a cathode of the light-emitting device is connected to the common ground line; and
a first storage unit and a second storage unit, a first end of the first storage unit is connected to the first node, a second end of the first storage unit is connected to the third node and a first end of the second storage unit.
Choi (Fig. 1-8) discloses the pixel drive circuit (Fig. 2 and 3) comprising:
a first drive module (160 and CM1; Fig. 2 and 3), wherein a control end of the first drive module (CM1; Fig. 3) is configured for receiving a dimming signal (Ei; Fig. 3), an input end of the first drive module (CM1; Fig. 3) is connected to an operating power line (ELVDD; Fig. 2) for receiving an operating voltage (ELVDD; Fig. 3), and an output end of the first drive module (CM1; Fig. 3) is respectively connected to (160 and 140; Fig. 4; wherein figure shows circuit 160 is connected to multiple pixels 140 in single row) first ends (M1 and 140; Fig. 3) of multiple pixel circuits (140; Fig. 2) and configured for sending (Paragraph [0057]) the operating voltage (ELVDD; Fig. 3) to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
a second drive module (160 and CM2; Fig. 2 and 3), wherein a control end of the second drive module (CM2; Fig. 3) is configured for receiving an initial signal (Si-2; Fig. 3), an input end of the second drive module (CM2; Fig. 3) is connected to an initial power line (Vint; Fig. 2) for receiving an initial voltage (Vint; Fig. 3), and an output end of the second drive module (CM2; Fig. 3) is respectively connected to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2) and configured for sending (Paragraph [0063]) the initial voltage (Vint; Fig. 3) to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
a scan line (Si; Fig. 2 and 3), wherein the scan line (Si; Fig. 3) is respectively connected to second end (M2; Fig. 3) of each pixel circuit (140; Fig. 4) and configured for (Paragraph [0051]) sending a scanning signal (Si; Fig. 2) to second ends (M2; Fig. 3) of the multiple pixel circuits (140: Fig. 2);
multiple data lines (D1-Dm; Fig. 2) corresponding to the multiple pixel circuits (140: Fig. 2), wherein the multiple data lines (D1-Dm; Fig. 2) are respectively connected to corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140; Fig. 2) for sending a reference voltage or a data voltage (Paragraph [0051]) to the corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140: Fig. 2); and
a common ground line (ELVSS; Fig. 2 and 3), the common ground line (ELVSS; Fig. 2 and 3) is respectively connected to fourth ends of the multiple pixel circuits and configured for grounding the fourth ends (OLED; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
wherein, each of the multiple pixel circuits (140; Fig. 2 and 3) comprises:
a third drive module (M2; Fig. 3), a control end of the third drive module (M2; Fig. 3) is connected to the scan line (Si; Fig. 3), an input end of the third drive module (M2; Fig. 3) is connected to a corresponding data line (Dm; Fig. 3), and an output end of the third drive module (M2; Fig. 3) is connected to a first node (N1; Fig. 3);
a fourth drive module (M1; Fig. 3), a control end of the fourth drive module (M1; Fig. 3) is connected to the first node (N1; Fig. 3), an input end of the fourth drive module (M1; Fig. 3) is connected to a second node (Paragraph [0050]; wherein discloses a first electrode; Fig. 3; wherein figure shows the first electrode of transistor M1 is connected to a node that is connected to both transistors CM1 and CM2), wherein the second node (Fig. 3; wherein figure shows the first electrode of transistor M1 is connected to a node that is connected to both transistors CM1 and CM2) is connected to the output end of the first drive module (CM1; Fig. 3) and the output end of the second drive module (CM2; Fig. 3), and an output end of the fourth drive module (M1; Fig. 3) is connected to a third node (N2; Fig. 3);
a light-emitting device (OLED: Fig. 3), an anode of the light-emitting device (OLED; Fig. 3) is connected to the third node (N2; Fig. 3), and a cathode of the light-emitting device (OLED; Fig. 3) is connected to the common ground line (ELVSS; Fig. 3); and
a first storage unit (C1; Fig. 3) and a second storage unit (C2; Fig. 3), a first end of the first storage unit (C1; Fig. 3) is connected to the first node (N1; Fig. 3), a second end of the first storage unit (C1; Fig. 3) is connected to the third node (N2; Fig. 3) and a first end of the second storage unit (C2; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Jiang in view of Choi does not expressly disclose a second end of the second storage unit is connected to the cathode of the light-emitting device and the common ground line.
Omoto (Fig. 10 and 11) discloses a second end of the second storage unit (Csub; Fig. 11A) is connected to the cathode of the light-emitting device (21; Fig. 11A) and the common ground line (34; Fig. 2; Paragraph [0067]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang in view of Choi’s pixel structure by applying a layering method, as taught by Omoto, so to use a pixel structure with a layering method for providing an organic EL display device that allows for formation of capacitance elements with reduced layout areas of the pixels and an electronic apparatus having the organic EL display device (Paragraph [0008]).
Claims 5 and 13, Choi (Fig. 1-8) discloses wherein the pixel drive circuit (160; Fig. 2 and 3) further comprises:
a fifth drive module (160 and CM1; Fig. 2 and 3; wherein figure shows element 160 is applied for each row of pixels), a control end of the fifth drive module (CM1; Fig. 3) is configured for receiving the dimming signal (Ei; Fig. 3), an input end of the fifth drive module (CM1; Fig. 3) is connected to the operating power line (ELVDD; Fig. 2) for receiving the operating voltage (ELVDD; Fig. 3), and an output end of the fifth drive module (CM1; Fig. 3) is respectively connected to first ends (M1; Fig. 3) of a preset number of pixel circuits (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits) among the multiple pixel circuits (140; Fig. 2) in one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits), and configured for sending the operating voltage (ELVDD; Fig. 3) to the first ends (M1; Fig. 3) of the preset number of pixel circuits (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits);
a sixth drive module (160 and CM2; Fig. 2 and 3; wherein figure shows element 160 is applied for each row of pixels), a control end of the sixth drive module (CM2; Fig. 3) is configured for receiving the initial signal (Si-2; Fig. 3), an input end of the sixth drive module (CM2; Fig. 3) is configured to be connected to the initial power line (Vint; Fig. 2) and configured for receiving the initial voltage (Vint; Fig. 3), and an output end of the sixth drive module (CM2; Fig. 3) is respectively connected to first ends (M1; Fig. 3) of multiple pixel circuits in one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits) and configured for sending the initial voltage (Vint; Fig. 3) to the first ends (M1; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits);
a scan line (Si; Fig. 2 and 3), the scan line (Si; Fig. 3) is respectively connected to second ends (M2; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows scan line Si connected to a row pixel circuits) and configured for sending the scanning signal (Fig. 4) to the second ends (M2; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows scan line Si connected to a row pixel circuits);
multiple data lines (D1-Dm; Fig. 2) corresponding to the multiple pixel circuits (140; Fig. 2) in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140), the multiple data lines (D1-Dm; Fig. 2) are respectively connected to corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140; Fig. 2) in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140) and configured for sending the reference voltage or the data voltage (Dm; Fig. 3) to the corresponding third ends (M2; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140);
a common ground line (ELVSS; Fig. 2), the common ground line (ELVSS; Fig. 2) is respectively connected to fourth ends (OLED; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140) and configured for grounding (ELVSS; Fig. 3) the fourth ends (OLED; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Claims 6 and 14, Choi (Fig. 1-8) discloses wherein the first drive module (CM1; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels), the second drive module (CM2; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels), the third drive module (M1; Fig. 3), the fourth drive module (M2; Fig. 3), the fifth drive module (CM1; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels) and the sixth drive module (CM2; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels) are all thin film transistors (Fig. 3; wherein figure shows a plurality of transistors); and
the first storage unit (C1; Fig. 3) and the second storage unit (C2; Fig. 3) are both capacitors (Fig. 3; wherein figure shows a plurality of capacitors).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (CN 115988905 A (See US 2024/0324295 A1 for official translation and rejection citations)) in view of Choi (US 2010/0156762 A1), Omoto (US 2012/0175645 A1), and Kimura et al (US 2015/0187272 A1).
Claim 7, Jiang (Fig. 1-9) discloses a pixel drive circuit (20; Fig. 5; Paragraph [0043]), arranged on the drive substrate (10; Fig. 1) according to claim 1 (see rejection to claim 1 above).
Jiang does not expressly disclose the pixel drive circuit comprising:
a first drive module, wherein a control end of the first drive module is configured for receiving a dimming signal, an input end of the first drive module is connected to an operating power line for receiving an operating voltage, and an output end of the first drive module is respectively connected to first ends of multiple pixel circuits and configured for sending the operating voltage to the first ends of the multiple pixel circuits;
a second drive module, wherein a control end of the second drive module is configured for receiving an initial signal, an input end of the second drive module is connected to an initial power line for receiving an initial voltage, and an output end of the second drive module is respectively connected to the first ends of the multiple pixel circuits and configured for sending the initial voltage to the first ends of the multiple pixel circuits;
a scan line, wherein the scan line is respectively connected to second end of each pixel circuit and configured for sending a scanning signal to second ends of the multiple pixel circuits;
multiple data lines corresponding to the multiple pixel circuits, wherein the multiple data lines are respectively connected to corresponding third ends of the multiple pixel circuits for sending a reference voltage or a data voltage to the corresponding third ends of the multiple pixel circuits; and
a common ground line, the common ground line is respectively connected to fourth ends of the multiple pixel circuits and configured for grounding the fourth ends of the multiple pixel circuits;
wherein, each of the multiple pixel circuits comprises:
a third drive module, a control end of the third drive module is connected to the scan line, an input end of the third drive module is connected to a corresponding data line, and an output end of the third drive module is connected to a first node;
a fourth drive module, a control end of the fourth drive module is connected to the first node, an input end of the fourth drive module is connected to a second node, wherein the second node is connected to the output end of the first drive module and the output end of the second drive module, and an output end of the fourth drive module is connected to a third node;
a light-emitting device, an anode of the light-emitting device is connected to the third node, and a cathode of the light-emitting device is connected to the common ground line; and
a first storage unit and a second storage unit, a first end of the first storage unit is connected to the first node, a second end of the first storage unit is connected to the third node and a first end of the second storage unit.
Choi (Fig. 1-8) discloses the pixel drive circuit (Fig. 2 and 3) comprising:
a first drive module (160 and CM1; Fig. 2 and 3), wherein a control end of the first drive module (CM1; Fig. 3) is configured for receiving a dimming signal (Ei; Fig. 3), an input end of the first drive module (CM1; Fig. 3) is connected to an operating power line (ELVDD; Fig. 2) for receiving an operating voltage (ELVDD; Fig. 3), and an output end of the first drive module (CM1; Fig. 3) is respectively connected to (160 and 140; Fig. 4; wherein figure shows circuit 160 is connected to multiple pixels 140 in single row) first ends (M1 and 140; Fig. 3) of multiple pixel circuits (140; Fig. 2) and configured for sending (Paragraph [0057]) the operating voltage (ELVDD; Fig. 3) to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
a second drive module (160 and CM2; Fig. 2 and 3), wherein a control end of the second drive module (CM2; Fig. 3) is configured for receiving an initial signal (Si-2; Fig. 3), an input end of the second drive module (CM2; Fig. 3) is connected to an initial power line (Vint; Fig. 2) for receiving an initial voltage (Vint; Fig. 3), and an output end of the second drive module (CM2; Fig. 3) is respectively connected to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2) and configured for sending (Paragraph [0063]) the initial voltage (Vint; Fig. 3) to the first ends (M1 and 140; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
a scan line (Si; Fig. 2 and 3), wherein the scan line (Si; Fig. 3) is respectively connected to second end (M2; Fig. 3) of each pixel circuit (140; Fig. 4) and configured for (Paragraph [0051]) sending a scanning signal (Si; Fig. 2) to second ends (M2; Fig. 3) of the multiple pixel circuits (140: Fig. 2);
multiple data lines (D1-Dm; Fig. 2) corresponding to the multiple pixel circuits (140: Fig. 2), wherein the multiple data lines (D1-Dm; Fig. 2) are respectively connected to corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140; Fig. 2) for sending a reference voltage or a data voltage (Paragraph [0051]) to the corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140: Fig. 2); and
a common ground line (ELVSS; Fig. 2 and 3), the common ground line (ELVSS; Fig. 2 and 3) is respectively connected to fourth ends of the multiple pixel circuits and configured for grounding the fourth ends (OLED; Fig. 3) of the multiple pixel circuits (140; Fig. 2);
wherein, each of the multiple pixel circuits (140; Fig. 2 and 3) comprises:
a third drive module (M2; Fig. 3), a control end of the third drive module (M2; Fig. 3) is connected to the scan line (Si; Fig. 3), an input end of the third drive module (M2; Fig. 3) is connected to a corresponding data line (Dm; Fig. 3), and an output end of the third drive module (M2; Fig. 3) is connected to a first node (N1; Fig. 3);
a fourth drive module (M1; Fig. 3), a control end of the fourth drive module (M1; Fig. 3) is connected to the first node (N1; Fig. 3), an input end of the fourth drive module (M1; Fig. 3) is connected to a second node (Paragraph [0050]; wherein discloses a first electrode; Fig. 3; wherein figure shows the first electrode of transistor M1 is connected to a node that is connected to both transistors CM1 and CM2), wherein the second node (Fig. 3; wherein figure shows the first electrode of transistor M1 is connected to a node that is connected to both transistors CM1 and CM2) is connected to the output end of the first drive module (CM1; Fig. 3) and the output end of the second drive module (CM2; Fig. 3), and an output end of the fourth drive module (M1; Fig. 3) is connected to a third node (N2; Fig. 3);
a light-emitting device (OLED: Fig. 3), an anode of the light-emitting device (OLED; Fig. 3) is connected to the third node (N2; Fig. 3), and a cathode of the light-emitting device (OLED; Fig. 3) is connected to the common ground line (ELVSS; Fig. 3); and
a first storage unit (C1; Fig. 3) and a second storage unit (C2; Fig. 3), a first end of the first storage unit (C1; Fig. 3) is connected to the first node (N1; Fig. 3), a second end of the first storage unit (C1; Fig. 3) is connected to the third node (N2; Fig. 3) and a first end of the second storage unit (C2; Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Jiang in view of Choi does not expressly disclose a second end of the second storage unit is connected to the cathode of the light-emitting device and the common ground line.
Omoto (Fig. 10 and 11) discloses a second end of the second storage unit (Csub; Fig. 11A) is connected to the cathode of the light-emitting device (21; Fig. 11A) and the common ground line (34; Fig. 2; Paragraph [0067]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang in view of Choi’s pixel structure by applying a layering method, as taught by Omoto, so to use a pixel structure with a layering method for providing an organic EL display device that allows for formation of capacitance elements with reduced layout areas of the pixels and an electronic apparatus having the organic EL display device (Paragraph [0008]).
Jiang in view of Choi and Omoto does not expressly disclose a drive method, applied to drive a pixel drive circuit:
the drive method comprising:
in a reset phase, the first drive module is controlled to switch off via a low-level dimming signal, the second drive module is controlled to switch on via a high-level initial signal, the scan line stops sending a high-level scanning signal, the data voltage from a data line provided in a previous frame is retained at the first node, the fourth drive module is controlled to switch on through the data voltage at the first node, the initial voltage is written to the third node to reset the light-emitting device, and the light-emitting device does not emit light;
in a compensation phase, the second drive module is controlled to switch off via a low-level initial signal, the first drive module is controlled to switch on via a high-level dimming signal, the operating voltage from the operating power line is written to the second node, the third drive module is controlled to switch on via the high-level scanning signal from the scan line, the reference voltage from the data line is written to the first node, the fourth drive module is controlled to switch on through the reference voltage, the third node is charged by the operating voltage, until a voltage at the third node rises to a preset interval voltage, then the fourth drive module is switched off, and the light-emitting device does not emit light;
in a writing phase, the first drive module is controlled to switch off via the low-level dimming signal, the third drive module is controlled to switch on via the high-level scanning signal from the scan line, the data voltage from the data line is written to the first node, the voltage at the third node is a coupling voltage, a driving voltage of the fourth drive module is a coupling driving voltage, and the light-emitting device does not emit light; and
in a light-emitting phase, the first drive module is controlled to switch on via the high-level dimming signal, and a driving current is generated by the fourth drive module under an excitation of the coupling driving voltage, and the light-emitting device is driven by the driving current to emit light;
wherein, the data voltage and the reference voltage of the previous frame are both greater than or equal to the initial voltage.
Kimura (Fig. 1-24) discloses a drive method (Fig. 6), applied to drive a pixel drive circuit (Fig. 12):
the drive method (Fig. 6) comprising:
in a reset phase (Source Initialization; Fig. 6), the first drive module (BCT; Fig. 18) is controlled to switch off (BG; Fig. 12) via a low-level dimming signal (BG; Fig. 6; wherein figure shows signal BG is low to disable transistor BCT), the second drive module (RST; Fig. 12) is controlled to switch on (RG; Fig. 12) via a high-level initial signal (RG; Fig. 6; wherein figure shows signal RG is high level to enable transistor RST), the scan line stops sending a high-level scanning signal (SG1 and SG2; Fig. 6; wherein during Source Initialization scan lines SG1 and SG2 are a low level), the data voltage from a data line provided in a previous frame is retained at the first node (Fig. 6; wherein voltage stored on capacitor Cs is not adjusted during Source Initialization period but rather in the next period Gate Initialization), the fourth drive module (DRT; Fig. 12) is controlled to switch on through the data voltage at the first node (Cs; Fig. 12), the initial voltage (Vrst; Fig. 12) is written to the third node (Paragraph [0120]) to reset the light-emitting device (OLED; Fig. 12), and the light-emitting device does not emit light (Fig. 6; wherein light emitting is only during light emitting period);
in a compensation phase (OC1 and OC2; Fig. 6; Paragraph [0087]; wherein discloses a offset cancel period), the second drive module (RST; Fig. 12) is controlled to switch off (RG; Fig. 12) via a low-level initial signal (RG; Fig. 6; wherein figure shows during OC1 and OC2 the drive signal RG at a low level), the first drive module (BCT; Fig. 12) is controlled to switch on (BG; Fig. 12) via a high-level dimming signal (BG; Fig. 6; wherein figure shows during OC1 and OC2 the drive signal BG at a high level), the operating voltage (Pvdd; Fig. 12) from the operating power line (Pvdd; Fig. 12) is written to the second node (DRT; Fig. 6), the third drive module (SST; Fig. 12) is controlled to switch on (SG2 or SG1; Fig. 12) via the high-level scanning signal from the scan line (SG1 and SG2; Fig. 6; wherein figure shows during OC1 and OC2 the drive signal SG1 and SG2 at a high level), the reference voltage (Vini; Fig. 6) from the data line (Vsig; Fig. 6 and 12) is written to the first node (Cs; Fig. 12), the fourth drive module (DRT; Fig. 12) is controlled to switch on (Paragraph [0088]) through the reference voltage (Vini; Fig. 6), the third node is charged by the operating voltage (Paragraph [0088-0090]), until a voltage at the third node rises to a preset interval voltage (Paragraph [0088-0090]), then the fourth drive module (DRT; Fig. 12) is switched off (Paragraph [0088-0090]), and the light-emitting device does not emit light (Fig. 6; wherein light emitting is only during light emitting period);
in a writing phase (Write; Fig. 6), the first drive module (BCT; Fig. 12) is controlled to switch off (BG; Fig. 12) via the low-level dimming signal (BG; Fig. 6; wherein figure shows during write period the signal BS is low level), the third drive module (SST; Fig. 12) is controlled to switch on (SG2 or SG1; Fig. 12) via the high-level scanning signal from the scan line (SG1 and SG2; Fig. 6; wherein during write period the scan signals SG1 and SG2 are at a high level), the data voltage (R,G, B, W; Fig. 6) from the data line (Vsig; Fig. 6 and 12) is written to the first node (Cs; Fig. 12), the voltage at the third node is a coupling voltage (Paragraph [0095-0096]), a driving voltage of the fourth drive module (DRT; Fig. 12) is a coupling driving voltage (Paragraph [0095-0096]), and the light-emitting device does not emit light (Fig. 6; wherein light emitting is only during light emitting period); and
in a light-emitting phase (Light Emitting Period; Fig. 6), the first drive module (BCT; Fig. 12) is controlled to switch on (BG; fig. 12) via the high-level dimming signal BG; Fig. 6; wherein during Light Emitting Period the signal BG is a high level), and a driving current is generated by the fourth drive module (DRT; Fig. 12) under an excitation of the coupling driving voltage (Paragraph [0101-0104]), and the light-emitting device (OLED; Fig. 12) is driven by the driving current to emit light (Paragraph [0101-0104]);
wherein, the data voltage (R, G, B, W; Fig. 6) and the reference voltage (Vini; Fig. 6; Paragraph [0086]; wherein discloses 2V) of the previous frame are both greater than or equal to the initial voltage (PVSS; Fig. 18; Paragraph [0050]; wherein discloses PVSS is 1.5 voltages).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang in view of Choi and Omoto’s pixel drive circuit by applying a driving method, as taught by Kimura, so to use a pixel drive circuit with a driving method for providing process prevents problems such as poorness, non-uniformity, and roughness in the display quality due to the variations in the threshold value of and mobility in the driving transistor DRT, and provides a high-quality image display which realizes a high-definition active-matrix display device with improved display quality (Paragraph [0107]).
Claim 8, Choi (Fig. 1-8) discloses wherein the pixel drive circuit (160; Fig. 2 and 3) further comprises:
a fifth drive module (160 and CM1; Fig. 2 and 3; wherein figure shows element 160 is applied for each row of pixels), a control end of the fifth drive module (CM1; Fig. 3) is configured for receiving the dimming signal (Ei; Fig. 3), an input end of the fifth drive module (CM1; Fig. 3) is connected to the operating power line (ELVDD; Fig. 2) for receiving the operating voltage (ELVDD; Fig. 3), and an output end of the fifth drive module (CM1; Fig. 3) is respectively connected to first ends (M1; Fig. 3) of a preset number of pixel circuits (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits) among the multiple pixel circuits (140; Fig. 2) in one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits), and configured for sending the operating voltage (ELVDD; Fig. 3) to the first ends (M1; Fig. 3) of the preset number of pixel circuits (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits);
a sixth drive module (160 and CM2; Fig. 2 and 3; wherein figure shows element 160 is applied for each row of pixels), a control end of the sixth drive module (CM2; Fig. 3) is configured for receiving the initial signal (Si-2; Fig. 3), an input end of the sixth drive module (CM2; Fig. 3) is configured to be connected to the initial power line (Vint; Fig. 2) and configured for receiving the initial voltage (Vint; Fig. 3), and an output end of the sixth drive module (CM2; Fig. 3) is respectively connected to first ends (M1; Fig. 3) of multiple pixel circuits in one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits) and configured for sending the initial voltage (Vint; Fig. 3) to the first ends (M1; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows circuit 160 connected to a row pixel circuits);
a scan line (Si; Fig. 2 and 3), the scan line (Si; Fig. 3) is respectively connected to second ends (M2; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows scan line Si connected to a row pixel circuits) and configured for sending the scanning signal (Fig. 4) to the second ends (M2; Fig. 3) of the multiple pixel circuits in the one row (140; Fig. 2; wherein figure shows scan line Si connected to a row pixel circuits);
multiple data lines (D1-Dm; Fig. 2) corresponding to the multiple pixel circuits (140; Fig. 2) in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140), the multiple data lines (D1-Dm; Fig. 2) are respectively connected to corresponding third ends (M2; Fig. 3) of the multiple pixel circuits (140; Fig. 2) in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140) and configured for sending the reference voltage or the data voltage (Dm; Fig. 3) to the corresponding third ends (M2; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140);
a common ground line (ELVSS; Fig. 2), the common ground line (ELVSS; Fig. 2) is respectively connected to fourth ends (OLED; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140) and configured for grounding (ELVSS; Fig. 3) the fourth ends (OLED; Fig. 3) of the multiple pixel circuits in the one row (Fig. 2; wherein figure shows at least a row of pixel circuits 140).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Claim 9, Choi (Fig. 1-8) discloses wherein the first drive module (CM1; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels), the second drive module (CM2; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels), the third drive module (M1; Fig. 3), the fourth drive module (M2; Fig. 3), the fifth drive module (CM1; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels) and the sixth drive module (CM2; Fig. 3; 160; Fig. 2; wherein figure shows element 160 is applied for each row of pixels) are all thin film transistors (Fig. 3; wherein figure shows a plurality of transistors); and
the first storage unit (C1; Fig. 3) and the second storage unit (C2; Fig. 3) are both capacitors (Fig. 3; wherein figure shows a plurality of capacitors).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang’s pixel structure by applying a driving method, as taught by Choi, so to use a pixel structure with a driving method for providing an organic light emitting display device capable of compensating for threshold voltage of a driving transistor (Paragraph [0009]).
Claim 10, Kimura (Fig. 1-24) discloses wherein a calculation formula (Paragraph [0095]) of the coupling voltage is expressed by:
V_N3 = Vref- Vth + α×(Vdata - Vref); and (Paragraph [0095])
a calculation formula of the coupling driving voltage (Paragraph [0096]) is expressed by:
VGS =(1- α)×(Vdata-Vref) + Vth; (Paragraph [0096])
wherein, V_N3 is the coupling voltage (Paragraph [0095]), VGS is the coupling driving voltage (Paragraph [0096]), Vref is the reference voltage (Paragraph [0095-0096]), Vth is a threshold voltage (Paragraph [0095-0096]) of the fourth drive module (DRT; Fig. 12), Vdata is the data voltage (Paragraph [0095-0096]), α is a capacitance coefficient (Paragraph [0095-0096]), and α = C1/(C1+C2) (Paragraph [0095-0096]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang in view of Choi and Omoto’s pixel drive circuit by applying a driving method, as taught by Kimura, so to use a pixel drive circuit with a driving method for providing process prevents problems such as poorness, non-uniformity, and roughness in the display quality due to the variations in the threshold value of and mobility in the driving transistor DRT, and provides a high-quality image display which realizes a high-definition active-matrix display device with improved display quality (Paragraph [0107]).
Claim 11, Kimura (Fig. 1-24) discloses wherein a range of the preset interval voltage is:
Vinterval ≥ Vref – Vth; (Paragraph [0089])
wherein, Vinterval is the preset interval voltage (Paragraph [0089]; wherein discloses “the source potential of the driving transistor DRT is set to, approximately, Vini-Vth”), Vref is the reference voltage (Vini; Fig. 6; Paragraph [0089]), and Vth is a threshold voltage (Vth; Paragraph [0089]) of the fourth drive module (DRT; Fig. 12).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Jiang in view of Choi and Omoto’s pixel drive circuit by applying a driving method, as taught by Kimura, so to use a pixel drive circuit with a driving method for providing process prevents problems such as poorness, non-uniformity, and roughness in the display quality due to the variations in the threshold value of and mobility in the driving transistor DRT, and provides a high-quality image display which realizes a high-definition active-matrix display device with improved display quality (Paragraph [0107]).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 02/05/2026