Prosecution Insights
Last updated: April 19, 2026
Application No. 19/246,710

Display Device

Non-Final OA §102
Filed
Jun 24, 2025
Examiner
CHOW, VAN NGUYEN
Art Unit
2627
Tech Center
2600 — Communications
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
97%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
696 granted / 838 resolved
+21.1% vs TC avg
Moderate +14% lift
Without
With
+13.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
25 currently pending
Career history
863
Total Applications
across all art units

Statute-Specific Performance

§101
3.6%
-36.4% vs TC avg
§103
42.3%
+2.3% vs TC avg
§102
37.2%
-2.8% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 29-31, 35 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by TIAN US 20240032386. Regarding claim 29, TIAN US 2024/0032386, figs. 1, 3, 9-13, discloses the display device comprising: a substrate including a display area (fig 1,, A display panel includes a display area (DA) and a peripheral area (PA) surrounding the display area (DA)); a plurality of light emitting devices in the display area; a plurality of column lines in the display area, the plurality of column lines extending in a column direction; a plurality of row lines in the display area, the plurality of row lines extending in a row direction; and a plurality of drivers on the substrate and in the display area, the plurality of drivers configured to drive the plurality of column lines and the plurality of row lines, wherein each of the plurality of column lines is electrically connected in common with a first electrode of each of two or more light emitting devices arranged in a same column among the plurality of light emitting devices, wherein each of the plurality of row lines is electrically connected in common with a second electrode of each of two or more light emitting devices arranged in a same row among the plurality of light emitting devices (all of the second pixel units include M columns*N rows of light emitting devices, M columns*N rows of bottom drive circuits, and M*N anode leads, where the anode leads are used to connect the light emitting devices to the bottom drive circuits, the bottom drive circuits are disposed at lower layers of the light emitting devices, and both M and N are natural numbers. A dimension of an area enclosed by the light emitting devices in the some or all of the second pixel units is greater than a dimension of an area enclosed by the bottom drive circuits corresponding to the light emitting devices in the pixel units, and therefore there are gaps between the some or all of the second pixel units (The light emitting device 501 is configured to emit light. The light emitting device 501 may emit one or more of red light, green light, and blue light. This is not limit in this embodiment of this application. For example, each light emitting device 501 may alternatively emit light of other colors such as cyan, magenta, and yellow. Light emitted by a plurality of light emitting devices 501 constitutes a display image. The light emitting device 501 may be an organic light emitting diode. Sizes and shapes of the light-emitting devices 501 may be uniform, or may not be uniform). Regarding claim 30, TIAN US 2024/0032386, figs. 1, 3, 9-13, discloses the display device of claim 29, wherein the plurality of row lines include a first row line, wherein a first low-potential voltage is applied to the first row line during a first period, wherein a second low-potential voltage that is greater than the first low-potential voltage is applied to the first row line during a second period different from the first period (FIG. 7, one pixel unit may include two rows*four columns of light emitting devices. The first row of light emitting devices separately emit red light, green light, blue light, and green light, and the second row of light emitting devices separately emit blue light, green light, red light, and green light. A color of light emitted by the light emitting devices in the pixel unit and an arrangement sequence of the light emitting devices are not limited in this embodiment of this application) (The capacitor Cst may be connected to the second transistor T2 and a supply voltage line. The capacitor Cst is configured to store a voltage corresponding to a difference between a voltage corresponding to the data signal received from the second transistor T2 and a first supply voltage ELVDD supplied to the supply voltage line. The supply voltage line may be spaced parallel to the scanning line or the data line). Regarding claim 31, TIAN US 2024/0032386, figs. 1, 3, 9-13, discloses the display device of claim 30, wherein a signal having a swing voltage level is applied to the first row line during a third period that is different from the first period and the second period (The second transistor T2 is configured to transmit, to the first transistor T1 based on a switching voltage input to the scanning line, a data signal input from the data line. [0110] The capacitor Cst may be connected to the second transistor T2 and a supply voltage line. The capacitor Cst is configured to store a voltage corresponding to a difference between a voltage corresponding to the data signal received from the second transistor T2 and a first supply voltage ELVDD supplied to the supply voltage line. The supply voltage line may be spaced parallel to the scanning line or the data line. The first transistor T1 is a drive transistor, and may be connected to the supply voltage line and the capacitor Cst. The first transistor T1 is configured to control, in response to a voltage value stored in the capacitor Cst, a drive current Ioled flowing through the light emitting device 501, to control light emitting intensity of the light emitting device 501). Regarding claim 35, TIAN US 2024/0032386, figs. 1, 3, 9-13, discloses a display device comprising: a substrate including a display area; a plurality of light emitting devices in the display area (fig 1, A display panel includes a display area (DA) and a peripheral area (PA) surrounding the display area (DA)), the plurality of light emitting devices comprising a first light emitting device with a defect (pars. 131, 139, 157); a plurality of column lines comprising a first column line that is electrically connected to the first light emitting device; wherein a predefined low level voltage is supplied to the first column line during a first display-on driving period predefined for the first light emitting device (see pars. 66, 109, 110, 111), and wherein, during the first display-on driving period, other light emitting devices connected to the first column line except for the first light emitting device do not emit light (FIG. 13 shows an example of 13 columns of pixel units 1301 and a plurality of data lines 1302. Some of the light emitting devices of the 9th column to the 16th column and some of the light emitting devices of the 37th column to the 44th column are located in the UDC area 1303. Light emitting devices in some of the pixel units 1301 in the hole 1304 and a surrounding area of the hole 1304 are missing, and therefore a quantity of light emitting devices of the 17th column to the 36th column is small). Allowable Subject Matter The following is an examiner’s statement of reasons for allowance: Claims 1-28 are allowed. Kim et al. US 2024/0290767, figs. 3, 10, 12, discloses a display device 100 may include: a display panel PN; an active area AA and a non-active area NA surrounding the active area; and a plurality of pixels PX in the active area AA (see, e.g., FIGS. 1 to 3). Each pixel PX of the plurality of pixels PX may include electrode areas EA. Each electrode area EA of the electrode areas EA may include a first electrode area EA1 and a second electrode area EA2 adjacent to the first electrode area EA1. Positions of the first and second electrode areas EA1 and EA2 relative to each other may be the same for all of the electrode areas EA in the plurality of pixels PX. Each pixel PX of the plurality of pixels PX may include a plurality of light emitting diodes 130. Each light emitting diode 130 of the plurality of light emitting diodes 130 may be disposed in at least one of the first electrode area EA1 or the second electrode area EA2 of a corresponding electrode area EA. The plurality of pixels PX may include a first pixel. (see, e.g., FIGS. 2B, 4A, 4B, 14 and 19). In this example, the corresponding electrode area EA associated with the at least one light emitting diode of the first pixel may correspond to the defective transferring area. A light emitting diode (e.g., the defective light emitting diode 130′) may be absent or misplaced from the first electrode area EA1 of the corresponding electrode area EA that corresponds to the defective transferring area. The at least one light emitting diode of the first pixel may be formed in the second electrode area EA2 of the corresponding electrode area EA of the first pixel during the step S137 of a repair transfer process step S130. None of the references in the art disclose or suggest a display device comprising: a substrate including a display area; a plurality of light emitting devices in the display area; a plurality of column lines in the display area, the plurality of column lines extending in a column direction; a plurality of row lines in the display area, the plurality of row lines extending in a row direction; and a plurality of drivers on the substrate and in the display area, the plurality of drivers configured to drive the plurality of column lines and the plurality of row lines, wherein the plurality of light emitting devices include a first light emitting device with a defect, or a missing area in which the first light emitting device is missing exists in an arrangement of the plurality of light emitting devices, wherein the plurality of column lines include a first column line electrically connected to a first electrode of the first light emitting device or overlapping with at least a part of the missing area, wherein the plurality of row lines include a first row line electrically connected to a second electrode of the first light emitting device or overlapping with at least a part of the missing area, wherein a predefined low level voltage is supplied to the first column line during a first display-on driving period predefined for the first light emitting device. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claims 32-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the references cited in record disclose or suggest the display device of claim 29, wherein the plurality of light emitting devices include a first light emitting device with a defect or a missing area in which the first light emitting device is missing exists in an arrangement of the plurality of light emitting devices, wherein the plurality of column lines include a first column line electrically connected to a first electrode of the first light emitting device or overlapping with at least a portion of the missing area, wherein the plurality of row lines include a first row line electrically connected to a second electrode of the first light emitting device or overlapping with at least a portion of the missing area, wherein a predefined low level voltage is supplied to the first column line during a first display-on driving period predefined for the first light emitting device. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VAN N CHOW/ Primary Examiner, Art Unit 2627
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Prosecution Timeline

Jun 24, 2025
Application Filed
Mar 04, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
97%
With Interview (+13.5%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allow rate.

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