Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu.
Regarding claim 1, Brown discloses a device comprising an output driver coupled to an Input-Output (I/O) pad, the output driver to be enabled by an output driver enable signal to drive a voltage onto the I/O pad. Brown discloses "an input/output driver circuit driving an input/output connection of the integrated circuit digital device," which is "selectable to operate as a digital input/output driver or as a current limited output driver" (Brown, col. 6, l. 62 – col. 7, l. 8 (claim 1); FIG. 7, I/O node 704; FIG. 8, I/O node 804). In the digital output configuration, the driver is a "standard totem pole active output driver" (FIGS. 7–8; col. 3, ll. ~32–42) that drives a voltage onto the I/O node. Brown further discloses that selection is made by an enable signal: "[t]he multiplexers 706 and 710 may be controlled with a current limit enable signal for selecting between the programmable constant current sink 712 and the low side drive circuit 708" (FIG. 7; col. 5, ll. ~33–37), and correspondingly for multiplexers 806, 810 and high side drive circuit 802 (FIG. 8; col. 5, l. ~66 – col. 6, l. ~3). Brown's I/O node is a true input-output node: "a receiver 760 may be used to determine logic levels at the I/O node 704 when used as an input and/or an output node" (FIG. 7; col. 5, ll. ~54–57).
Brown further discloses a current sink coupled to the I/O pad, enabled by a current sink enable signal to sink a current from the I/O pad. Brown discloses a "programmable constant current sink 514" that sinks current from the I/O node 504 (FIG. 5; col. 4, l. ~55 – col. 5, l. ~4) and a "programmable constant current sink 712" coupled to I/O node 704 through multiplexers 706, 710 under control of the current limit enable signal (FIG. 7; col. 5, ll. ~28–37).
Brown further discloses a current source coupled to the I/O pad, enabled by a current source enable signal to supply a current to the I/O pad. Brown discloses a "programmable constant current source 614" that sources current to the I/O node 604 (FIG. 6; col. 5, ll. ~5–22) and a "programmable constant current source 812" coupled to I/O node 804 through multiplexers 806, 810 under control of the current limit enable signal (FIG. 8; col. 5, l. ~58 – col. 6, l. ~8).
Brown discloses the current sink and the current source in alternative embodiments,the sink at FIGS. 5 and 7, the source at FIGS. 6 and 8,rather than disclosing both coupled to a single I/O node in one embodiment. Brown is therefore relied upon for the I/O pad, the selectable output driver, and each of the programmable constant current source and the programmable constant current sink individually, but not for their co-location on a single pad.
Wu remedies this. Wu discloses a single output terminal T_S having coupled to it, simultaneously: (i) a voltage mode drive unit 1420 that couples a first reference voltage V_R1 (the DC power VDD) or a second reference voltage V_R2 (ground) to the output terminal T_S through resistor R_1 via switches S_V1 and S_V3,that is, a driver that drives a voltage onto the terminal; (ii) a current source IS_0, "selectively coupled to the output terminal T_S according to the data input DIN_0" through switch S_C1; and (iii) a current sink IS_0′, likewise "selectively coupled to the output terminal T_S according to the data input DIN_0" through switch S_C3 (Wu, FIG. 14; ¶¶ [0067]–[0070], [0072]). Wu expressly provides that "when one of the current source IS_0 and the current sink IS_0′ is coupled to the output terminal T_S according to the data input DIN_0, the other … is not coupled to the output terminal T_S" (FIG. 14; ¶ [0068]),i.e., the source and the sink are separately and independently enabled at the same terminal. Wu claims the same arrangement: "a current source … selectively coupled to the first output terminal according to the first data input; and a current sink … selectively coupled to the first output terminal according to the first data input; wherein when one of the current source and the current sink is coupled to the first output terminal … the other … is not coupled" (Wu, claim 3), together with "a first voltage mode drive unit, coupled to the first output terminal … arranged for coupling one of a first reference voltage and a second reference voltage to the first output terminal" (Wu, claim 1), and a dedicated switch for each current path (Wu, claim 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date to provide Brown's I/O node with both the programmable constant current sink of Brown FIGS. 5/7 and the programmable constant current source of Brown FIGS. 6/8, arranged as taught by Wu so that each is separately switchable onto the shared node alongside the voltage-driving output driver.
The rationale is twofold. First, the combination unites two of Brown's own disclosed alternatives. Brown teaches the sink configuration and the source configuration as parallel implementations of the same programmable-constant-current I/O driver, using the same multiplexer-plus-enable architecture and the same configuration register (compare FIG. 7, col. 5, ll. ~23–43, with FIG. 8, col. 5, l. ~58 – col. 6, l. ~8). Combining two alternative embodiments disclosed by the same reference, each performing its known function in the combination, is the combination of prior art elements according to known methods to yield predictable results. MPEP § 2143(I)(A); KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007). Second, Wu supplies both the architecture for doing so and the reason: Wu's switch arrangement demonstrates that a current source and a current sink may share one output terminal with a voltage-mode driver without conflict, by switching only one current path onto the terminal at a time (FIG. 14; ¶¶ [0068], [0072]; claims 3–4). Wu further supplies an express benefit of adding a switchable current path to a voltage-driven terminal: because a conventional driver’s "maximum single-ended output level is limited to one half a supply voltage level," selectively outputting the reference current "may increase an electric potential of the output terminal T_S … thereby increasing an output swing while maintaining a low supply voltage level" (¶ [0064]; see also ¶ [0101]). The predictable benefit is a single pin able to drive current in either direction,sourcing to a load referenced to ground and sinking from a load referenced to the supply,rather than requiring the designer to commit a given pin to one polarity at design time, which is precisely the constraint Brown's separate FIG. 7 and FIG. 8 embodiments impose.
Regarding claim 3, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown further discloses that the device is to be configured as one of a digital input, a digital output, a current source and a current sink. Brown's I/O driver circuit is "selectable to operate as a digital input/output driver or as a current limited output driver" (claim 1; col. 6, ll. ~65–67); the receiver 760 determines logic levels "when used as an input" (FIG. 7; col. 5, ll. ~54–57); the totem pole active output driver provides the digital output configuration (FIGS. 7–8; col. 5, ll. ~44–52); and the current limit enable signal selects the current sink (FIG. 7, 712; col. 5, ll. ~33–37) or, in the FIG. 8 embodiment, the current source (812; col. 5, l. ~66 – col. 6, l. ~3).
Claim 2 is rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Chen.
Regarding claim 2, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown contemplates a switched pull-up at the I/O node but does not expressly recite a pull-up resistor enabled by a pull-up enable signal. Brown discloses "switch applications using low current weak pull-ups that may be susceptible to noise," which "may be overcome by setting current output to a low limit and using a direct connection to Vdd through the switch which would then raise the next stage input level closer to Vdd for improved noise tolerance" (col. 2, ll. ~5–11).
Chen discloses this arrangement. Chen discloses a resistance element 101 coupled to the output terminal 102 and to a first voltage level V_tt, together with a switching element 109 (FIG. 1) ⟦col:line⟧, and claims "a resistor; and a switch, coupled to the resistor and a voltage level, wherein the voltage level is substantially half of an operation voltage of the output driving circuit" (Chen, claim 6). The switch selectively couples the resistor between the supply voltage and the output terminal, thereby selectively supplying a voltage to the terminal. Chen's output terminal is an I/O pad of the same character claimed here: "the I/O pad 105 is a data pin or a strobe pin of the memory controller" (FIG. 1) ⟦col:line⟧.
Wu independently discloses the same structure in the combination already relied upon: resistor R_1 coupled between node N_S and output terminal T_S, with node N_S "coupled to the DC power VDD … through the switch S_V1 … according to the data input DIN_0" (Wu, FIG. 14; ¶ [0070]),a resistor selectively coupled to the supply to supply a voltage to the terminal. Wu states it in switch terms as well: "the switch S_V1 is selectively coupled between the reference voltage V_R1 and the output terminal T_S (through the resistor R_1) according to the data input DIN_0" (¶ [0070]), and the switch is exclusive with its ground-side counterpart (¶ [0071]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to provide the I/O pad of Brown as modified with Chen's switched pull-up resistor. Brown supplies the express invitation,it contemplates a selectable weak pull-up to Vdd at the I/O node for noise tolerance (col. 2, ll. ~5–11),and Chen supplies the conventional resistor-plus-switch implementation of it. Chen teaches the purpose: the switched resistance element permits the driver to meet differing interface specifications and to terminate the line so as to "maintain the completeness of the signal to increase the stability of a system" (FIG. 1). Providing a selectable pull-up at a microcontroller I/O pad is the use of a known technique to improve a similar device in the same way, MPEP § 2143(I)(C), and yields the predictable result of defining the pad voltage when the active drivers are disabled.
Claims 4 and 5 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu.
Regarding claim 4, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown further discloses a current source value register, the value of the current supplied by the current source being based on a content of that register. Brown discloses that "[c]onfigurations, e.g., current limiting or non-current limiting, current limit value, etc., for the I/O node … may be stored in a configuration register 758" and, for the sourcing embodiment, configuration register 858 (FIG. 7, col. 5, ll. ~37–43; FIG. 8, col. 6, ll. ~3–8). Brown further discloses that "[a]nother multi-bit register may determine the value of the constant current, whereby the range and resolution of the constant current value may be determined by the number of bits in this register" (col. 1, ll. ~61–65), and claims "a configuration register coupled to the programmable constant current circuit and storing the current value" (Brown, claim 6; col. 7, ll. ~28–32). Applied to the current source 812 of FIG. 8, the register content sets the sourced current value.
Regarding claim 5, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown discloses the identical register arrangement for the sinking configuration: configuration register 758 stores the current limit value for the programmable constant current sink 712 (FIG. 7; col. 5, ll. ~37–43), with the multi-bit register passage (col. 1, ll. ~61–65) and claim 6 (col. 7, ll. ~28–32) applying equally.
In which both the source and the sink are coupled to the shared I/O pad, it would have been obvious to provide each with its own value register as Brown teaches for each configuration separately, so that the sourced and sunk current magnitudes may be set independently. The motivation is Brown's own: the programmed value "maintain[s] the light intensity of the LED at [a] constant level for all operating and manufacturing variables" (col. 1, ll. ~53–58), a benefit that accrues to each current direction independently.
Claims 6 and 8 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Truong.
Regarding claim 6, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown further discloses an input driver coupled to the I/O pad: "a receiver 760 may be used to determine logic levels at the I/O node 704 when used as an input and/or an output node" (FIG. 7, col. 5, ll. ~54–57; see also receiver 560, FIG. 5, col. 5, ll. ~2–4; receiver 860, FIG. 8, col. 6, ll. ~13–16).
Brown does not expressly disclose a Schmitt trigger coupled to the I/O pad. Truong discloses an I/O cell 315 having an I/O pad 605, an input buffer 610 coupled to the pad, an output buffer 645 with output driver circuit 655 that "drive[s] the voltage V_out_0 onto the I/O pad 605," and a hysteresis generator 640 whose "hysteresis generating circuits may be Schmitt trigger circuits",specifically hysteresis circuits 705 and 710, coupled to the input of buffer circuit 620, which is in the input path from I/O pad 605 (Truong, FIGS. 6–7; col. 14, ll. ~34–47 and ~53–67; col. 16, ll. ~1–8 and ~51–54). Truong states it twice: "the hysteresis generating circuits may be Schmitt trigger circuits" (col. 15, ll. ~42–44) and "the hysteresis circuits 705 and 710 may be Schmitt trigger circuits" (col. 16, ll. ~51–54).
It would have been obvious to one of ordinary skill in the art before the effective filing date to provide the input path of Brown's I/O node with Truong's Schmitt trigger hysteresis circuit. Truong states the reason expressly: hysteresis is applied "to mitigate system noise and/or fluctuations in the V_CCIO and/or V_CC levels," preventing the input buffer from "transitioning from low-to-high and high-to-low due to system noise" (col. 2, ll. ~31–48; see also col. 8, ll. ~18–28; col. 15, ll. ~16–19). Applying a known noise-immunity technique to a known input receiver to yield the predictable result of a noise-tolerant input is obvious under MPEP § 2143(I)(C) and KSR, 550 U.S. at 417.
Regarding claim 8, Brown, as modified by Wu and Truong, discloses the device of claim 6 for the reasons discussed above. Truong further discloses an internal circuit to which the input driver provides an input signal: the input path proceeds from I/O pad 605 through buffer circuits 615 and 620 and level-shifter circuit 625, and "the level-shifter circuit 625 transmits the logic block voltage V_ls1_0 to the logic fabric 670 of the PLD" via buffer 660 (FIGS. 6–7; col. 14, l. ~58 – col. 15, l. ~3; col. 20, ll. ~28–40). Brown likewise contemplates the receiver delivering logic levels to the integrated circuit digital device,a microcontroller (Brown, claim 14; col. 7, ll. ~55–57).
Claim 7 is rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Truong.
Regarding claim 7, Brown, as modified by Wu and Truong, discloses the device of claim 6 for the reasons discussed above. Truong further discloses a hysteresis register, the Schmitt trigger providing an amount of hysteresis to a signal at the I/O pad based on a content of that register.
Truong discloses a multi-stage hysteresis generator 640 in which hysteresis circuit 705 provides a first hysteresis voltage V_hysA_0 and hysteresis circuit 710 is selectively turned on or off to add a second, larger hysteresis voltage V_hysB_0, such that the amount of hysteresis applied at the input of buffer circuit 620 is selectable (FIG. 7; col. 17, l. ~40 – col. 18, l. ~45). Truong describes the result as "a multistage hysteresis circuit," in which circuit 710 "may be selectively turned on … or turned off … in response to the enable voltage V_en_0" while circuit 705 "generally remains on" (col. 18, ll. ~31–41).
Truong discloses that the selection is made from stored configuration bits: the hysteresis control circuit 305 includes multiplexer 410 selecting between the comparator output V_comp_0 and a hysteresis enable voltage V_hEnable_0 under selection signal S_0, and "the multiplexer 410, hysteresis enable voltage V_hEnable_0, and/or selection signal S_0 may be programmed by configuration bits" (FIG. 4; col. 11, ll. ~24–28). Those configuration bits are stored in the PLD's array of configuration memory cells, which "may be volatile memory cells (e.g., RAM cells, such as SRAM cells)" and "may be referred to as configuration RAM (CRAM) cells" (col. 6, ll. ~29–34). A set of addressable memory cells whose stored content determines the amount of hysteresis applied to the pad signal is a hysteresis register under its broadest reasonable interpretation.
It would have been obvious to provide the hysteresis of the modified Brown device as a register-programmed amount, for the reason Truong gives: register control "provide[s] the user with flexibility to cause the lower hysteresis voltage or the higher hysteresis voltage to be generated and applied" as the interface voltage and noise environment require (col. 11, ll. ~13–20),the same flexibility rationale Brown applies to its own register-programmed current value.
Ground 6,Claims 9–12: Brown in view of Wu (claims 10, 12), further in view of Wyatt (claims 9, 11)
Claims 10 and 12 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu.
Regarding claim 10, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown further discloses that the current sink comprises a current mirror. Brown discloses a detailed implementation of the programmable constant current sink in which "[t]ransistor 1054 and constant current source 1056 are used to produce a voltage control signal that controls the amount of current that flows through each of a plurality of transistors 1018," the sunk current value being programmed by "enabling and disabling, with the respective switch pairs 1050 and 1052, an appropriate number of the plurality of transistors 1018" (FIG. 10; col. 6, ll. ~31–43). A diode-connected reference transistor 1054 biased by reference current source 1056 and setting the gate control voltage of output transistors 1018, which conduct a proportional current into I/O node 1004, is a current mirror.
Regarding claim 12, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown further discloses that the current sink comprises an amplifier. Brown discloses a second programmable constant current sink in which "NMOS FET 1160 is coupled between the I/O node 1104 and power supply common, Vss," the current value being determined by the gate voltage, and in which "[a] programmable voltage reference 1164 may be used in combination with an amplifier 1162 to produce the control voltage at the gate of the FET 1160" (FIG. 11; col. 6, ll. ~44–53).
Claims 9 and 11 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Wyatt.
Regarding claim 9, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown discloses the current-mirror topology of FIG. 10 and the reference-plus-unit-block topology of FIG. 9 in connection with "a programmable constant current sink or source" (FIG. 9 title; col. 6, ll. ~17–30), but illustrates the current mirror in detail only for the sink (FIG. 10). Wyatt supplies the complementary source-side structure: a current source circuit 370 comprising a current mirror circuit 322 (current mirror transistors 309/311) and a current source device 314 coupled to output node 330, together with a complementary current sink circuit 360 comprising current mirror circuit 321 (transistors 301/303) and current sink device 306 coupled to that same output node 330 (Wyatt, FIG. 3; ¶¶ [0035]–[0036], [0038]–[0040]). Wyatt confirms that both sit on one node: the current source circuit 370 "is electrically connected to the same voltage output node 330 and the same biasing circuit 390 as the current sink circuit 360" (¶ [0064]; see also claim 19). In Wyatt each is independently enabled by its own digital switch responsive to its own control signal: switch 315 turns on "in response to a signal (e.g., an ‘Up’ signal 343)" to establish the source current path, and switch 307 turns on "in response to a signal (e.g., a ‘Down’ signal 341)" to establish the sink current path (¶¶ [0035]–[0036]). Each path is broken by its own complementary switch,316 on "Up_N" signal 344 and 308 on "Down_N" signal 342 (¶¶ [0035]–[0036]; claims 23, 25).
Regarding claim 11, Brown, as modified by Wu, discloses the device of claim 1 for the reasons discussed above. Brown discloses an amplifier in the constant current sink (amplifier 1162, FIG. 11; col. 6, ll. ~44–53). Wyatt discloses the counterpart in the current source circuit: a "two-stage feedback amplifier" 324 (transistors 312/313), and correspondingly amplifier 323 (transistors 304/305) in the sink circuit, each comprising "a common-gate feedback amplifier connected in series with a common-source amplifier" (FIG. 3; ¶¶ [0036], [0040]; see also claims 21, 30).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement the current source of the modified Brown device with the same current-mirror and amplifier topology Brown already uses for its current sink, as taught by Wyatt for a source coupled to a shared output node. Brown teaches the source and the sink as complementary implementations of one programmable constant current circuit and expressly describes FIG. 9 as "a programmable constant current sink or source" (col. 6, ll. ~17–30), so applying the sink’s mirror-and-amplifier topology to the source is the use of a known technique in a device the same reference already contemplates. MPEP § 2143(I)(C), (D). Wyatt supplies the further express motivation,the two-stage feedback amplifier "stabilize[s] the drain voltage of the current mirror circuit independent of variations in the output voltage at the output node" and thereby "increases the output resistance at the output node," which "allows for a wide operation voltage range and ensures good circuit performance under a very low power supply" and yields "highly matched" source and sink currents (¶¶ [0034], [0043]; see also ¶ [0072]). Constant current magnitude that does not vary with the load voltage at the node is exactly the property Brown seeks for LED drive (col. 1, ll. ~53–58) and that Applicant identifies as the problem to be solved at [0004] ("current mirrors and other current generating circuits do not provide reliable currents over long distances or driving heavy loads").
Notes: Wyatt is cited for the current source and current sink topology only. Wyatt’s phase-locked-loop and charge-pump application is not bodily incorporated into Brown’s I/O driver, and no such incorporation is required,the rejection relies on Wyatt’s circuit structure and its stated advantage, not on its use as a charge pump. In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012).
Claims 13 and 14 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu.
Regarding claim 13, Brown discloses a system comprising a microcontroller comprising an I/O circuit. Brown claims that "the integrated circuit digital device is a microcontroller" (Brown, claim 14, col. 7, ll. ~55–57; claim 20, col. 8, ll. ~40–42), having an I/O driver circuit driving an I/O connection (claim 1; col. 6, l. 62 – col. 7, l. 8). The I/O circuit comprises an output driver coupled to an I/O pad (the totem pole active output driver at I/O nodes 704/804, FIG. 7, col. 5, ll. ~29–33; FIG. 8, col. 5, ll. ~62–66); a current sink coupled to the I/O pad and enabled based on a current sink enable signal (programmable constant current sink 712, enabled via multiplexers 706/710 under the current limit enable signal, FIG. 7; col. 5, ll. ~28–37); and a current source coupled to the I/O pad and enabled based on a current source enable signal (programmable constant current source 812, enabled via multiplexers 806/810 under the current limit enable signal, FIG. 8; col. 5, l. ~62 – col. 6, l. ~3). Brown further discloses a load coupled to the I/O pad: LED 106 coupled to the I/O node (FIGS. 3–6; col. 4, ll. ~26–54; col. 4, l. ~59 – col. 5, l. ~20).
Brown further discloses that the microcontroller is to configure the I/O pad and to enable the current source and the current sink based on a predetermined condition. Brown discloses that the I/O node's configuration,"current limiting or non-current limiting, current limit value, etc.",is stored in configuration register 758/858 and applied to the multiplexers by the current limit enable signal (FIG. 7, col. 5, ll. ~33–43; FIG. 8, col. 6, ll. ~1–8), and that the register may be volatile RAM or nonvolatile Flash/PROM (col. 5, ll. ~39–43; col. 6, ll. ~5–8; Brown, claims 7–8, col. 7, ll. ~33–36),that is, the device is configured under program control according to the stored condition.
For the reasons and the rationale set out in earlier section, Brown does not disclose the current source and the current sink coupled to a single I/O pad in one embodiment, and it would have been obvious in view of Wu (FIG. 14; ¶¶ [0067]–[0070], [0072]; claims 1, 3, 4) to so arrange them.
Regarding claim 14, Brown, as modified by Wu, discloses the system of claim 13 for the reasons discussed above. Brown further discloses that the load comprises at least one light emitting diode (LED) and that the current source is to provide a current to drive the LED: Brown's FIG. 6 discloses that "a current will flow from the programmable constant current source 614, through the LED 106" (col. 5, ll. ~11–14), and Brown claims that "the output node is coupled to a light emitting diode (LED) and the programmable constant current circuit regulates current through the LED to the constant current value" (Brown, claim 13, col. 7, ll. ~50–54; claim 25, col. 9, ll. ~10–14). Brown states the purpose: maintaining a constant current "will maintain the light intensity of the LED at [a] constant level for all operating and manufacturing variables" (col. 1, ll. ~53–58),the same rationale Applicant recites at [0003].
Claim 15 is rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Cornelius.
Regarding claim 15, Brown, as modified by Wu, discloses the system of claim 13 for the reasons discussed above. Brown as modified does not expressly disclose that the load comprises a communication receiver, nor that the microcontroller enables the current source and the current sink in a predetermined sequence to transmit one or more data bits to that receiver.
Wu supplies the communication receiver. In Wu’s single-ended embodiment the output terminal T_S drives "the termination resistor R_S (or a load resistor)," which "may be located in a receiver … and coupled to a reference voltage VF" (Wu, ¶ [0061]; FIGS. 13–14). The load coupled to Wu’s output terminal is therefore a communication receiver.
Cornelius supplies the transmission of data bits by enabling the current circuits in a predetermined sequence. Cornelius discloses a transmitter configured to "receive a sequence of bits for transmission through the communication channel" (Cornelius, claim 7; ¶ [0010]). Cornelius discloses both a current source 416 and a current sink 422 coupled to the same communication channel 432 through switches 420/424 and 418/428 respectively, alongside a voltage-mode driver formed by pull-up network 402 and pull-down network 404,"[p]ull-up network 402 and pull-down network 404 form the voltage-mode driver",with control signal 430 closing switches 420 and 424 and leaving switches 418 and 428 open (FIG. 4; ¶¶ [0056]–[0057]).
Critically, Cornelius discloses enabling those current circuits in a sequence determined by the data bits to be transmitted. Cornelius discloses a decoder 608 that receives the incoming bit stream at input 600 and the history of previously transmitted bits held in flip-flops 602, 604, 606, and that "activates the current sources to optimize the shape and to boost the drive-level of the transmitted signal," the current sources "boost[ing] the signal strength … by injecting current through output 618, which is coupled to the communication channel" (FIG. 6; ¶¶ [0062]–[0064]). Cornelius specifies the predetermined condition governing the sequence: "the system determines if the given bit has the same state as the previously transmitted bit. If so, the system does not activate the current source. Otherwise, the system activates the current source to boost the signal of the transmitted bit" (FIG. 7, steps 702–708; ¶ [0067]), and further discloses using "a sequence of previously transmitted bits … to control the current source" (claims 4, 10, 16; ¶¶ [0013], [0068]). Cornelius also discloses that "each current source is activated separately from the other current sources as well as the voltage-mode driver" (claims 3, 9, 15; ¶¶ [0012], [0065]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to couple the I/O pad of the modified Brown microcontroller to a communication receiver and to enable its current source and current sink in a predetermined sequence, as taught by Cornelius, to transmit data bits. Cornelius states the motivation: current-mode drive "compensates for frequency dependant losses in the communication channel without sacrificing impedance matching and without substantially increasing power consumption," because "the current source does not consume any power when it is turned off," and it "makes the signal eye larger and thereby facilitates easier detection of the signal" (¶¶ [0010], [0054]; see also ¶ [0058]). A microcontroller pin already provisioned with a programmable constant current source and sink (Brown as modified by Wu) is the obvious host for this technique, and using a pad's existing current circuits for signalling as well as for LED drive expands the function of the pin without additional hardware,a predictable use of prior art elements according to their established functions. MPEP § 2143(I)(A), (D).
Claims 16–18 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Truong.
Regarding claim 16, Brown, as modified by Wu, discloses the system of claim 13 for the reasons discussed above. Brown discloses an input driver coupled to the I/O pad (receiver 760, FIG. 7; col. 5, ll. ~54–57), and Truong discloses the input driver providing an input signal to an internal circuit,input buffer 610 and level-shifter circuit 625 delivering the logic block voltage to logic fabric 670 (FIGS. 6–7; col. 14, l. ~58 – col. 15, l. ~3; col. 20, ll. ~28–40),for the reasons and with the rationale set out in previously.
Regarding claim 17, Brown, as modified by Wu and Truong, discloses the system of claim 13 for the reasons discussed above. Truong discloses a Schmitt trigger coupled to the I/O pad to provide hysteresis to a signal at the I/O pad (hysteresis circuits 705, 710, which "may be Schmitt trigger circuits," applying hysteresis voltages to the input path from I/O pad 605, FIG. 7; col. 16, ll. ~51–54; col. 17, ll. ~1–20), for the reasons and with the rationale set out previously.
Regarding claim 18, Brown, as modified by Wu and Truong, discloses the system of claim 13 for the reasons discussed above. Truong discloses a hysteresis register whose content determines the amount of hysteresis provided to the signal at the I/O pad, for the reasons and with the rationale set out earlier.
Claims 19 and 20 are rejected under 35 U.S.C. § 103 as unpatentable over Brown in view of Wu, further in view of Truong.
Regarding claim 19, Brown, as modified by Wu and Truong, discloses a method comprising disabling an output driver, an input driver and a Schmitt trigger that are part of an I/O pad, and enabling one of a current source and a current sink that are part of the I/O pad, wherein enabling the current source sources current at an external circuit and enabling the current sink sinks current at the external circuit.
Brown discloses the mode change as a method step: the multiplexers 706/710 and 806/810 are "controlled with a current limit enable signal for selecting between" the programmable constant current circuit and the standard drive circuit (FIG. 7, col. 5, ll. ~33–37; FIG. 8, col. 5, l. ~66 – col. 6, l. ~3),selecting the constant-current path necessarily deselects, i.e. disables, the totem pole active output driver path. Brown's I/O driver circuit is correspondingly "selectable to operate as a digital input/output driver or as a current limited output driver" (claim 1; col. 6, ll. ~65–67), which likewise disables the digital input function, including receiver 760 (col. 5, ll. ~54–57), when the current mode is selected. Truong supplies the Schmitt trigger that is disabled along with the input path (FIG. 7, hysteresis circuit 710 turned off when the enable voltage V_en_0 is at logic low, such that "no hysteresis voltage V_hysB_0 is applied"; col. 17, ll. ~33–44), for the reasons set out in earlier. Brown discloses that current is sourced or sunk at an external circuit,the LED 106 coupled to the I/O node (FIGS. 3–6; col. 4, ll. ~26–54; col. 4, l. ~59 – col. 5, l. ~20).
Enabling one of the source and the sink, from a pad provisioned with both, follows from the earlier combination: Wu expressly teaches that when one of the current source IS_0 and the current sink IS_0′ is coupled to the output terminal, "the other … is not coupled to the output terminal" (FIG. 14; ¶ [0068]; claim 3).
Regarding claim 20, Brown, as modified by Wu and Truong, discloses the method of claim 19 for the reasons discussed above. Brown discloses that enabling is effected by asserting an enable signal,the current limit enable signal controlling the multiplexers (FIG. 7, col. 5, ll. ~33–37; FIG. 8, col. 5, l. ~66 – col. 6, l. ~3),and Wu discloses separate control of the source path (switch S_C1) and the sink path (switch S_C3) (FIG. 14; ¶¶ [0069], [0072]), each "selectively coupled between the current source … and the first output terminal according to the first data input" and "between the current sink and the first output terminal according to the first data input," respectively, and switched in complementary fashion (Wu, claim 4),i.e. a current source enable signal and a current sink enable signal.
Conclusion
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/MONICA C KING/Primary Examiner, Art Unit 2844
9/19/2026
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