CTNF 19/247,477 CTNF 81114 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This office action is in response to application 19/247,477 filed on 6/24/2025 which is a continuation of application 18/402,572 filed on 1/2/2024, which is a continuation of application 16/828,843 filed on 3/24/2020. Claims 1-20 have been examined. Information Disclosure Statement The information disclosure statement (IDS) submitted on 9/9/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-2, 7, and 15 is/are rejected under 35 U.S.C. 102 (a)(1), (a)(2) as being anticipated by Sharon et al. (US 2017/0255403) . With respect to claim 1, Sharon teaches of a memory device, comprising: an array of stacked storage cells (fig. 1; paragraph 42; where the memory has a stacked die 3D configuration); a temperature sensor configured to measure a temperature of the memory device (fig. 1; paragraph 48; where the memory device includes a temperature sensor to measure the temperature and provide it to the controller); and a controller coupled to the array of stacked storage cells and the temperature sensor (fig. 1; paragraph 46-48; where the controller communicates with and thus is coupled to the memory and temperature sensor in the memory device), wherein the controller is configured to modulate a program step size voltage applied to the array of stacked storage cells based on a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device (fig. 1; paragraph 54, 110; where the difference between the read temperature and the write temperature determines an index into the table which selects the read voltage offset to apply to the read voltage). With respect to claim 15, Sharon teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1. Sharon also teaches of a method, comprising: at a memory device including an array of stacked storage cells (fig. 1; paragraph 42; where the memory has a stacked die 3D configuration): measuring a temperature of the memory device (fig. 1; paragraph 48; where the memory device includes a temperature sensor to measure the temperature and provide it to the controller); determining a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device (paragraph 54; where delta T1 is determined); and modulating a program step size voltage applied to the array of stacked storage cells based on the difference (fig. 1; paragraph 54, 110; where the difference between the read temperature and the write temperature determines an index into the table which selects the read voltage offset to apply to the read voltage). With respect to claim 2, Sharon teaches of wherein the controller is configured to increase the program step size voltage as the temperature of the memory device approaches a midpoint of the rated temperature range (paragraph 25-28; where an even slower and finer trim (“trim2”) may be used for programming when in an extreme “abnormal” temperature range. A slower and finer trim (“trim1”) may be used for programming when in a slightly “abnormal” temperature range, and a nominal programming trim (“trim0”) may be used for programming when in the “normal” temperature range. Thus, the trim gets larger as the temperature approaches the normal range). With respect to claim 7, Sharon teaches of wherein the controller is configured to decrease the program step size voltage as the temperature of the memory device moves away from a midpoint of the rated temperature range of the memory device (paragraph 25-28; where a nominal programming trim (“trim0”) may be used for programming when in the “normal” temperature range. A slower and finer trim (“trim1”) may be used for programming when in a slightly “abnormal” temperature range. An even slower and finer trim (“trim2”) may be used for programming when in an extreme “abnormal” temperature range. Thus, the trim gets smaller as the temperature gets further outside the normal range) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 8-9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and Ramalingam (US 2018/0088810) . With respect to claim 8, Sharon teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1. Sharon fails to explicitly teach of a plurality of processing cores; a system memory controller; a peripheral control hub; and a memory device coupled to the system memory controller or the peripheral control hub. However, Ramalingam teaches of a plurality of processing cores; a system memory controller; a peripheral control hub; and a memory device coupled to the system memory controller or the peripheral control hub (paragraph 12; where the SSD accepts sectors or blocks of information from a host (such as a platform complex composed of one or more central processing unit (CPU) cores, main memory controller, system memory and peripheral control hub) for writing into the device). Sharon and Ramalingam are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon and Ramalingam before the time of the effective filing of the claimed invention to incorporate the hosts of Ramalingam into Sharon. Their motivation would have been to use the SSD in more applications. With respect to claim 9, Sharon teaches of wherein the controller is configured to increase the program step size voltage as the temperature of the memory device approaches a midpoint of the rated temperature range (paragraph 25-28; where an even slower and finer trim (“trim2”) may be used for programming when in an extreme “abnormal” temperature range. A slower and finer trim (“trim1”) may be used for programming when in a slightly “abnormal” temperature range, and a nominal programming trim (“trim0”) may be used for programming when in the “normal” temperature range. Thus, the trim gets larger as the temperature approaches the normal range). With respect to claim 14, Sharon teaches of wherein the controller is configured to decrease the program step size voltage as the temperature of the memory device moves away from a midpoint of the rated temperature range of the memory device (paragraph 25-28; where a nominal programming trim (“trim0”) may be used for programming when in the “normal” temperature range. A slower and finer trim (“trim1”) may be used for programming when in a slightly “abnormal” temperature range. An even slower and finer trim (“trim2”) may be used for programming when in an extreme “abnormal” temperature range. Thus, the trim gets smaller as the temperature gets further outside the normal range) . 07-21-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and Reina (US 2020/0202938) . With respect to claim 3, Sharon fails to explicitly teach of wherein the increase of the program step size voltage is to happen in both warming and cooling directions of the memory device. However, Reina teaches of wherein the increase of the program step size voltage is to happen in both warming and cooling directions of the memory device (Reina, abstract, paragraph 10; the increase of the program step size voltage is to happen in both directions of the flash memory chip). Sharon and Reina are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon and Reina before the time of the effective filing of the claimed invention to incorporate the increasing and decreasing the voltage step size of Sharon as taught in Reina. Their motivation would have been to reduce errors and improve performance (Reina, paragraph 3) . 07-21-aia AIA Claim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and Ramalingam as applied to claim 9 above and in further view of Reina . With respect to claim 10, the combination of Sharon and Ramalingam fails to explicitly teach of wherein the increase of the program step size voltage is to happen in both warming and cooling directions of the memory device. However, Reina teaches of wherein the increase of the program step size voltage is to happen in both warming and cooling directions of the memory device (Reina, abstract, paragraph 10; the increase of the program step size voltage is to happen in both directions of the flash memory chip). Sharon, Ramalingam, and Reina are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon, Ramalingam, and Reina before the time of the effective filing of the claimed invention to incorporate the increasing and decreasing the voltage step size of the combination of Sharon and Ramalingam as taught in Reina. Their motivation would have been to reduce errors and improve performance (Reina, paragraph 3) . 07-21-aia AIA Claim (s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and Lee et al (US 8,238,185) . With respect to claim 4, Sharon fails to explicitly teach of wherein an increase in the program step size voltage corresponds to wider charge distribution in the array of stacked storage cells. However, Lee teaches of wherein an increase in the program step size voltage corresponds to wider charge distribution in the array of stacked storage cells (fig. 5, 8; Col. 7 Lines 32-59; where the application of progressively larger program voltages, as the temperature of the cell increases or decrease, resulting in wider charge distribution in the storage cells. For example, when the temperature is less than or equal to -45° C, the program voltage can be as high as seven volts (Vpgm = 0111), see Fig. 5. This results in a wider charge distribution than a Vpgm of zero when the temperature is between 45° C and 55° C). Sharon and Lee are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon and Lee before the time of the effective filing of the claimed invention to incorporate the charge distribution of Lee in Sharon as taught in Lee. Their motivation would have been to more efficiently use the memory. With respect to claim 5, Lee teaches of wherein the controller is configured to set the program step size voltage to a minimum program step size voltage at a maximum temperature of the rated temperature range of the memory device or a minimum temperature of the rated temperature range of the memory device (fig. 5; Col. 7 Lines 32-59; where the minimum of voltage of a step charge size of Vpgm equal to -4V (-0100) at 125° C.). The reasons for obviousness are the same as indicated above with respect to claim 4. With respect to claim 6, Lee teaches of wherein the minimum program step size voltage corresponds to narrowest charge distributions within the array of stacked storage cells compared with alternative program step size voltages corresponding to remainder temperatures of the rated temperature range, the remainder temperatures distinct from the maximum temperature and the minimum temperature (fig. 5; Col. 7 Lines 32-59; where the minimum charge step size of 4V at 125° C is the narrowest, when compared to a charge step size of 5V at 125° C). The reasons for obviousness are the same as indicated above with respect to claim 4 . 07-21-aia AIA Claim (s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon Ramalingam as applied to claim 9 and 8 above and in further view of Lee . With respect to claim 4, the combination of Sharon and Ramalingam fails to explicitly teach of wherein an increase in the program step size voltage corresponds to wider charge distribution in the array of stacked storage cells. However, Lee teaches of wherein an increase in the program step size voltage corresponds to wider charge distribution in the array of stacked storage cells (fig. 5, 8; Col. 7 Lines 32-59; where the application of progressively larger program voltages, as the temperature of the cell increases or decrease, resulting in wider charge distribution in the storage cells. For example, when the temperature is less than or equal to -45° C, the program voltage can be as high as seven volts (Vpgm = 0111), see Fig. 5. This results in a wider charge distribution than a Vpgm of zero when the temperature is between 45° C and 55° C). Sharon, Ramalingam, and Lee are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon, Ramalingam, and Lee before the time of the effective filing of the claimed invention to incorporate the charge distribution of Lee in the combination of Sharon and Ramalingam as taught in Lee. Their motivation would have been to more efficiently use the memory. With respect to claim 5, Lee teaches of wherein the controller is configured to set the program step size voltage to a minimum program step size voltage at a maximum temperature of the rated temperature range of the memory device or a minimum temperature of the rated temperature range of the memory device (fig. 5; Col. 7 Lines 32-59; where the minimum of voltage of a step charge size of Vpgm equal to -4V (-0100) at 125° C.). The reasons for obviousness are the same as indicated above with respect to claim 4. With respect to claim 6, Lee teaches of wherein the minimum program step size voltage corresponds to narrowest charge distributions within the array of stacked storage cells compared with alternative program step size voltages corresponding to remainder temperatures of the rated temperature range, the remainder temperatures distinct from the maximum temperature and the minimum temperature (fig. 5; Col. 7 Lines 32-59; where the minimum charge step size of 4V at 125° C is the narrowest, when compared to a charge step size of 5V at 125° C). The reasons for obviousness are the same as indicated above with respect to claim 4 . 07-21-aia AIA Claim (s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and Gopalakrishnan et al. (US 2021/0110865) . With respect to claim 16, Sharon fails to explicitly teach of wherein the difference indicates that the temperature of the memory device gradually gets closer to a midpoint of the rated temperature range of the memory device, and the method further comprises moving a page from lower density cells to higher density cells. However, Gopalakrishnan teaches of wherein the difference indicates that the temperature of the memory device gradually gets closer to a midpoint of the rated temperature range of the memory device, and the method further comprises moving a page from lower density cells to higher density cells (fig. 6; paragraph 87, 92-93, 96; where the folding (step 602) was done above the first temperature range and the integrity check is performed when the temperature falls into to the upper end of the second temperature range, i.e. the temperature has decreased towards the middle of the range, which is away from one of the minimum and maximum of the range. When the integrity check fails, the SLC data in the first group is folded into MLC data (step 612), moving the data from SLC to MLC (lower density cells to higher density cells). Sharon and Gopalakrishnan are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon and Gopalakrishnan before the time of the effective filing of the claimed invention to incorporate the store data to SLC and MLC memory based on the temperature in Sharon as taught in Gopalakrishnan. Their motivation would have been to increase the range of operating temperatures for the storage device (Gopalakrishnan, abstract) . 07-21-aia AIA Claim (s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharon Gopalakrishnan as applied to claim 16 above and in further view of Lee . With respect to claim 17, the combination of Sharon and Gopalakrishnan fails to explicitly teach of wherein the temperature of the memory device increases towards the midpoint of the rated temperature range. However, Lee teaches of wherein the temperature of the memory device increases towards the midpoint of the rated temperature range (fig. 5; Col. 5 Lines 11-16; column 7, line 17-column 8, line 19; where the midpoint of the rated temperature range of the flash memory chip between the extremes of -45° C and 125° C and the temperature change detected is increasing). Sharon, Gopalakrishnan, and Lee are analogous art because they are from the same field of endeavor, as they are directed to data storage. It would have been obvious to one of ordinary skill in the art having the teachings of Sharon, Gopalakrishnan, and Lee before the time of the effective filing of the claimed invention to incorporate the voltage changes of Lee in the combination of Sharon and Gopalakrishnan as taught in Lee. Their motivation would have been to more efficiently use the memory. With respect to claim 18, Lee teaches of wherein the temperature of the memory device decreases towards the midpoint of the rated temperature range (fig. 5; Col. 5 Lines 11-16; column 7, line 17-column 8, line 19; where the midpoint of the rated temperature range of the flash memory chip between the extremes of -45° C and 125° C and the temperature change detected is decreasing). The reasoning for obviousness is the same as indicated with respect to claim 17. With respect to claim 19, Lee teaches of wherein the program step size voltage increases over time (fig. 5; Col. 7 Lines 17-31; program step size voltage increases). The reasoning for obviousness is the same as indicated with respect to claim 17. With respect to claim 20, Lee teaches of wherein an increase in program step size voltage corresponds to a decrease of a program time for a block of the array of stacked storage cells (fig. 5, 7a; Col. 9 Lines 1-42; where an increase in the program step size permits memory cell programming with a single verify pass step. If the program is not successful, Col. 9 Lines 41-42 indicates adjusting the program step size and reverifying). The reasoning for obviousness is the same as indicated with respect to claim 17 . Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-7 and 9-14 of U.S. Patent No. 12,340,847 in view of Sharon . US 12,340,847 fails to explicitly claim (1) wherein the controller is configured to modulate a program step size voltage applied to the array of stacked storage cells based on a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device, and (2) determining a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device. However, Sharon teaches these in figure 1 and paragraphs 48, 54, and 110. US 12,340,847’s claims and Sharon are analogous art because they are from the same field of endeavor, as they are directed to temperature compensation of memory devices. It would have been obvious to one of ordinary skill in the art having the teachings of US 12,340,847’s claims and Sharon before the time of the effective filing of the claimed invention to incorporate the adjusting the read trim value based on the difference between the program and the read temperatures in US 12,340,847’s claims as taught in Sharon. Their motivation would have been to more efficiently use the memory (Sharon, paragraph 3-4) . 08-36 AIA Claim s 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-6, 8-13, and 15 of U.S. Patent No. 11,923,010 in view of Sharon . US 11,923,010 fails to explicitly claim (1) wherein the controller is configured to modulate a program step size voltage applied to the array of stacked storage cells based on a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device, and (2) determining a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device. However, Sharon teaches these in figure 1 and paragraphs 48, 54, and 110. US 11,923,010’s claims and Sharon are analogous art because they are from the same field of endeavor, as they are directed to temperature compensation of memory devices. It would have been obvious to one of ordinary skill in the art having the teachings of US 11,923,010’s claims and Sharon before the time of the effective filing of the claimed invention to incorporate the adjusting the read trim value based on the difference between the program and the read temperatures in US 11,923,010’s claims as taught in Sharon. Their motivation would have been to more efficiently use the memory (Sharon, paragraph 3-4). See the chart below for a mapping of the rejected claims. Application 19/247,477 US 12,340,847 US 11,923,010 Claim 1: A memory device, comprising: an array of stacked storage cells; Claim 1: An apparatus, comprising: a flash memory chip comprising i), ii), iii) and iv) below: ii) a first array of stacked storage cells; Claim 1: An apparatus, comprising: a flash memory chip comprising i), ii), iii) and iv) below: ii) a first array of stacked storage cells; a temperature sensor configured to measure a temperature of the memory device; and iii) a temperature sensing device; and, iii) a temperature sensing device; and, a controller coupled to the array of stacked storage cells and the temperature sensor, iv) a controller coupled to the chip interface, the first array of stacked storage cells and the temperature sensing device, iv) a controller coupled to the chip interface, the first array of stacked storage cells and the temperature sensing device, wherein the controller is configured to modulate a program step size voltage applied to the array of stacked storage cells based on a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device. wherein the controller is to modulate a program step size voltage applied to the first array of stacked storage cells based on a temperature of the flash memory chip as measured by the temperature sensing device, wherein the controller is to modulate a program step size voltage applied to the first array of stacked storage cells based on a temperature of the flash memory chip as measured by the temperature sensing device, Claim 2 Claim 2 Claim 2 Claim 3 Claim 3 Claim 3 Claim 4 Claim 4 Claim 4 Claim 5 Claim 5 Claim 5 Claim 6 Claim 6 Claim 6 Claim 7 Claim 1 Claim 1 Claim 8: A computing system, comprising: a plurality of processing cores; Claim 7: A computing system, comprising: a plurality of processing cores; Claim 8: A computing system, comprising: a plurality of processing cores; a system memory controller; a system memory controller coupled to the system memory; a system memory controller coupled to the system memory; a peripheral control hub; and a peripheral control hub; and, a peripheral control hub; and, a memory device coupled to the system memory controller or the peripheral control hub, a memory device coupled to the system memory controller or the peripheral control hub, a memory device coupled to the system memory controller or the peripheral control hub, the memory device further comprising: an array of stacked storage cells; the memory device comprising a flash memory chip, the flash memory chip comprising i), ii), iii), and iv) below: ii) a first array of stacked storage cells; the memory device comprising a flash memory chip, the flash memory chip comprising i), ii), iii), and iv) below: ii) a first array of stacked storage cells; a temperature sensor configured to measure a temperature of the memory device; and iii) a temperature sensing device; and, iii) a temperature sensing device; and, a controller coupled to the array of stacked storage cells and the temperature sensor, iv) a controller coupled to the chip interface, the first array of stacked storage cells and the temperature sensing device, iv) a controller coupled to the chip interface, the first array of stacked storage cells and the temperature sensing device, wherein the controller is configured to modulate a program step size voltage applied to the array of stacked storage cells based on a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device. wherein the controller is to modulate a program step size voltage applied to the first array of stacked storage cells based on a temperature of the flash memory chip as measured by the temperature sensing device, wherein the controller is to modulate a program step size voltage applied to the array of stacked storage cells based on a temperature of the flash memory chip as measured by the temperature sensing device, Claim 9 Claim 9 Claim 9 Claim 10 Claim 10 Claim 10 Claim 11 Claim 11 Claim 11 Claim 12 Claim 12 Claim 12 Claim 13 Claim 13 Claim 13 Claim 14 Claim 7 Claim 8 Claim 15: A method, comprising: at a memory device including an array of stacked storage cells: Claim 14: A method, comprising: performing the following on a flash memory chip: a first array of stacked storage cells of the flash memory chip Claim 15: A method, comprising: performing the following on a flash memory chip: a first array of stacked storage cells of the flash memory chip measuring a temperature of the memory device; measuring a temperature of the flash memory chip; measuring a temperature of the flash memory chip; determining a difference between a temperature of the memory device and a first temperature within a rated temperature range of the memory device; and modulating a program step size voltage applied to the array of stacked storage cells based on the difference. changing a program step size voltage of a first array of stacked storage cells of the flash memory chip because the temperature of the flash memory chip has changed including decreasing the program step size voltage as the temperature of the flash memory chip moves away from a midpoint temperature of a rated temperature range of the flash memory chip and toward a maximum temperature of the rated temperature range of the flash memory chip; and, changing a program step size voltage of a first array of stacked storage cells of the flash memory chip because the temperature of the flash memory chip has changed including decreasing the program step size voltage as the temperature of the flash memory chip moves away from a midpoint temperature of a rated temperature range of the flash memory chip and toward a maximum temperature of the rated temperature range of the flash memory chip; and , Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Madraswala et al. (US 2019/0043596) discloses measuring a first temperature and a second temperature of an MLC NAND memory array at different times. Determining the temperature difference between them, and performing operations based on the temperature difference. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael Krofcheck/Primary Examiner, Art Unit 2138 MICHAEL C. KROFCHECK Primary Examiner Art Unit 2138 Application/Control Number: 19/247,477 Page 2 Art Unit: 2138 Application/Control Number: 19/247,477 Page 4 Art Unit: 2138 Application/Control Number: 19/247,477 Page 5 Art Unit: 2138 Application/Control Number: 19/247,477 Page 6 Art Unit: 2138 Application/Control Number: 19/247,477 Page 7 Art Unit: 2138 Application/Control Number: 19/247,477 Page 8 Art Unit: 2138 Application/Control Number: 19/247,477 Page 9 Art Unit: 2138 Application/Control Number: 19/247,477 Page 10 Art Unit: 2138 Application/Control Number: 19/247,477 Page 11 Art Unit: 2138 Application/Control Number: 19/247,477 Page 12 Art Unit: 2138 Application/Control Number: 19/247,477 Page 13 Art Unit: 2138 Application/Control Number: 19/247,477 Page 14 Art Unit: 2138 Application/Control Number: 19/247,477 Page 15 Art Unit: 2138 Application/Control Number: 19/247,477 Page 16 Art Unit: 2138 Application/Control Number: 19/247,477 Page 17 Art Unit: 2138 Application/Control Number: 19/247,477 Page 18 Art Unit: 2138 Application/Control Number: 19/247,477 Page 19 Art Unit: 2138 Application/Control Number: 19/247,477 Page 20 Art Unit: 2138 Application/Control Number: 19/247,477 Page 21 Art Unit: 2138
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