DETAILED ACTION
This Office action has been issued in response to amendment filed July 20, 2026.
Claims 1-6, 8 and 9 have been amended. Claim 7 us canceled. Currently, claims 1-6, 8 and 9 are pending. Applicant’s arguments are carefully and respectfully considered and some are persuasive, while others are not. Accordingly, rejections have been removed where arguments were persuasive, but rejections have been maintained where arguments were not persuasive. Also, a new rejection based on the newly added amendments have been set forth. Accordingly, claims 1-6, 8 and 9 are rejected and this action has been made FINAL, as necessitated by amendment.
Response to Arguments
Applicant’s remarks and arguments directed to 35 USC 103 rejection, presented on 07/20/26 have been fully considered but they are moot in view of the new ground of rejection presented in this office action.
Objection
4. In claims 1, 8 and 9 recited the limitations of “enable an input of subsequent query”; The phrases “enable” may not able to perform operation or step as recited in the claim, As such, the phrases ‘enable’ is confusing and made the remaining limitations have no patentable weight.
Claim Rejections- 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 1-6, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Burger et al. (US 2016/0379115 A1), hereinafter Burger in view of Temam et al. (US 2019/0180170 A1), hereinafter Huang.
As for claim 1, Burger teaches a hardware accelerator device for deep learning inference, the hardware accelerator device comprising: an application-specific integrated circuit (ASIC) configured to: store query data input from a host processor, without using a buffer for temporary storage of the query data (see [0160]. e.g., input considerations, local host component, remote acceleration component compress the information, [0152], local acceleration component can query a service mapping component (SMC) in addition to, local host component, [0002], e.g., deep neural network, [0079], implemented in FPGA or on an ASIC, [0199], e.g., separate configurable domain can be use without affecting other domain, [0330], fourth memory is used to buffer output and temporaries data, [0332], e.g., verity of strategies for buffering and parallelization can be implemented);
perform a deep learning operation on the query data stored in the input storage, and to inference data, which is a result of the deep learning operation (see [0002], e.g., a deep neural network and system includes an acceleration component including an acceleration component die and a memory stack disposed in an integrated circuit package, perform forward propagation and backpropagation);
store the inference data; and determine whether previous query data is required in a deep learning operation during the deep learning operation on the previous query data (see [0003], e.g., processing deep neural network, [0082], e.g., receive a request for a service. In response and determination returns an address associated with the service, identify a particular acceleration component that hosts the requested service, [0120], data processing system integrates acceleration plane required by consumers and/or services, [0141], e.g., status of one or more acceleration components described whether previously registered as reserved” to non-reserved);
and generate a flag, indicating a state in which new query data can be input, when the previous query data is no longer required in the deep learning operation, wherein the deep learning operation is a propagation method in which initially input query data is not used from a specific time (see [0077], e.g., host defined packet associated with value of a status flag in each of the packet, [0082], e.g., receive a request for a service, in response identify a particular acceleration component that hosts the requested service, [0147], e.g., service mapping component need not perform multi-factor analysis, a host component make a request for a service that is associated with a single fixed location, defer to location determination component to map the service request to the address of the service, executing the service in different ways. Data store and acceleration component in allocating a request for a service to a particular address, [0002], e.g., forward and backward propagation is used, [0064], e.g., multiple entities is not intended to preclude the use of a single entity. Certain features as alternative ways of carrying out identified functions or implementing identified mechanisms, [0130], not be engaged in providing that service at the current time, [0138]);
wherein the ASIC is further configured to enable receive the new query data from the host processor that recognizes the flag during the deep learning operation on the previous query data,….the previous query data with the new query data, and store the new query data in advance (see [0074], e.g., host and accelerator communicate each other over network., host initiates and interacts with accelerator services, [0077], e.g., host defined packet associated with value of a status flag in each of the packet, [0096], e.g., host sends request, each acceleration component receives the message perform multi-component service in parallel with the other acceleration component, [0149], e.g., memory store instructions, or dedicated logic gate arrays implemented, for example, in an FPGA or on an ASIC, or other similar device),
and wherein the ASIC is further configured to enable an input of subsequent query data in advance at a first time point in that the initially input query is no longer required during the deep learning operation, after a first time period, which is required to receive the new query data has elapsed, and……time period, which is required to perform the deep learning operation on the previous query data and output inference data, elapses (see [0138], e.g., repeatedly made a request for the same service in a short period of time, [0200], dynamically acceleration component perform services on periodic basis and/or event-driven basis, [0201], put to sleep until it receives a notification (e.g., elapse), continues processing other data asynchronously. acceleration component transfers the data from the host logic's memory and places it in an acceleration component input buffer, [0254], e.g., an FPGA or on an ASIC, or other similar device, multiple requests and places them into queues. The request processing component adds each incoming request to an appropriate queues, and subsequently submits requests for processing, (e.g., these features described after instructing the accelerator to retrieve and process the data, such as retrieving/handling other data while prior processing is occurring, which is the same as the claim recited limitations “required to receive the new query data has elapsed, and……time period, which is required to perform the deep learning operation on the previous query data and output inference data, elapses”)), [0211], time-out period (e.g., elapsed), [0311], deep neural network using forward propagation of input activities to generate output activities/predictions, performing DNN calculations, Fig. 27, and associated text describes host logic putting data into an input buffer, the acceleration transferring it to an accelerator input buffer, and application logic later retrieving and processing data; Also, Fig. 27 disclosed host input buffer, transfer to accelerator input buffer, processing, accelerator output buffer, host output buffer. The host can continue processing other data asynchronously after starting the accelerator operation. Further teaches, [0332], DNN controller may employ various buffering and parallelization strategies and streams input activation into neural engine storage, which support the amended claim limitations).
Burger teaches the claimed invention including the limitations of previous query, time period ([0096], [0173]), but does not explicitly teach the limitations of replace the previous query; before a second time period. Although, Burger teaches transaction information associated with time stamps ([0198]). However, in the same field of endeavor Temam teaches the limitations of replace the previous query; before a second time period (see [009], e.g., data elements based on a number of iterations of one or more loops used to iterate through the sequence of data elements. [0023], the next machine learning computation can be moved into the buffers while the previous neural network computation is still being performed, [0058], buffer memory addresses one at a time. These features described overlap between receipt of the next data and execution of the previous neural-network computation, which can be the same such as before a second time period. Also, these features can be the same as before a second time period, which is required to perform the deep learning operation on the previous query data and output inference data, elapses).
Burger and Temam both references teach features that are directed to analogous art and they are from the same field of endeavor, such as data store or data sets, handling data buffer, integration circuit, sending and receiving requests via network, using accelerator component and deep learning.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Temam’s teaching to Burger system for double buffering and transferring data to multiple memories. Using multiple memories allows for quicker and more efficient transfer of data that exceeds the storage capacity of a single buffer. Also, reduction of addresses can be reduced. The reduction in instructions also results in higher performance as the processing unit processes fewer instructions to determine the memory addresses (see Temam, [0012]).
As for claim 8,
The limitations therein have substantially the same scope as claim 1 because claim 8 is a computing system claim for implementing those steps of claim 1. Therefore, claim 8 is rejected for at least the same reasons as claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Temam’s teaching to Burger system for double buffering and transferring data to multiple memories. Using multiple memories allows for quicker and more efficient transfer of data that exceeds the storage capacity of a single buffer. Also, reduction of addresses can be reduced. The reduction in instructions also results in higher performance as the processing unit processes fewer instructions to determine the memory addresses (see Temam, [0012]).
As for claim 9,
The limitations therein have substantially the same scope as claim 1 because claim 9 is a method claim for implementing those steps of claim 1. Therefore, claim 9 is rejected for at least the same reasons as claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Temam’s teaching to Burger system for double buffering and transferring data to multiple memories. Using multiple memories allows for quicker and more efficient transfer of data that exceeds the storage capacity of a single buffer. Also, reduction of addresses can be reduced. The reduction in instructions also results in higher performance as the processing unit processes fewer instructions to determine the memory addresses (see Temam, [0012]).
As to claim 2, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Temam teach:
wherein the buffer is neither included in the input storage nor located between the host processor and the accelerator device (see Burger, [0330]).
As to claim 3, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Temam teach:
wherein a process in which the ASIC receives the new query data is performed in parallel with a process in which the ASIC performs the deep learning operation on the previous query data (see Burger, [0060], [0254]).
As to claim 4, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Temam teach:
wherein the ASIC stores the flag indicating that input of the new query data after a second time point that the deep learning operation on the previous query data does not require the previous query data (see Burger, [0060], [0084]).
As to claim 5, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Temam teach:
wherein, when the ASIC outputs inference data, which is a result of the deep learning operation on the previous query data, the ASIC performs the deep learning operation on the new query data previously stored in the ASIC (see Burger, [0002], [0141], [0148]).
As to claim 6, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Temam teach:
further comprising a direct memory access (DMA) controller (see Burger, [0193]).
Prior Arts
8. US 2024/0143611 A1 teaches query by easily training data stored in an information database in response to a user's requested query through a deep learning approach, also enabling utilization of a pre-learned model and requiring less deep learning training and inference time ([0007]).
US 2026/0017261 A1 teaches deep learning applications; application-specific integrated circuits (ASICs) implementing custom logic for domain-specific tasks; application-specific instruction set processors (ASIPs) with instruction sets tailored for particular applications; field-programmable gate arrays (FPGAs) providing reconfigurable logic fabric that can be customized for specific processing tasks ([0269]).
WO2022/108029A1 teaches deep learning framework is connected to an information database. A request query of a user is learned via a deep learning method and data corresponding to the query can be inferred (abstract).
Also see, WO2022030670A1, US 20240177017, US 20240143611, US 12118010, WO2022030669A1, US 20220405100, US 11675592, US 20260017261, US 2018018935, US 20210279285, WO202264003A1, US 12314322, WO2023080276, these reference also read the claim recited limitation. These references are state of the art at the time of the claimed invention.
Conclusion
9. The examiner suggests, in response to this Office action, support being shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application (see 37 C.F.R. § 1.75(d)(1), 37 C.F.R. § 1.83(f)).
10. The prior art made of record on form PTO-892 and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action (see MPEP § 7.96). Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
11. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
12. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Daniel A Kuddus whose telephone number is (571) 270-1722. The examiner can normally be reached on Monday to Thursday 8.00 a.m.-5.30 p.m. The examiner can also be reached on alternate Fridays from 8.00 a.m. to 4.30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Boris Gorney can be reached on (571) 270-5626. The fax phone number for the organization where this application or processing is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from the either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL A KUDDUS/ Primary Examiner, Art Unit 2154
09/24/26
