DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Application filed December 26, 2022.
Claims 1-20 are pending.
Examiner has presented the rejections of all of the independent claims first (e.g. claims 1, 8 and 9) followed subsequently by the rejections of the respective dependent claims.
Acknowledgment is made of applicant' s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been received as described on 37 CFR 1.55.
No Information Disclosure Statement (IDS) filed by Applicant with this Application. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Specification
7. The Specification has been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any grammatical/spelling or any other errors of which applicant may become aware in the specification.
Remarks
8. In claims 1, 8 and 9 recited the limitations of “query data in advance, “storage is possible after a time”; The phrases “advance” and “possible” describing any types of data activities or possibilities. As such, the phrases “advance” and “possible” made the remaining limitations have no patentable weight.
9. Claim 5 recited the limitations of “it performs a deep learning operation”. The pronoun “it” is improper and should be replaced with the noun to which it refers.
10. Claims 1-8 are interpreted as including limitations which invoke 35 U.S.C. 112(f).
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 1 and 8 recited the limitations of “an accelerator configured to perform a deep learning operation”, “a status register configure to determine whether previous query data is required”, “a hardware accelerator device for deep learning inference configured to receive the query data”, has/have been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses/they use a generic placeholder “configure to” coupled with functional language, without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Therefore, the claim limitations as indicated as above are interpreted as invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
If applicant does not intend to have the claim limitation(s) treated under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112 , sixth paragraph, applicant may amend the claim(s) so that it/they will clearly not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, or present a sufficient showing that the claim recites/recite sufficient structure, material, or acts for performing the claimed function to preclude application of 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
11. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
12. Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claims 1 and 8, recites the following function limitations of an accelerator configured to perform a deep learning operation, a status register configure to determine whether previous query data is required, a hardware accelerator device for deep learning inference configured to receive the query data etc. These limitations invoke 35 USC § 112(f) , because they meet the 3-prong analysis set forth in MPEP 2181. However, the specification and drawings do not disclose sufficient corresponding structures, materials or acts for performing the claimed function. None of the component/function as recited in claim has links to corresponding hardware structure. As such, Applicant's failed to adequately describe sufficient structure for performing the function claimed or the specification does not disclose sufficient corresponding links and structures, materials or acts for performing the claimed function. As such, Applicant‘s failed to adequately describe sufficient structure for performing the function claimed. Note that a § 112(f) computer-implemented limitation that recites more than a non-specialized function must be supported in the specification by the computer and the algorithm that the computer uses to perform a claimed specialized function in order to definite the boundaries and notify the public of the claim scope.
Dependent claims are rejected for incorporating the same deficiencies of their respective base claims.
Claim Rejections – 35 USC § 101
35 USC 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture and composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title
13. Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter, e.g., claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more. The judicial exception is not integrated into a practical application.
Step 1. The device of claims 1-7, system of claim 8 and method of claim 9 are directed to one of the eligible categories of subject matter and therefore satisfy Step 1.
Step 2A. Prong one of the 2019 PEG:
1. In accordance with Step 2A, prong one, the limitations are directed to additional elements include hardware, processor, memory and computing system.
2. The limitations are recited in claims 1, 8 and 9 are request a deep learning operation on query data; receive the query data from the host processor, to perform the deep learning operation on the query data, and to output inference data, which is a result of the deep learning operation; and memory configured to store the query data and the inference data, wherein the hardware accelerator device for deep learning inference comprises: input storage configured to store the query data input from the host processor; an accelerator configured to perform the deep learning operation on the query data stored in the input storage, and to output the inference data, which is the result of the deep learning operation; output storage configured to store the inference data; and wherein the input storage receives the new query data from the host processor that recognizes the flag during the deep learning operation on the previous query data, replaces the previous query data with the new query data, and stores the new query data in advance etc., is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of the generic computer components. That is, other than reciting hardware, processor, memory and computing system, nothing in the claim element precludes the step from practically being performed in the mind. The steps can be done my nominally, insignificantly or user can perform each of the tasks merely manually and can consider as a data gathering performance. Further, the limitations can describe data buffering with acceleration, data-flow streaming/cycle architecture, compute overlapping, data movement, signal readiness and load/preload data with triggering execution- these limitations are routine and convention such as continuous data ingestion with acceleration. Further, generate a flag is not telling how it is generating. Furthermore, the deep learning as recited in the claim does not improve technological environment. Also, is not improvement of technology or improvement computer itself. Thus, the limitations are directed to abstract mental process and can be manually performed by human. If a claim limitations, under its broadest reasonable interpretation, covers performance of the limitations in the mind but for the recitation of generic computer components, then it falls with mental process grouping of abstract ideas.
With respect to Step 2A, Prong two of the 2019 PEG: the judicial exception is not integrated into a practical application. The hardware, processor, memory and computing system in both steps is recited at a high-level of generality or insignificant extra solution activity such that it amounts no more than mere instructions to apply the exception using a generic computer component, Accordingly, these additional element (hardware, processor, memory and computing system) does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B.
Claims 1, 8 and 9 recited additional limitations, such that a status register configured to determine whether previous query data is required in a deep learning operation during the deep learning operation on the previous query data, and to generate a flag, indicating a state in which new query data can be input, when the previous query data is no longer required in the deep learning operation. These limitations are a context which encompasses continuous data processing, set a signal/trigger associated with the data processing status and management or controlling the data processing operations. Further, the claim does not recite when the previous query data is no longer need and how the no longer needed. The additional elements are broadly applied to the abstract idea at a high level of generality, they are directed to extra solution activity or they operate in a well-understood, routine, and conventional manner (MPEP § 2106.05(f); MPEP § 2106.05(d)(II)). Storing and retrieving information in memory (e.g. Versata Dev. Group, Inc. v. SAP Am., Inc..). Courts have held computer-implemented processes not to be significantly more than an abstract idea (and thus ineligible) where the claim as a whole amount to nothing more than generic computer function merely used to implement an abstract idea, such as an idea that could be done by human thinking. Using generic computing components (e.g., system, hardware processor, non-transitory processor-readable storage medium) does not amount to significantly more than the abstract and is not enough to transform an abstract idea to a particular technological environment, which is not enough to render the claims patent-eligible. Further, the subject matter can also interpret as well-understood, routine and conventional functions (e.g., electronically scanning or extracting data from a physical document/object, Content Extraction and Transmission, LLC v. Wells Fargo Bank….). There is no indication that the combination of elements integrates the abstract idea into a practical application. They are merely collective functions provide conventional computer implementation. Therefore, when viewed as a whole, these additional claim elements do not provide meaningful limitations to transform the abstract idea into a practical application of the abstract idea. Accordingly, the claims are directed to an abstract idea.
Dependent claim 2 recited the limitations of temporary store the query data is neither include in the input storage nor located between the host processor and the accelerator device, which are merely describing storage functionality. The limitations are routine and conventional. Dependent claims 3 recited the limitations of accelerator performs the deep learning operation on the previous data, which not telling how acceleration performs. The limitations are mental process. Dependent claims 4 recited the limitations of stores the flag indicating the input of the new query data to the input storage is possible after a times when the deep learning on the previous data does not require the previous query data. The limitations store the flag and other limitations are merely describing storing data. The limitations are routine and conventional. Dependent claim 5 recited the limitations of output interference data, perform a deep learning operation on the new query data previously stored in the input storage. The limitations are describing output operation and using deep learning. The limitations are mental process. Dependent claim 6 recited the limitations of a direct memory access (DMA), which is describing a hardware component. The limitations are routine and conventional. Dependent claim 7 recited the limitations of propagation method in which initially input query data is not used from a specific time. The limitations are describing distributing/processing data maintaining the time. The limitations are mental process. The claim recited limitations are do not provide meaningful limitations to transform the abstract idea into a practical application of the abstract idea. As such, the claims are directed to an abstract idea.
Claim Rejections- 35 USC § 103
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
16. Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Burger et al. (US 2016/0379115 A1), hereinafter Burger in view of Lie et al. (US 2020/0005142 A1), hereinafter Lie.
As for claim 1, Burger teaches a hardware accelerator device for deep learning inference, the hardware accelerator device comprising: input storage configured to store query data input from a host processor (see [0160]. e.g., input considerations, local host component, remote acceleration component compress the information, [0152], local acceleration component can query a service mapping component (SMC) in addition to, local host component, [0002], e.g., deep neural network);
an accelerator configured to perform a deep learning operation on the query data stored in the input storage, and to output inference data, which is a result of the deep learning operation (see [0002], e.g., a deep neural network and system includes an acceleration component including an acceleration component die and a memory stack disposed in an integrated circuit package, perform forward propagation and backpropagation);
output storage configured to store the inference data; and a status register configured to determine whether previous query data is required in a deep learning operation during the deep learning operation on the previous query data (see [0003], e.g., processing deep neural network, [0082], e.g., receive a request for a service. In response and determination returns an address associated with the service, identify a particular acceleration component that hosts the requested service, [0120], data processing system integrates acceleration plane required by consumers and/or services, [0141], e.g., status of one or more acceleration components described whether previously registered as reserved” to non-reserved);
and to generate a flag, indicating a state in which new query data can be input, when the previous query data is no longer required in the deep learning operation (see [0077], e.g., host defined packet associated with value of a status flag in each of the packet, [0082], e.g., receive a request for a service, in response identify a particular acceleration component that hosts the requested service, [0147], e.g., service mapping component need not perform multi-factor analysis, a host component make a request for a service that is associated with a single fixed location, defer to location determination component to map the service request to the address of the service, executing the service in different ways. Data store and acceleration component in allocating a request for a service to a particular address);
wherein the input storage receives the new query data from the host processor that recognizes the flag during the deep learning operation on the previous query data,….the previous query data with the new query data, and stores the new query data in advance (see [0074], e.g., host and accelerator communicate each other over network., host initiates and interacts with accelerator services, [0077], e.g., host defined packet associated with value of a status flag in each of the packet, [0096], e.g., host sends request, each acceleration component receives the message perform multi-component service in parallel with the other acceleration component).
Burger teaches the claimed invention including the limitations of previous query ([0096]), but does not explicitly teach the limitations of replaces the previous query. However, in the same field of endeavor Lie teaches the limitations of replaces the previous query (see [0062], e.g., communication via wavelets, continuous propagation gradient descent techniques usable to train weights of a neural network modeled by the processing elements).
Burger and Lie both references teach features that are directed to analogous art and they are from the same field of endeavor, such as data store or data sets, sending and receiving requests via network, using accelerator component and deep learning.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lie’s teaching to Burger system to data structure descriptors for accelerated deep learning. Thus provide an improvements in one or more of accuracy, performance and energy efficiency. A data structure with deep learning enable use computational resources in multiple processing elements, load balancing across the processing elements while maintaining locality of incoming activations for the processing elements (see Lie, [0065]).
As for claim 8,
The limitations therein have substantially the same scope as claim 1 because claim 8 is a computing system claim for implementing those steps of claim 1. Therefore, claim 8 is rejected for at least the same reasons as claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lie’s teaching to Burger system to data structure descriptors for accelerated deep learning. Thus provide an improvements in one or more of accuracy, performance and energy efficiency. A data structure with deep learning enable use computational resources in multiple processing elements, load balancing across the processing elements while maintaining locality of incoming activations for the processing elements (see Lie, [0065]).
As for claim 9,
The limitations therein have substantially the same scope as claim 1 because claim 9 is a method claim for implementing those steps of claim 1. Therefore, claim 9 is rejected for at least the same reasons as claim 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lie’s teaching to Burger system to data structure descriptors for accelerated deep learning. Thus provide an improvements in one or more of accuracy, performance and energy efficiency. A data structure with deep learning enable use computational resources in multiple processing elements, load balancing across the processing elements while maintaining locality of incoming activations for the processing elements (see Lie, [0065]).
As to claim 2, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
wherein a buffer configured to temporarily store the query data is neither included in the input storage nor located between the host processor and the accelerator device (see Burger, [0330]).
As to claim 3, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
wherein a process in which the input storage receives the new query data is performed in parallel with a process in which the accelerator performs the deep learning operation on the previous query data (see Burger, [0060], [0254]).
As to claim 4, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
wherein the status register stores the flag indicating that input of the new query data to the input storage is possible after a time when the deep learning operation on the previous query data does not require the previous query data (see Burger, [0060], [0084]).
As to claim 5, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
wherein, when the accelerator outputs inference data, which is a result of the deep learning operation on the previous query data, it performs a deep learning operation on the new query data previously stored in the input storage (see Burger, [0002], [0141], [0148]).
As to claim 6, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
further comprising a direct memory access (DMA) controller connected to the input storage or the output storage (see Burger, [0193]).
As to claim 7, this claim is rejected based on the same reason as above to reject the claim above and are similarly rejected including the following:
Burger and Lie teach:
wherein the deep learning operation is a propagation method in which initially input query data is not used from a specific time (see Burger, [0095], [0138]).
Prior Arts
17. US 2024/0143611 A1 teaches query by easily training data stored in an information database in response to a user's requested query through a deep learning approach, also enabling utilization of a pre-learned model and requiring less deep learning training and inference time ([0007]).
US 2026/0017261 A1 teaches deep learning applications; application-specific integrated circuits (ASICs) implementing custom logic for domain-specific tasks; application-specific instruction set processors (ASIPs) with instruction sets tailored for particular applications; field-programmable gate arrays (FPGAs) providing reconfigurable logic fabric that can be customized for specific processing tasks ([0269]).
WO2022/108029A1 teaches deep learning framework is connected to an information database. A request query of a user is learned via a deep learning method and data corresponding to the query can be inferred (abstract).
Also see, WO2022030670A1, US 20240177017, US 20240143611, US 12118010, WO2022030669A1, US 20220405100, US 11675592, US 20260017261, US 2018018935, US 20210279285, WO202264003A1, US 12314322, WO2023080276, these reference also read the claim recited limitation. These references are state of the art at the time of the claimed invention.
Conclusion
18. The examiner suggests, in response to this Office action, support being shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application because:
a. 37 C.F.R. § 1.75(d)(1) requires antecedent basis in the Specification or original disclosure for any new language, including terms and phrases, added to the claims;
and because:
b. 37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety
as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the examiner.
19. The prior art made of record on form PTO-892 and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action (see MPEP § 7.96).
Contact Information
20. Any inquiry concerning this communication or earlier communication from the examiner should be directed to Daniel A Kuddus whose telephone number is (571) 270-1722. The examiner can normally be reached on Monday to Thursday 8.00 a.m.-5.30 p.m. The examiner can also be reached on alternate Fridays from 8.00 a.m. to 4.30 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Boris Gorney can be reached on (571) 270-5626. The fax phone number for the organization where this application or processing is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from the either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL A KUDDUS/ Primary Examiner, Art Unit 2154
4/30/26
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