Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application covers same scope as the reference patent. The table below shows a limitation by limitation comparison.
Instant application Claim 2
Parent patent Claim 1
A memory system, comprising:
An apparatus, comprising:
one or more memory devices; and
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
a controller coupled with the one or more memory devices and configured to cause the apparatus to:
transfer data from a set of source data blocks of the memory system to a set of destination data blocks of the memory system according to a first order;
determine to transfer data from a set of source data blocks of the apparatus to a set of destination data blocks of the apparatus;
Instant application Claim 2
Parent patent Claim 12
receive a command to access the set of destination data blocks;
sequentially read the data from the set of destination data blocks
sequentially read the data from the set of destination data blocks according to a second order in response to the command and in accordance with transferring the data from the set of source data blocks to the set of destination data blocks according to the first order; and
sequentially read the data from the set of destination data blocks according to the second order based at least in part on transferring the data according to the first order and transferring the first portion of the data; and
sequentially transmit, via one or more channels coupled with the memory system and a host system, the data according to the second order in response to reading the data.
transmit the sequentially read data to the host system coupled with the apparatus.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application covers same scope as the reference patent. The table below shows a limitation by limitation comparison.
Instant application Claim 2
Parent patent Claim 12
transfer, after a first source data block of the set of source data blocks is accessed and after transferring respective portions of the data from the set of source data blocks to the set of destination data blocks, a first portion of the data to a destination data block of the set of destination data blocks according to the second order.
transfer, after the first source data block is accessed, the first portion of the data to a destination data block of the set of destination data blocks based at least in part on the second order;
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application covers same scope as the reference patent. The table below shows a limitation by limitation comparison.
Instant application Claim 2
Parent patent Claim 12
access one or more source data blocks of the set of source data blocks concurrent with the transfer of the data from the set of source data blocks to the set of destination data blocks, wherein the concurrent access and transfer is according to the first order.
the first order excluding a first portion of the data from the first source data block based at least in part on the accessing the first source data block being concurrent with the transfer of the data;
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application covers same scope as the reference patent. The table below shows a limitation by limitation comparison.
Instant application Claim 7
Parent patent Claim 13
wherein each source data block of the set of source data blocks and each destination data block of the set of destination data blocks is associated with a virtual block of a respective memory die of the memory system.
the set of source data blocks comprises a source virtual block associated with a set of memory dies of the apparatus; and the set of destination data blocks comprises a destination virtual block associated with the set of memory dies of the apparatus.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 merely recites the result of the ordering process already recited in claim 1 of the parent. Parent claim 1 additionally recites generating the first order based upon the sequential-read order and concurrent-access condition. Therefore, continuation claim 8 is at most an obvious variant of parent claim 1.
The table below shows a limitation by limitation comparison.
Instant application Claim 8
Parent patent Claim 1
A memory system comprising one or more memory devices and processing circuitry
An apparatus comprising one or more memory devices and a controller
determine to transfer data from a set of source data blocks to a set of destination data blocks
determine to transfer data from a set of source data blocks to a set of destination data blocks
transfer respective portions of the data from the source data blocks to the destination data blocks according to a first order
transfer respective portions of the data from the source data blocks to the destination data blocks based on a first order
wherein the first order is associated with a second order associated with a sequential read of the data from the destination data blocks
generate the first order based at least in part on a second order associated with a sequential read of the data from the destination data blocks
wherein the first order excludes a first portion of the data
the first order excludes a first portion of the data
wherein the exclusion is in accordance with a host system accessing the first source data block concurrent with the transfer
the first order excludes the first portion based at least in part on accessing the first source data block being concurrent with transfer of the data
Claims 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 of U.S. Patent No. 12,346,587. The limitations are essentially identical in both claims.
Claims 11-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10 of U.S. Patent No. 12,346,587. Although the claims at issue are not identical, they are not patentably distinct from each other because the continuation merely breaks the parent claim into two dependent claims.
Claims 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 4 of U.S. Patent No. 12,346,587. The limitations are essentially identical in both claims.
Claims 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 of U.S. Patent No. 12,346,587. The limitations are essentially identical in both claims.
Claims 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13 of U.S. Patent No. 12,346,587. The limitations are essentially identical in both claims.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 12 of U.S. Patent No. 12,346,587 under the same rationale of rejection of claim 2.
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 12 of U.S. Patent No. 12,346,587 under the same rationale of rejection of claim 5.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 12,346,587 under the same rationale of rejection of claim 6.
Claim 21 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 13 of U.S. Patent No. 12,346,587 under the same rationale of rejection of claim 7.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1 and 16 the prior art of record, including Sokolov et al. (US 2017/0220264 A1), Fujiwara et al. (US 2024/0094943 A1), and Li et al. (US 2024/0168683 A1), fails to teach or suggest the claimed feature of sequentially reading data from a set of destination data blocks according to a second order in response to a command and after transferring data from a set of source data blocks to the set of destination data blocks according to a first order, and subsequently sequentially transmitting the data to a host according to the second order upon reading the data.
Sokolov generally discloses data relocation and management operations within a memory system, but does not disclose reading relocated data from destination blocks according to an order that is distinct from, or otherwise coordinated with, the order used during the transfer operation. Further, Sokolov does not disclose sequential host transmission based upon such a destination-block read order.
Fujiwara describes memory data movement and block management techniques but does not teach performing a transfer operation according to a first order and thereafter reading the transferred data from destination blocks according to a second order that governs subsequent host delivery. Fujiwara lacks any disclosure of preserving or reconstructing a particular transmission sequence through a post-transfer destination-block read process.
Li discloses memory management and data transfer operations but similarly fails to teach sequentially reading data from destination blocks according to a second order in response to a command and then sequentially transmitting the data to a host according to that same second order. Li does not disclose coordinating destination-block read sequencing with host transmission sequencing following an earlier transfer operation performed according to a first order.
Accordingly, the cited references, whether considered individually or in combination, do not teach or suggest the claimed ordered relationship among (i) transferring data from source blocks according to a first order, (ii) subsequently reading the data from destination blocks according to a second order, and (iii) sequentially transmitting the data to a host according to the second order. The claimed sequence-aware post-transfer read and transmission mechanism provides a specific manner of reconstructing and delivering data after relocation that is not disclosed or suggested by the prior art of record. Therefore, claims 1 and 16 are allowable upon overcoming the double patenting rejection.
Regarding claim 8 the prior art of record, including Sokolov et al. (US 2017/0220264 A1), Fujiwara et al. (US 2024/0094943 A1), and Li et al. (US 2024/0168683 A1), fails to teach or suggest the claimed operation of transferring respective portions of data from a set of source data blocks to a set of destination data blocks according to a first order while excluding a first portion of the data from a first source data block based on concurrent host access to the first source data block, wherein the first order is associated with a second order used for a subsequent sequential read of the data from the destination data blocks.
Sokolov generally discloses relocation and movement of data among memory blocks, but does not disclose dynamically excluding a particular portion of data from a transfer operation in response to a host system concurrently accessing the source block containing that portion. Nor does Sokolov disclose maintaining an ordered transfer sequence that is expressly associated with a separate sequential read order for later retrieval of the relocated data.
Fujiwara describes memory-management operations involving movement of data between blocks, but does not teach selectively omitting a portion of data from migration due to concurrent host access during the transfer process. Further, Fujiwara does not disclose a first transfer order that is associated with a second order governing a subsequent sequential read of the transferred data.
Li similarly fails to disclose excluding a first portion of data from a source block during relocation based upon contemporaneous host access to that source block. Additionally, Li does not teach coordinating a transfer order with a subsequent read order such that the relocated data can later be sequentially read according to the associated second order.
Accordingly, the cited references, either alone or in combination, do not teach or suggest the claimed combination of (i) selectively excluding a portion of data from a transfer operation in response to concurrent host access to the corresponding source block, and (ii) performing the transfer according to a first order that is associated with a second order used for subsequent sequential reading of the transferred data. The claimed mechanism preserves host accessibility while maintaining an ordered relocation framework for later retrieval, which is not disclosed or suggested by the prior art of record. Therefore, claim 8 is allowable upon overcoming the double patenting rejection.
Claims 3, 10 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 and 18 are objected as being dependent on already objected claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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