DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Disposition of the Claims
2. The instant application was effectively filed on May 17, 2024, wherein claims 8-20 are cancelled and 1-7 and 21-33 are currently pending.
Claim Objections
Claim 30 is objected to because of the following informalities:
Claim recites “….. a first sampling capacitor selectively coupled between: 1) the first inverting terminal and the first non-inverting terminal of the first differential integrator; and 2) a set of voltage input terminals; and a second sampling capacitor selectively coupled between: 1) an inverting output terminal and a non-inverting output terminal of the first differential integrator; and 2) the second inverting terminal and the second non-inverting terminal of the second differential integrator” for clarity proposes claim should be amended as follows:
“….. a first sampling capacitor selectively coupled between: i) the first inverting terminal and the first non-inverting terminal of the first differential integrator; and ii) a set of voltage input terminals; and a second sampling capacitor selectively coupled between: i) an inverting output terminal and a non-inverting output terminal of the first differential integrator; and ii) the second inverting terminal and the second non-inverting terminal of the second differential integrator
Appropriate correction is required.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim Comparison Table #1
Claims of Present Application# 19,248,810
Claims of Patent No. # 12,375,098 B1
1. (Currently Amended) An integrated circuit comprising: a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor, wherein the sigma-delta modulator comprises: a first single-ended integrator; a second single-ended integrator selectively coupled to an output of the first single-ended integrator; a latch coupled to an output of the second single-ended integrator and driven by a frequency modulation signal; a balancing circuit selectively coupled to a first input of the first single-ended integrator and to a second input of the second single-ended integrator; and logic coupled to the balancing circuit, the logic to cause, based on the frequency modulation signal and an output value of the latch an output of the second single-ended integrator, the balancing circuit to one of: apply a positive balancing current to the first input and a negative balancing current to the second input; or apply a positive balancing current to the second input and a negative balancing current to the first input.
2. (Original) The integrated circuit of claim 1, further comprising a current-to-current converter coupled to the receive electrode, wherein the first single-ended integrator is coupled to the current-to-current converter.
3. (Currently Amended) The integrated circuit of claim 1, further comprising; a latch coupled to an output of the second single-ended integrator and driven by a frequency modulation signal, wherein the logic is driven by the frequency modulation signal and an output value of the latch; and a comparator coupled between the output of the second single-ended integrator and an input to the latch.
4. (Original) The integrated circuit of claim 1, wherein each of the first and second single- ended integrators comprises: an operational amplifier with a non-inverting terminal coupled to a bias voltage; and an integrating capacitor coupled between an output and an inverting terminal of the operational amplifier.
5. (Original) The integrated circuit of claim 1, further comprising: a single-ended sampling capacitor; and a set of switches coupled between the first and second single-ended integrators and the single-ended sampling capacitor, wherein a sample signal directs the set of switches to charge the single-ended sampling capacitor from the first single-ended integrator and discharge the single-ended sampling capacitor through the second single-ended integrator.
6. (Currently Amended) The integrated circuit of claim [[1]]3, wherein the balancing circuit comprises: a balancing capacitor; a first set of switches to selectively couple a first side of the balancing capacitor between a reference voltage and ground; and a second set of switches to selectively couple a second side of the balancing capacitor between the first input and the second input.
7. (Original) The integrated circuit of claim 6, wherein the logic comprises an XOR gate having inputs comprising the frequency modulation signal and the output value of the latch, wherein an output of the XOR gate is coupled to the second set of switches.
1. An integrated circuit comprising: a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor, wherein the sigma-delta modulator comprises: a first single-ended integrator; a second single-ended integrator selectively coupled to an output of the first single-ended integrator; a latch coupled to an output of the second single-ended integrator and driven by a frequency modulation signal; a balancing circuit selectively coupled to a first input of the first single-ended integrator and to a second input of the second single-ended integrator; and logic coupled to the balancing circuit, the logic to cause, based on the frequency modulation signal and an output value of the latch, the balancing circuit to one of: apply a positive balancing current to the first input and a negative balancing current to the second input; or apply a positive balancing current to the second input and a negative balancing current to the first input.
2. The integrated circuit of claim 1, further comprising a current-to-current converter coupled to the receive electrode, wherein the first single-ended integrator is coupled to the current-to-current converter.
3. The integrated circuit of claim 1, further comprising a comparator coupled between the output of the second single-ended integrator and an input to the latch.
4. The integrated circuit of claim 1, wherein each of the first and second single-ended integrators comprises: an operational amplifier with a non-inverting terminal coupled to a bias voltage; and an integrating capacitor coupled between an output and an inverting terminal of the operational amplifier.
5. The integrated circuit of claim 1, further comprising: a single-ended sampling capacitor; and a set of switches coupled between the first and second single-ended integrators and the single-ended sampling capacitor, wherein a sample signal directs the set of switches to charge the single-ended sampling capacitor from the first single-ended integrator and discharge the single-ended sampling capacitor through the second single-ended integrator.
6. The integrated circuit of claim 1, wherein the balancing circuit comprises: a balancing capacitor; a first set of switches to selectively couple a first side of the balancing capacitor between a reference voltage and ground; and a second set of switches to selectively couple a second side of the balancing capacitor between the first input and the second input.
7. The integrated circuit of claim 6, wherein the logic comprises an XOR gate having inputs comprising the frequency modulation signal and the output value of the latch, wherein an output of the XOR gate is coupled to the second set of switches.
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-7 as shown in table#1 above of present application No. 19,248,810 is similar in scope to claims 1-7 of Patent No. 12,375,098 B1, as shown in the claim comparison table #1 above.
Allowable Subject Matter
Claims 21-33 are allowed.
The following is examiner's statement of reason for allowance.
Ogirko (US PG-PUB 20210226626 A1) teaches Sigma-delta modulator 402 also includes a first integrator capacitor 412 coupled to a first node 405 and a second integrator 414 capacitor coupled to a second node 407. Sigma-delta modulator 402 also includes a first current source 416, a second current source 418, a comparator 420, and a flip-flop 422 coupled to an output of comparator 420 and coupled to an input of counter 404. An output of the flip-flop 422 is part of a balancing feedback loop 424 coupled to the switching circuitry. the sigma-delta modulator includes a balancing feedback loop coupled to the switching circuitry and the switching circuitry includes a first switch coupled to provide the incoming signal to the first integrator or the second integrator, a second switch coupled to provide the first output signal to the comparator or the second output signal to the comparator, and a third switch coupled to provide a balancing feedback signal from the balancing feedback loop to the incoming signal provided to the first integrator or the incoming signal provided to the second integrator. In this embodiment, the first switch, the second switch, and the third switch are configured to operate synchronously.
Maharyta et. al (US PG-PUB 20220196437 A1) teaches a sigma-delta modulator 1056 can include modulator capacitance Cmod, switch SW9, comparator 108, and flip-flop FF 110. Said sigma-delta modulator 105A can generate a bitstream 112A from Vmod. i.e. a high Bitstream 112B can be received by feedback logic 114. In response, feedback logic 114 can generate pulse Ph0_mod_fb followed by pulse Ph1_mod_fb. Pulse Ph0_mod_fb can result in a balance current Ibal by switched capacitor operation of Cref. As shown, Ibal can be a sink current from modulator node 106, which can reduce Vmod. Subsequently, Cref can be charged by operation of switches SW5 and SW6. Provided Bitstream 112B remains high, current Ibal can continue to be generated. A balance current can be modulated by the voltage at the modulator node (e.g., via a feedback path). In some embodiments, a balance current can be generated by a switch capacitor circuit. Such a switch capacitor circuit can include a programmable capacitance.
Maharyta et al. (US PG-PUB 20220360275 A1) teaches differential sigma-delta modulator operation can detect a voltage difference and compensates for this difference using a balancing current. A balance current generator 312 can generate a balance current Ibal. A balance current Ibal can flow in a direction opposite to that of sensor current (Is) with respect to input (IN1). In some embodiments, a balance current generator 312 can be modulated according to one or more balance switch control signals SWIbal. A digital section 302-1 can include a switch signal generator 314 and digital processing circuits 316. A switch signal generator 314 can generate switch control signals SWIbal and/or SW_Is in response to an output of analog comparator 310 and a modulation clock Fmod. An output of switch signal generator 314 can be a bit stream that varies according to a sensor current (Is).
Regarding claim 1, Ogirko teaches An integrated circuit (Fig. 4a; 400) comprising: a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor (Fig. 4a and Para. [0028]-[0032]; a sigma-delta modulator 402 receive from touch sensor 436), wherein the sigma-delta modulator comprises: a first single-ended integrator (Fig. 4a; first integrator 412); a second single-ended integrator selectively coupled to an output of the first single-ended integrator (Fig. 45a; second integrator 414); a balancing circuit selectively coupled to a first input of the first single-ended integrator and to a second input of the second single-ended integrator (Fig. 4a; Switching circuitry 126 coupled to both the input of integrators 122 and 124); and logic coupled to the balancing circuit (Fig. 4a and Para. [0031]; logic 422 coupled to balancing circuitry),
The prior art as recorded fails to teach either alone or in any obvious combination the claim as recited in combination with “the logic to cause, based on an output of the second single-ended integrator, the balancing circuit to one of: apply a positive balancing current to the first input and a negative balancing current to the second input; or apply a positive balancing current to the second input and a negative balancing current to the first input”.
Regarding claim 21, Ogirko teaches An integrated circuit (Fig. 4a; 400) comprising: a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor (Fig. 4a and Para. [0028]-[0032]; a sigma-delta modulator 402 receive from touch sensor 436),
The prior art as recorded fails to teach either alone or in any obvious combination the claim as recited in combination with “wherein the sigma-delta modulator comprises: a first differential integrator comprising a first inverting terminal and a first non-inverting terminal, the first differential integrator to receive an input; a second differential integrator selectively coupled to a first output of the first differential integrator, the second differential integrator comprising a second inverting terminal and a second non-inverting terminal; a first balancing circuit selectively coupled between the first inverting terminal and the second inverting terminal; a second balancing circuit selectively coupled between the first non-inverting terminal and the second non-inverting terminal; and logic coupled to the first and second balancing circuits, the logic to cause, based on a second output of the second differential integrator, the first and second balancing circuits to one of: apply a positive balancing current to the second non-inverting terminal and a negative balancing current to the first inverting terminal; or apply a positive balancing current to the second inverting terminal and a negative balancing current to the first non-inverting terminal”.
Regarding claim 28, Ogirko teaches An integrated circuit (Fig. 4a; 400) comprising: a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor (Fig. 4a and Para. [0028]-[0032]; a sigma-delta modulator 402 receive from touch sensor 436),
The prior art as recorded fails to teach either alone or in any obvious combination the claim as recited in combination with “wherein the sigma-delta modulator comprises: a first differential integrator comprising a first inverting terminal and a first non- inverting terminal, the first differential integrator to receive an input; a second differential integrator selectively coupled to a first output of the first differential integrator, the second differential integrator comprising a second inverting terminal and a second non-inverting terminal; a first balancing circuit selectively coupled between the first inverting terminal and the first non-inverting terminal; a second balancing circuit selectively coupled between the second inverting terminal and the second non-inverting terminal; and logic coupled to the first and second balancing circuits, the logic to cause, based on a second output of the second differential integrator, the first and second balancing circuits to one of: apply a positive balancing current to the second non-inverting terminal and a negative balancing current to the first inverting terminal; or apply a positive balancing current to the second inverting terminal and a negative balancing current to the first non-inverting terminal”.
Conclusion
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/AMY ONYEKABA/Primary Examiner, Art Unit 2628