Prosecution Insights
Last updated: July 17, 2026
Application No. 19/248,870

MEMORY SYSTEM AND METHOD

Non-Final OA §112§DP
Filed
Jun 25, 2025
Priority
Sep 20, 2022 — JP 2022-148952 +1 more
Examiner
BRYAN, JASON B
Art Unit
2113
Tech Center
2100 — Computer Architecture & Software
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 9m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
238 granted / 311 resolved
+21.5% vs TC avg
Moderate +15% lift
Without
With
+14.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
11 currently pending
Career history
325
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
72.4%
+32.4% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 311 resolved cases

Office Action

§112 §DP
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement(s) (IDS) filed on 06/25/2025 and 12/11/2025 has/have been considered by the Examiner and made of record in the application file. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 24, 31, and 35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claims 24 and 31, there is a lack of antecedent basis in the claims for the first memory. As to claim 35, there is a lack of antecedent basis in the claims for the controller. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 19-21, 23-28, 30-35, and 37-38 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims of U.S. Patent No. 12360834 (see mapping below). Although the claims at issue are not identical, they are not patentably distinct from each other because the differences are minor obvious variations. 19. (New) A memory system comprising: a non-volatile memory including a first storage area, the first storage area including a word line and a plurality of memory cells connected to the word line (see claim 1); a controller configured to manage first information corresponding to temperature dependency of threshold voltages of the plurality of memory cells and second information in which voltage values corresponding to read voltages are recorded, the read voltages corresponding to threshold voltages of the plurality of memory cells (see claim 1, disclosing the first and second information and that the controller uses and records them); and a temperature sensor (see claim 1), wherein the controller is configured to, at a first timing, acquire a first temperature detection value from the temperature sensor, execute an acquisition operation on the first storage area (see claim 1), the acquisition operation including determining, multiple times, whether the plurality of memory cells are in an on state or an off state while varying a value of the voltage values and acquiring a first voltage value on the basis of a group of determination results, the group of determination results being obtained by the determining (see claim 3), the first voltage value being a value of the voltage values(see claim 1), and convert, on the basis of the first temperature detection value and the first information, the first voltage value into a second voltage value of the voltage values at a first temperature, and record the second voltage value in the second information (see claim 1). As to claim 20, see claim 1/3 of 12360834. As to claim 21, see claims 2/4 of 12360834. As to claim 23-25, see claims 7-9 of 12360834. 26. (New) A memory system comprising: a non-volatile memory including a first storage area, the first storage area including a word line and a plurality of memory cells connected to the word line (see claim 1); a controller configured to manage first information corresponding to temperature dependency of threshold voltages of the plurality of memory cells and second information in which voltage values corresponding to read voltages are recorded, the read voltages corresponding to threshold voltages of the plurality of memory cells (see claim 1), disclosing the first and second information and that the controller uses and records them); and a temperature sensor (see claim 1), wherein the controller is configured to, acquire a first temperature detection value from the temperature sensor (se claim 1), execute a first read operation of acquiring data from the plurality of memory cells (see claim 6), execute error correction on the data acquired by the first read operation (see claim 6, and execute a first acquisition operation when the error correction is successful, the first acquisition operation being an operation of calculating a first voltage value on the basis of a comparison between the data before the error correction and the data after the error correction, the first voltage value being a value of the voltage values (see claim 6), convert, on the basis of the first temperature detection value and the first information, the first voltage value into a second voltage value of the voltage values at a first temperature, and record the second voltage value in the second information (see claim 6). As to claims 27 and 28, see claim 1/3 of 12360834. As to claims 30-32, see claims 7-9 33. (New) A method of controlling a non-volatile memory, the non-volatile memory including a first storage area, the first storage area including a word line and a plurality of memory cells connected to the word line (see claim 10), the method comprising: managing first information corresponding to temperature dependency of threshold voltages of the plurality of memory cells (see claim 10); managing second information in which voltage values corresponding to read voltages are recorded, the read voltages corresponding to threshold voltages of the plurality of memory cells (see claim 10); performing, at a first timing, processing including acquiring a first temperature detection value from a temperature sensor (see claim 10), executing an acquisition operation on the first storage area (see claim 10), the acquisition operation including determining, multiple times, whether the plurality of memory cells are in an on state or an off state while varying a value of the voltage values and acquiring a first voltage value on the basis of a group of determination results, the group of determination results being obtained by the determining(see claim 12), the first voltage value being a value of the voltage values (see claim 10), and converting, on the basis of the first temperature detection value and the first information, the first voltage value into a second voltage value of the voltage values at a first temperature, and recording the second voltage value in the second information (see claim 10). As to claim 34, see claims 10/12. As to claim 35, see claims 11/13. As to claims 37 and 38, see claims 17 and 18 Claims 22, 29, and 36 rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 12360834 as detailed above in view of Sharon (US 9996281 B2). As to claim 22, the reference above does not explicitly teach the memory system is connectable to a host device, and the second timing is a timing at which the controller read data of the plurality of memory cells based on a read command from the host device. However, Sharon teaches host read commands to memory devices (see Fig. 1 and associated text). It would have been obvious, before the effective filing date, to a person of ordinary skill in the art to which said subject matter pertains to combine the reference with the use of host read commands because it can trigger adjustments to thresholds (see col. 3, lines 35-47) and can reduce error rates (see col. 5 lines 15-37). Claims 29 and 36 are rejected for the same reasons as claim 22. Conclusion No prior art was found with which it would be appropriate to reject the claims. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 11194523 B2, US 10475523 B2, US 20190286442 A1. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON B BRYAN whose telephone number is (571)270-7091. The examiner can normally be reached Mon-Fri, 8-5 First Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 5712720631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON B BRYAN/Primary Examiner, Art Unit 2114
Read full office action

Prosecution Timeline

Jun 25, 2025
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §112, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
91%
With Interview (+14.7%)
2y 10m (~1y 9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 311 resolved cases by this examiner. Grant probability derived from career allowance rate.

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