Prosecution Insights
Last updated: May 29, 2026
Application No. 19/248,958

Controller, Light Source Control System, And Display System

Non-Final OA §103
Filed
Jun 25, 2025
Priority
Jun 26, 2024 — JP 2024-102697
Examiner
GYAWALI, BIPIN
Art Unit
2625
Tech Center
2600 — Communications
Assignee
Seiko Epson Corporation
OA Round
1 (Non-Final)
58%
Grant Probability
Moderate
1-2
OA Rounds
2y 0m
Est. Remaining
58%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
219 granted / 376 resolved
-3.8% vs TC avg
Minimal -1% lift
Without
With
+-0.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
23 currently pending
Career history
402
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
95.4%
+55.4% vs TC avg
§102
3.6%
-36.4% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 376 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 4-7, 10-12, 14-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Akiba et al. (US 2023/0073794 A1, hereinafter “Akiba”) in view of Kikuta et al. (US 2019/0013826 A1, hereinafter “Kikuta”). As to claim 1, Akiba (Fig. 2) discloses a controller (400) that transmits control data (CNT, CD1, CD2) for controlling luminance of a light source to a light source driver (500) that drives the light source based on the control data (Para. 0025), the controller comprising: a control data generation circuit (Fig. 3 element 180) that generates the control data (CD1) based on luminance data indicating the luminance (IMB; Para. 0035); a first interface circuit (Fig. 6 element 140) that transmits the control data (CNT) to the light source driver (200; Para. 0028); a first storage circuit (Fig. 8 element 172) that stores first comparison data (ER1) based on the luminance data or the control data (Para. 0072-0077, the comparison data would have to be stored for some time in order to perform the calculation); and an error detection circuit (170) that performs error detection using the stored first comparison data (Para. 0079), wherein the light source driver (300) includes a second interface circuit (370) that receives the control data (CD1, CD2), a second circuit that stores the received control data (Fig. 8 element 172, Para. 0047, the comparison circuit of second error detection circuit), and a drive circuit (Fig. 2 element 520) that drives the light source based on the stored control data (Para. 0025), and the first interface circuit (Fig. 6 element 140) receives the control data (CNT, CD1, CD2) stored in the second storage circuit from the second interface circuit (370), and the error detection circuit (Fig. 9 element 310) performs error detection of the control data (CD2) received from the light source driver (200) by comparing the first comparison data (ER1) with second comparison data (ER2) based on the control data received from the light source driver (Para. 0042-0043). Akiba does not expressly disclose a second storage circuit. However, Kikuta (Fig. 1) teaches a second storage circuit (Fig. 1 element 150; Para. 0168). It would have been obvious to one of ordinary skill in the art to combine the teaching of Kikuta to include a register in the device disclosed by Akiba. The motivation would have been to store the error detection information (Kikuta; Para. 0168). As to claim 2, Akiba (Fig. 6) discloses the controller according to claim 1, wherein the first comparison data (ER1) and the second comparison data (ER2) are error check codes generated from the control data, error check codes generated from the luminance data (IMB; Para. 0040), the control data, or the luminance data. As to claim 4, Akiba (Fig. 3) discloses the controller according to claim 1, wherein the error detection circuit (300) includes: a first error check code generation circuit (170) that generates an error check code (ER1) from the control data generated by the control data generation circuit and stores the error check code as the first comparison data (ER1) in the first storage circuit; a second error check code generation circuit (370) that generates an error check code (ER2) from the control data received by the first interface circuit and outputs the error check code as the second comparison data (ER2); and a comparison circuit (310) that compares the first comparison data (ER1) with the second comparison data (ER2) and outputs a comparison result as an error signal (CNT; Para. 0045, 0048). As to claim 5, Akiba (Fig. 3) discloses the controller according to claim 1, wherein the error detection circuit includes: a first error check code generation circuit (370) that generates an error check code (ER2) from the luminance data input (IMB) to the control data generation circuit and stores the error check code as the first comparison data (ER2) in the first storage circuit; a conversion circuit (Fig. 8 element 171) that converts the control data received by the first interface circuit (110) into the luminance data (IMB); a second error check code generation circuit (172) that generates an error check code (ER1) from the luminance data (IMC) output by the conversion circuit (171) and outputs the error check code as the second comparison data (ER1); and a comparison circuit (Fig. 3 element 310) that compares the first comparison data (ER2) with the second comparison data (ER1) and outputs a comparison result as an error signal (CNT; Para. 0045, 0048). As to claim 6, Akiba (Fig. 6) discloses the controller according to claim 1, wherein the first storage circuit (170) stores the control data generated by the control data generation circuit as the first comparison data (ER1), the first interface circuit (370, 310) receives the control data from the light source driver as the second comparison data (CD2, ER2), and the error detection circuit includes a comparison circuit (310) that compares the first comparison data (ER1) with the second comparison data (ER2) and outputs a comparison result as an error signal (CNT). As to claim 7, Akiba (Fig. 6) discloses the controller according to claim 1, wherein the first storage circuit (370) stores the luminance data input to the control data generation circuit as the first comparison data (ER2), and the error detection circuit includes: a conversion circuit (Fig. 8 element 171) that converts the control data received by the first interface circuit (110) into the luminance data (IMC) and outputs the converted luminance data as the second comparison data (ER1); and a comparison circuit (Fig. 6 element 310) that compares the first comparison data (ER2) with the second comparison data (ER1) and outputs a comparison result as an error signal (CNT). As to claim 10, Akiba discloses the controller according to claim 1, wherein the first interface circuit transmits and receives the control data in each frame (Para. 0034), and the error detection circuit compares the first comparison data with the second comparison data in each frame (Para. 0092). As to claim 11, Akiba (Fig. 3) discloses the controller according to claim 1, further comprising a luminance data processing circuit (115) that performs processing of changing a predetermined bit of the luminance data at predetermined time intervals (Para. 0030, 0038) and outputs processed luminance data (IMB) as a result of the processing to the control data generation circuit (170), wherein the first storage circuit stores the processed luminance data or the first comparison data based on the control data (Para. 0032). As to claim 12, Akiba discloses the controller according to claim 1, wherein the control data generation circuit generates the control data for turning off the light source when an error is detected by the error detection circuit (Para. 0043). As to claim 14, Akiba (Fig. 6) discloses the controller according to claim 1, wherein the first interface circuit (140) transmits a signal for turning off driving of the light source by the light source driver to the light source driver when an error is detected by the error detection circuit (Para. 0043). As to claim 15, Akiba (Fig. 6) discloses the controller according to claim 1, further comprising a third interface circuit (200, reception circuit of 200) that communicates with a host device of the controller (Fig. 2 element 500), wherein the third interface circuit transmits an error signal to the host device when an error is detected by the error detection circuit (Para. 0043). As to claim 17, Akiba (Fig. 2) discloses t light source control system comprising: the controller according to claim 1 (400); and the light source driver (520). As to claim 18, Akiba (Fig. 2) discloses t display system comprising: the controller according to claim 1; the light source driver (520); the light source (530); and a display panel (540) that a light enters from the light source (Para. 25-0026). Claim(s) 3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Akiba and Kikuta as applied to claim 1 above, and further in view of Lee et al. (US 9,183,790 B2, hereinafter “Lee”). As to claim 3, Akiba in view of Kikuta does not disclose the controller according to claim 1, wherein the control data is PWM data indicating a pulse width of a pulse signal for driving the light source or current value data indicating a current value for driving the light source. However, Lee teaches the control data is PWM data indicating a pulse width of a pulse signal for driving the light source or current value data indicating a current value for driving the light source (Col. 5 lines 1-4). It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee to use PWM signal in the device disclosed by Akiba/Kikuta. The motivation would have been to control the backlight (Lee; Col. 5 lines 4-6). As to claim 8, Akiba in view of Kikuta does not disclose the controller according to claim 1, wherein the first interface circuit transmits the control data to a first light source driver to an n-th light source driver including the light source driver, and then, receives the control data from the first light source driver to the n-th light source driver, n being an integer of 2 or more. However, Lee teaches the first interface circuit transmits the control data to a first light source driver to an n-th light source driver including the light source driver (INV1..INVk), and then, receives the control data from the first light source driver to the n-th light source driver, n being an integer of 2 or more (Col. 3 lines 13-20). It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee to include a plurality of light source drivers in the device disclosed by Akiba/Kikuta. The motivation would have been to drive a plurality of light sources (Col. 3 lines 17-19). As to claim 9, Akiba in view of Kikuta does not disclose the controller according to claim 1, wherein the first interface circuit sequentially performs transmission and reception of the control data to and from a first light source driver, transmission and reception of the control data to and from a second light source driver,..., and transmission and reception of the control data to and from an n-th light source driver among the first light source driver to the n-th light source driver including the light source driver, n being an integer of 2 or more. However, Lee teaches the first interface circuit sequentially performs transmission and reception of the control data to and from a first light source driver, transmission and reception of the control data to and from a second light source driver,..., and transmission and reception of the control data to and from an n-th light source driver among the first light source driver to the n-th light source driver including the light source driver, n being an integer of 2 or more (Fig. 3; Col. 4 lines 41-46, Col. 5 lines 22-25). It would have been obvious to one of ordinary skill in the art to combine the teaching of Lee to sequentially control the light source driver in the device disclosed by Akiba/Kikuta. The motivation would have been to independently control the brightness for each area (Lee; Col. 5 lines 22-25). Claim(s) 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Akiba and Kikuta as applied to claim 1 above, and further in view of Wang (US 11,929,043 B1, hereinafter “Wang”). As to claim 13, Akiba in view of Kikuta does not disclose the controller according to claim 1, further comprising a dimming processing circuit that generates the luminance data by dimming processing, wherein the dimming processing circuit stops the dimming processing and outputs luminance data having a given value when an error is detected by the error detection circuit. However, Wang (Fig. 8) teaches a dimming processing circuit (102) that generates the luminance data by dimming processing, wherein the dimming processing circuit stops the dimming processing and outputs luminance data having a given value when an error (ERR) is detected by the error detection circuit (Col. 8 lines 12-37). It would have been obvious to one of ordinary skill in the art to combine the teaching of Wang to control local dimming in the device disclosed by Akiba/Kikuta. The motivation would have been to ensure the user can see the entire image content (Wang; Col. 8 lines 21-25). As to claim 16, Akiba does not disclose the controller according to claim 1, further comprising a dimming processing circuit that receives image data for displaying an image on a display panel that lights enter from a plurality of light sources including the light source, and generates the luminance data for each of the plurality of light sources by performing local dimming processing based on the image data. However, Wang (Fig. 4) teaches a dimming processing circuit (102) that receives image data (IMG_IN) for displaying an image on a display panel that lights enter from a plurality of light sources including the light source (Fig. 5), and generates the luminance data for each of the plurality of light sources by performing local dimming processing based on the image data (Fig. 6; Col. 29-40). It would have been obvious to one of ordinary skill in the art to combine the teaching of Wang to control local dimming in the device disclosed by Akiba/Kikuta. The motivation would have been to provide warning signals feasibly (Wang; Col. 6 lines 38-40). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure. Kobayashi (US 2020/0342796 A1) discloses error detection circuit (Fig. 3). Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPIN GYAWALI whose telephone number is (571)272-1597. The examiner can normally be reached M-F 9:00-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Will Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BIPIN GYAWALI Examiner Art Unit 2625 /BIPIN GYAWALI/ Examiner, Art Unit 2625
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Prosecution Timeline

Jun 25, 2025
Application Filed
Mar 30, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
58%
Grant Probability
58%
With Interview (-0.6%)
2y 11m (~2y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 376 resolved cases by this examiner. Grant probability derived from career allowance rate.

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