DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f) unless otherwise noted in this application.
The “access control unit” is modified by the sufficient structure of the “switch” for performing the claimed functions of controlling access to the memory via the test pad as the switch is used to “connect… the test pad to the memory”. Accordingly, this limitation is not interpreted under 35 USC §112(f) in claims 1-20.
Claim Objections
Claims 3, 6 and 13-18 are objected to because of the following informalities:
Claim 3 recites, “wherein the controller is further configured to transmit a response to the host acknowledging the first command”, which as best understood by the Examiner in light of the specification, should be amended to recite “wherein the is an acknowledgment”.
Claim 6 recites, “wherein the controller is further configured to transmit, based on the second command being determined to contain the correct key and address, a response to the host in response to the second command authenticating the host to communicate with the memory via the test pad”, which as best understood by the Examiner in light of the specification, should be amended to recite “wherein the controller is further configured to transmit, based on the second command being determined to contain the correct key and address, a response to the host authenticating the host to communicate with the memory via the test pad
Claim 13 recites, “receive, after detection of modification of the reserved byte, a notification from a firmware to activate a switch of the access control unit to connect the test pad to the non-volatile memory”, which as best understood by the Examiner in light of the specification, should be amended to recite “receive, after detection by a firmware of modification of the reserved byte, a notification from [[a]]the firmware to activate a switch of the access control unit to connect the test pad to the non-volatile memory”.
Claims 14-18 are objected to for failing to cure the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 7-10, 12-16 and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 8-10, 14 and 19-20 of U.S. Patent No. US 12,411,619 B2 (‘619).
Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-4, 8-10, 14 and 19-20 of ‘619 contain every element of claims 1-4, 7-10, 12-16 and 19-20 of the instant application and as such anticipates claims 1-4, 7-10, 12-16 and 19-20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berq, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims of the Instant Application
Claims of ‘619
1. A device, comprising:
an access control unit configured to control access to memory via a test pad;
a controller configured to: receive, from a host, a first command associated with accessing the memory via the test pad;
transmit, to the host, a response to the first command;
receive a second command to modify a reserved byte of a partition of the memory;
connect, in response to detection of modification of the reserved byte and based on activation of a switch of the access control unit, the test pad to the memory; and
enable the host to access the memory via the test pad.
20. A device, comprising: a host; a non-volatile memory configured to store data;
an access control unit configured to control access to the non-volatile memory by the host via a test pad; and
a controller, wherein the controller is configured to; receive a command from the host, wherein the command is associated with accessing the non-volatile memory via the test pad;
transmit, to the host, a response code acknowledging the command, wherein the response code facilitates authentication of the host to communicate with the non-volatile memory;
modify, in response to a second command issued based on the response code being determined to be correct, a reserved byte of a protected memory partition;
activate, in response to detection of modification of the reserved byte, a switch in the access control unit to close a circuit to connect the test pad to the non-volatile memory; and
enable the host to access the non-volatile memory via the test pad upon closing the circuit.
1. A device, comprising:
an access control unit configured to control access to memory via a test pad;
a controller configured to: receive, from a host, a first command associated with accessing the memory via the test pad;
transmit, to the host, a response to the first command;
receive a second command to modify a reserved byte of a partition of the memory;
connect, in response to detection of modification of the reserved byte and based on activation of a switch of the access control unit, the test pad to the memory; and
enable the host to access the memory via the test pad.
1. A system, comprising: a non-volatile memory configured to store data;
an access control unit configured to control access to the non-volatile memory by a host via a test pad; and
a controller, wherein the controller is configured to; receive a first command from the host, wherein the first command is associated with accessing the non-volatile memory via the test pad;
transmit, to the host, a response code acknowledging the first command;
modify, in response to a second command issued based on the response code being determined to be correct, a reserved byte of a protected memory;
activate, in response to detection of modification of the reserved byte, a switch in the access control unit to close a circuit to connect the test pad to the non-volatile memory; and
enable the host to access the non-volatile memory via the test pad after activation of the switch.
2. The device of claim 1, wherein the controller is further configured to connect the test pad to the memory by closing a circuit based on the activation of the switch.
1… activate, in response to detection of modification of the reserved byte, a switch in the access control unit to close a circuit to connect the test pad to the non-volatile memory…
3. The device of claim 1, wherein the controller is further configured to transmit a response to the host acknowledging the first command.
1…transmit, to the host, a response code acknowledging the first command…
4. The device of claim 1, wherein the controller is further configured to determine whether the second command contains a correct key and address for accessing the partition of the memory.
4. The system of claim 1, wherein the controller is further configured to: receive the second command to modify the reserved byte of the protected memory partition of the non-volatile memory, wherein the second command to modify the reserved byte of the protected memory partition comprises a replay protected memory block authenticated data write command, wherein the replay protected memory block authenticated data write command comprise a message authentication code key and a replay protected memory block address associated with the protected memory partition of the non-volatile memory
7. The device of claim 1, wherein the device further comprises firmware configured to
monitor the partition of the memory.
2. The system of claim 1, wherein the system further comprises firmware and the controller is further configured to activate the switch in the access control unit in response to a notification received from the firmware of the non-volatile memory.
3. The system of claim 2, wherein the firmware is configured to: monitor the reserved byte; and generate the notification upon detecting that the reserved byte of the protected memory partition of the non-volatile memory has been modified.
8. The device of claim 7, wherein the firmware is further configured to: transmit, upon detection of a change in value of the reserved byte, a notification to the controller to activate the switch.
2. The system of claim 1, wherein the system further comprises firmware and the controller is further configured to activate the switch in the access control unit in response to a notification received from the firmware of the non-volatile memory.
3. The system of claim 2, wherein the firmware is configured to: monitor the reserved byte; and generate the notification upon detecting that the reserved byte of the protected memory partition of the non-volatile memory has been modified.
9. The device of claim 1, wherein the controller is further configured to receive a third command from the host to perform an operation with respect to the memory after the host is enabled to access the memory via the test pad.
8. The system of claim 7, wherein the controller is further configured to receive a fourth command from the host to modify the reserved byte of the protected memory partition.
9. The system of claim 8, wherein the controller is further configured to modify the reserved byte of the protected memory partition based on the fourth command.
10. The system of claim 9, wherein the controller is further configured to deactivate a switch in the access control unit to open a circuit to disconnect the test pad from the non-volatile memory.
10. The device of claim 9, wherein the controller is further configured to execute the third command to perform the operation with respect to the memory after the host is enabled to access the memory via the test pad.
8. The system of claim 7, wherein the controller is further configured to receive a fourth command from the host to modify the reserved byte of the protected memory partition.
9. The system of claim 8, wherein the controller is further configured to modify the reserved byte of the protected memory partition based on the fourth command.
10. The system of claim 9, wherein the controller is further configured to deactivate a switch in the access control unit to open a circuit to disconnect the test pad from the non-volatile memory.
12. The device of claim 1, wherein the controller is further configured to disconnect the test pad from the memory after toggling the reserved byte.
8. The system of claim 7, wherein the controller is further configured to receive a fourth command from the host to modify the reserved byte of the protected memory partition.
9. The system of claim 8, wherein the controller is further configured to modify the reserved byte of the protected memory partition based on the fourth command.
10. The system of claim 9, wherein the controller is further configured to deactivate a switch in the access control unit to open a circuit to disconnect the test pad from the non-volatile memory.
13. A system, comprising:
a non-volatile memory configured to store data;
an access control unit configured to control access to the non-volatile memory via a test pad; and
a controller, wherein the controller is configured to:
receive a first command to modify a reserved byte of a partition of the non-volatile memory; modify, in response to the first command, the reserved byte of the partition of the non-volatile memory;
receive, after detection of modification of the reserved byte, a notification from a firmware to activate a switch of the access control unit to connect the test pad to the non-volatile memory; and
enable, after the test pad is connected to the non-volatile memory, a host to access the non-volatile memory via the test pad.
1. A system, comprising:
a non-volatile memory configured to store data;
an access control unit configured to control access to the non-volatile memory by a host via a test pad; and
a controller, wherein the controller is configured to;
receive a first command from the host, wherein the first command is associated with accessing the non-volatile memory via the test pad; transmit, to the host, a response code acknowledging the first command; modify, in response to a second command issued based on the response code being determined to be correct, a reserved byte of a protected memory;
activate, in response to detection of modification of the reserved byte, a switch in the access control unit to close a circuit to connect the test pad to the non-volatile memory; and
enable the host to access the non-volatile memory via the test pad after activation of the switch.
14. The system of claim 13, wherein the controller is further configured to deactivate the switch of the access control unit to disconnect the test pad from the non-volatile memory.
10. The system of claim 9, wherein the controller is further configured to deactivate a switch in the access control unit to open a circuit to disconnect the test pad from the non-volatile memory.
15. The system of claim 13, wherein the controller is further configured to receive a second command from the host associated with accessing the non-volatile memory.
1… wherein the controller is configured to; receive a first command from the host, wherein the first command is associated with accessing the non-volatile memory via the test pad…
16. The system of claim 15, wherein the controller is further configured to transmit a response code to the host in response to the second command that enables the host to issue the first command to modify the reserved byte.
1…transmit, to the host, a response code acknowledging the first command; modify, in response to a second command issued based on the response code being determined to be correct, a reserved byte of a protected memory…
19. A method, comprising receiving, by a controller of a memory, a first command from a host, wherein the first command is associated with accessing the memory via a test pad;
transmitting, by the controller of the memory and to the host, a response to the first command;
modifying, by the controller of the memory and in response to a second command, a reserved byte of the memory;
connecting, upon detection of modification of the reserved byte, the test pad to the memory;
and enabling, by the controller, the host to access the non-volatile memory via the test pad after the test pad is connected to the memory.
14. A method, comprising: receiving, by a controller of a non-volatile memory system, a first command from a host, wherein the first command is associated with accessing non-volatile memory of the non-volatile memory system via a test pad;
transmitting, by the controller of the non-volatile memory system and to the host, a response code acknowledging the first command;
modifying, by the controller of the non-volatile memory system and in response to a second command issued based on the response code being determined to be correct, a reserved byte of a protected memory partition;
activating, by the controller of the non-volatile memory system and in response to detection of modification of the reserved byte, a switch in an access control unit to close a circuit to connect the test pad to the non-volatile memory;
and enabling, by the controller of the non-volatile memory system, the host to access the non-volatile memory via the test pad after activation of the switch.
20. The method of claim 19, further comprising receiving, from the host, a third command to perform an operation with respect to the memory.
19. The method of claim 14, further comprising opening the circuit in response to a third command received from the host.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13-14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2021/0286904 A1 (Cariello) in view of US Patent Application Publication No. US 2006/0212679 Al (Alfano).
Regarding claim 13:
Cariello discloses, a system (memory system (400) including host (425), comprising: a non-volatile memory configured to store data (memory die (415) including NAND memory arrays (i.e. non-volatile) and register (470) which also stores data [0057] [Fig. 4]. The memory die (415) store data in response to commands from the host as performed by the controller (410) [0057-0058]) an access control unit (switching component (450) [0069]) configured to control access to the non-volatile memory (memory die(415)) by a host (425) via a test pad ((435) by teaching that the switching component selectively provides either an internal control signal (from the memory controller (410)) or an external control signal (i.e. provided from the test pads (435)) [0069]) ]); and a controller (410); wherein the controller (410) is configured to receive a first command to modify a stored value; modify, in response to the first command, the reserved stored value (by disclosing receiving commands by the controller from an authenticated host that are to modify the value stored in a register (470), where the memory device (110) may write (i.e., modify) the value to the secure register (470) (i.e., a reserved partition of memory) based on receiving the command from the authenticated host [0030] [0069-0074]) receive, after detection of modification of the stored value, a notification from a firmware to activate a switch of the access control unit to connect the test pad to the non-volatile memory; and enable the host to access the non-volatile memory via the test pad (by disclosing that the controller and switching component may be implemented with a combination of hardware and software, including firmware, such that the controller (with firmware) may enable or disable (switching) the signal paths from the test pads with the switching component (450) based on the value stored in the memory as determined by the firmware (i.e. in response a notification) [0027] [0030] [0033] [0069-0070] [0075-0076] [0133]).
Cariello discloses that the memory location that is used to control access to the non-volatile memory through the test pad is a secure register. Cariello does not explicitly disclose, but Alfano teaches that the memory location may be a reserved byte of a partition of the non-volatile memory (by teaching that memory blocks of a flash memory may be locked from reading or writing through a test port by writing bits of data to security lock bytes of the flash memory (i.e., reserved byte of a partition of the non-volatile memory) [see Fig. 21] [0171]. Bits written with a ‘0’ prevent corresponding data blocks from being read/written/erased through the test port. The bits may be read or cleared (i.e., written to ‘0’, to protect additional memory ranges), but cannot be reset (i.e., written to a ‘1’, unlocking memory ranges for access) without erasing the entire memory).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the memory location for storing the indication of whether access through the test pads was granted or not in the secure register as taught by Cariello with a location in the flash memory itself, such as the security lock bytes of the flash memory that control read/write/erase access through the test port as taught by Alfano. Cariello teaches controlling access from test pads to a flash memory device based on the value stored in a secure register, whereas Alfano teaches controlling access from a test port to a flash memory based on the value stored in security block bytes of the flash memory itself. One of ordinary skill in the art could have substituted the location of the control access bits in the secure register with a location in a security lock byte of the flash memory itself, and the results would have been predictable. Namely, control of access to the flash memory would continue to be controlled by values stored in a secure memory, but the location would change from the secure register to a location within the flash memory itself.
Regarding claim 14:
The system of claim 13 is made obvious by Cariello in view of Alfano (Cariello-Alfano).
Cariello further discloses wherein the controller is further configured to deactivate the switch of the access control unit to disconnect the test pad from the non-volatile memory (by disclosing that the switching component (450) is configured to select different conductive paths, including a conductive path that no longer connects the test pads (435) to the non-volatile memory die (415) [0015] [0069-0070]. The switch may be configured to open (deactivate) to isolate the unselected conductive path (deactivate) [0071] [0076] [0125]).
Regarding claim 17:
The system of claim 13 is made obvious by Cariello-Alfano.
Cariello further discloses, wherein the test pad is further configured to measure test data associated with operation of the non-volatile memory (by teaching that the test pads support providing inputs to the memory device and observing resulting outputs (i.e., measure test data associated with operation of the non-volatile memory), such as to detect errors or verify behavior, or perform read accesses [0010-0011] [0063-0065]. The test pads may enable access to the memory, such as read access, which involves measuring the logic state in the transistors of the memory cells [0039-0048] [0086-0087] [0095-0098]).
Regarding claim 18:
The system of claim 17 is made obvious by Cariello-Alfano.
Cariello further discloses, wherein the controller is further configured to provide the test data measured via the test pad to the host (by disclosing that the memory may be accessed through the test pads, such as to perform a read access, which involves read data being returned to the host, or to observe resulting outputs, which are returned to a host, in a diagnostic procedure [0010-0011] [0039-0048] [0057-0059] [0086-0087] [0095-0098]).
Claim 1-12, 15-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cariello-Alfano in further view of US Patent Application Publication US 2021/0357125 A1 (Mendes).
Regarding claim 1 and analogous claim 19:
Cariello discloses, A device (memory device (405)), comprising: an access control unit configured to control access to memory via a test pad (by disclosing switching component (450) [Fig. 4], which controls access to memory die (415) via test pads (435) [Fig. 4] [0069]); a controller configured to: perform authentication associated with accessing the memory via the test pad (by teaching that before the value of the secure memory location can be written that allows the host to access the memory via the test pads (435), the host is authenticated [0014] [0030] [0074]) receive a second command to modify stored value (by disclosing receiving commands by the controller from an authenticated host that are to modify the value stored in a register (470), where the memory device (110) may write (modify) the value to the secure register (470) (a reserved partition of memory) based on receiving the command from the authenticated host [0030] [0069-0074]) connect, in response to detection of modification of the stored value and based on activation of a switch of the access control unit, the test pad to the memory; and enable the host to access the memory via the test pad (by disclosing that the controller and switching component may be implemented with a combination of hardware and software, including firmware, such that the controller (with firmware) may enable or disable (switching) the signal paths from the test pads with the switching component (450) based on the value stored in the memory as determined by the firmware (in response detection of modification) [0071] [0080-0081] [0092-0093] [0110] [0123-0124]).
Cariello discloses that the memory location that is used to control access to the non-volatile memory through the test pad is a secure register. Cariello does not explicitly disclose, but Alfano teaches that the memory location may be a reserved byte of a partition of the non-volatile memory (by teaching that memory blocks of a flash memory may be locked from reading or writing through a test port by writing bits of data to security lock bytes of the flash memory (i.e., reserved byte of a partition of the non-volatile memory) [see Fig. 21] [0171]. Bits written with a ‘0’ prevent corresponding data blocks from being read/written/erased through the test port. The bits may be read or cleared (i.e., written to ‘0’, to protect additional memory ranges), but cannot be reset (i.e., written to a ‘1’, unlocking memory ranges for access) without erasing the entire memory).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the memory location for storing the indication of whether access through the test pads was granted or not in the secure register as taught by Cariello with a location in the flash memory itself, such as the security lock bytes of the flash memory that control read/write/erase access through the test port as taught by Alfano. Cariello teaches controlling access from test pads to a flash memory device based on the value stored in a secure register, whereas Cariello teaches controlling access from a test port to a flash memory based on the value stored in security block bytes of the flash memory itself. One of ordinary skill in the art could have substituted the location of the control access bits in the secure register with a location in a security lock byte of the flash memory itself, and the results would have been predictable. Namely, control of access to the flash memory would continue to be controlled by values stored in a secure memory, but the location would change from the secure register to a location within the flash memory itself.
Cariello does not explicitly disclose, but Mendes teaches, receive, from a host, a first command to perform authentication (by teaching that a host (120) may send an authentication request (i.e. second command) with an authentication key (604) to a memory sub-system (110) [Fig. 6]. The authentication key may be a public key that corresponds to a private key held by the host so the memory sub-system can ensure the signature of the host is valid and was created by the host system [0055]. The authentication request may be part of an authentication process that determines whether a host (120) is able to access a memory subsystem (110) through a debug port according to an identified privilege level corresponding to the received authentication key [Fig. 6]) transmit, to the host, a response to the first command (by teaching that the authentication request may be part of an authentication process that determines whether a host (120) is able to access a memory subsystem (110) through a debug port according to an identified privilege level corresponding to the received authentication key [Fig. 6]. Depending on the determined level of privilege, the host is sent a privilege key by the memory as part of an authentication response (606). The authenticated host may then send the privilege key with a request to enable the debug port or to access the debug information [Fig. 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 2:
The device of claim 1 is made obvious by Cariello-Alfano in further view of Mendes (Cariello-Alfano-Mendes).
Cariello further discloses, wherein the controller is further configured to connect the test pad to the memory by closing a circuit based on the activation of the switch (by disclosing that the switching component (450) is configured to select different conductive paths, including a conductive path that connects the test pads (435) to the non-volatile memory die (415) [0015] [0069-0070]. The switch may be configured to close (activate) to connect the selected conductive path [0071] [0080-0081] [0092-0093] [0110] [0123-0124]).
Regarding claim 3:
The device of claim 1 is made obvious by Cariello-Alfano-Mendes.
Cariello does not explicitly disclose, but Mendes teaches wherein the controller is further configured to transmit a response to the host acknowledging the first command (by teaching that the authentication request may be part of an authentication process that determines whether a host (120) is able to access a memory subsystem (110) through a debug port according to an identified privilege level corresponding to the received authentication key [Fig. 6]. Depending on the determined level of privilege, the host is sent a privilege key by the memory as part of an authentication response (606) (acknowledging the first command). The authenticated host may then send the privilege key with a request to enable the debug port or to access the debug information [Fig. 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 4:
The device of claim 1 is made obvious by Cariello-Alfano-Mendes.
Cariello does not explicitly disclose, but Alfano teaches, wherein the controller is further configured to determine whether the second command contains an address for accessing the partition of the memory (by teaching that memory blocks of a flash memory may be locked from reading or writing through a test port by writing bits of data to security lock bytes of the flash memory (i.e., reserved byte of a partition of the non-volatile memory) [see Fig. 21] [0171]. Bits written with a ‘0’ prevent corresponding data blocks from being read/written/erased through the test port, while bits written to ‘1’ allow corresponding memory ranges to be unlocked for access, such as read/written/erase, through the test port [Fig. 21] [0171]. As seen in [Fig. 21], they are stored at addresses 0x7DFF and 0x7DFE.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the memory location for storing the indication of whether access through the test pads was granted or not in the secure register as taught by Cariello with a location at a particular address in the flash memory itself, such as the security lock bytes of the flash memory that control read/write/erase access through the test port as taught by Alfano. Cariello teaches controlling access from test pads to a flash memory device based on the value stored in a secure register, whereas Alfano teaches controlling access from a test port to a flash memory based on the value stored in security block bytes at a particular address of the flash memory itself. One of ordinary skill in the art could have substituted the location of the control access bits in the secure register with a location in a security lock byte of a particular address of the flash memory itself, and the results would have been predictable. Namely, control of access to the flash memory would continue to be controlled by values stored in a secure memory, but the location would change from the secure register to a location within the flash memory itself.
Cariello does not explicitly disclose, but Mendes teaches, wherein the controller is further configured to determine whether the second command contains a correct key for accessing the partition of the memory (by teaching that the host sends the request to enable the debug port with the privilege key (616), and the memory authenticates the privilege key against a level of access associated with the key [0057] [0062]. If the request is for a level of access not granted by the privilege key, then the request may be denied (740) [0064] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information, and checking if that privilege key allows the requested level of access as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 5:
The device of claim 4 is made obvious by Cariello-Alfano-Mendes.
Cariello teaches that diagnostic access is provided via the test pad (by disclosing that the memory may be accessed through the test pads to provide test inputs, such as to perform a read access, which involves read data being returned to the host, or to observe resulting outputs, which are returned to a host, in a diagnostic procedure [0010-0011] [0039-0048] [0057-0059] [0086-0087] [0095-0098])
Cariello does not explicitly disclose, but Mendes teaches, wherein the controller is further configured to prevent, based on the second command being determined to not contain the correct key and address, the host from accessing the memory in a diagnostic access (by teaching that the host sends the request to enable the debug port with the privilege key (616), and the memory authenticates the privilege key against a level of access associated with the key [0057] [0062]. If the request is for a level of access not granted by the privilege key, then the request may be denied (618) (740) (i.e., does not contain the correct key and address) [0057] [0064] [Fig. 6] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information, and checking if that privilege key allows the requested level of access and sending a confirmation to the host and allowing the access when the privilege key allows the requested level of access, or denying the access when the privilege key does not allow the requested level of access as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 6:
The device of claim 4 is made obvious by Cariello-Alfano-Mendes.
Cariello teaches that diagnostic access is provided via the test pad (by disclosing that the memory may be accessed through the test pads to provide test inputs, such as to perform a read access, which involves read data being returned to the host, or to observe resulting outputs, which are returned to a host, in a diagnostic procedure [0010-0011] [0039-0048] [0057-0059] [0086-0087] [0095-0098])
Cariello does not explicitly disclose, but Alfano teaches that the controller receiving the request to enable the diagnostic access would include the controlling receiving a request being determined to contain a request to write a particular value to an address of the lock bytes (by disclosing that the memory may be accessed through the test pads to provide test inputs, such as to perform a read access, which involves read data being returned to the host, or to observe resulting outputs, which are returned to a host, in a diagnostic procedure [0010-0011] [0039-0048] [0057-0059] [0086-0087] [0095-0098]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the memory location for storing the indication of whether access through the test pads was granted or not in the secure register as taught by Cariello with a location at a particular address in the flash memory itself, such as the security lock bytes of the flash memory that control read/write/erase access through the test port as taught by Alfano. Cariello teaches controlling access from test pads to a flash memory device based on the value stored in a secure register, whereas Alfano teaches controlling access from a test port to a flash memory based on the value stored in security block bytes at a particular address of the flash memory itself. One of ordinary skill in the art could have substituted the location of the control access bits in the secure register with a location in a security lock byte of a particular address of the flash memory itself, and the results would have been predictable. Namely, control of access to the flash memory would continue to be controlled by values stored in a secure memory, but the location would change from the secure register to a location within the flash memory itself.
Cariello does not explicitly disclose, but Mendes teaches, wherein the controller is further configured to transmit, based on the second command being determined to contain the correct key and address, a response to the host in response to the second command authenticating the host to communicate with the memory in a diagnostic access (by teaching that the host sends the request to enable the debug port (i.e. a write request with a value to enable access to the test pads with the address of the lock byte in non-volatile memory as taught by Cariello in view of Alfano) with the privilege key (616), and the memory authenticates the privilege key against a level of access associated with the key [0057] [0062]. If the request is for a level of access not granted by the privilege key, then the request may be denied (740) (618), but if the level of access is allowed (618), the request may be granted and a confirmation may be sent back to the host (620) (i.e., a response to the host in response to the second command authenticating the host to communicate with the memory) [0057] [0064] [Fig. 6] [Fig. 7]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information, and checking if that privilege key allows the requested level of access and sending a confirmation to the host and allowing the access when the privilege key allows the requested level of access, or denying the access when the privilege key does not allow the requested level of access as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 7:
The device of claim 1 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the device further comprises firmware configured to monitor the stored value (by disclosing that the controller and switching component may be implemented with a combination of hardware and software, including firmware, such that the controller (with firmware) may enable or disable (switching) the signal paths from the test pads with the switching component (450) based on the value stored in the memory as determined by the firmware (firmware configured to monitor the stored value) [0071] [0080-0081] [0092-0093] [0110] [0123-0124]
Cariello does not explicitly disclose, but Alfano teaches that the monitored location should be the partition of the memory (by teaching that memory blocks of a flash memory may be locked from reading or writing through a test port by writing bits of data to security lock bytes of the flash memory (i.e., reserved byte of a partition of the non-volatile memory) [see Fig. 21] [0171]. Bits written with a ‘0’ prevent corresponding data blocks from being read/written/erased through the test port. The bits may be read or cleared (i.e., written to ‘0’, to protect additional memory ranges), but cannot be reset (i.e., written to a ‘1’, unlocking memory ranges for access) without erasing the entire memory).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the memory location for storing the indication of whether access through the test pads was granted or not in the secure register as taught by Cariello with a location in the flash memory itself, such as the security lock bytes of the flash memory that control read/write/erase access through the test port as taught by Alfano. Cariello teaches controlling access from test pads to a flash memory device based on the value stored in a secure register, whereas Cariello teaches controlling access from a test port to a flash memory based on the value stored in security block bytes of the flash memory itself. One of ordinary skill in the art could have substituted the location of the control access bits in the secure register with a location in a security lock byte of the flash memory itself, and the results would have been predictable. Namely, control of access to the flash memory would continue to be controlled by values stored in a secure memory, but the location would change from the secure register to a location within the flash memory itself.
Regarding claim 8:
The device of claim 7 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses wherein the firmware is further configured to: transmit, upon detection of a change in value of the reserved byte, a notification to the controller to activate the switch (by disclosing that the controller and switching component may be implemented with a combination of hardware and software, including firmware, such that the controller (i.e. with firmware) may enable or disable the switching of the signal paths from the test pads based on the value stored in the memory as determined by the firmware (transmit, upon detection of a change in value of the reserved byte) [0027] [0033] [0069-0070] [0075-0076] [0133]).
Regarding claim 9 and analogous claim 20:
The device of claim 1 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the controller is further configured to receive a third command from the host to perform an operation with respect to the memory after the host is enabled to access the memory via the test pad (by teaching that after the signals (460) from the test pads (435) are connected to the memory (415) with the switching component (450), the host device (425) may perform diagnostic accesses and requests to the memory to provide inputs (a third command) and receive outputs [0010-0011] [0063-0069] [0086] [0120]).
Regarding claim 10:
The device of claim 9 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the controller is further configured to execute the third command to perform the operation with the memory after the host is enabled to access the memory via the test pad (by teaching that after the signals (460) from the test pads (435) are connected to the memory (415) with the switching component (450), the host device (425) may perform diagnostic accesses and requests to the memory to provide inputs (a third command) and receive outputs [0010-0011] [0063-0069] [0086] [0120]).
Regarding claim 11:
The device of claim 10 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the controller is further configured to provide, to the host, test data associated with the memory that results from the operation to determine whether the memory is operating in a manner as expected (by teaching that after the signals (460) from the test pads (435) are connected to the memory (415) with the switching component (450), the host device (425) may perform diagnostic accesses and requests to the memory to provide inputs (a third command) and receive outputs to verify operation of the memory device (to determine whether the memory is operating in a manner as expected) [0010-0011] [0063-0069] [0086] [0120]).
Regarding claim 12:
The device of claim 1 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the controller is further configured to disconnect the test pad from the memory after toggling the reserved byte (by teaching that depending on the stored value of the bit, the switching component (450) may select the diagnostic path from the test pads (435) or the normal path from the controller, such that when the value of the bit no longer indicates the diagnostic path after the stored value is written by the host (after toggling the reserved byte), the diagnostic path from the test pads may be isolated (disconnected from the memory) [Abstract] [0014-0015] [0030] [0069-0071] [0125]).
Regarding claim 15:
The system of claim 13 is made obvious by Cariello-Alfano.
Cariello further discloses, wherein the controller is further configured to authenticate the host before allowing the secure storage location to be written with a value allowing access through the test pads (by teaching that before the value of the secure memory location can be written, the host is authenticated [0014] [0030] [0074]).
Cariello does not explicitly disclose, but Mendes teaches to receive a second command from the host to perform authentication associated with accessing the non-volatile memory (by teaching that a host (120) may send an authentication request (i.e. second command) with an authentication key (604) to a memory sub-system (110) [Fig. 6]. The authentication key may be a public key that corresponds to a private key held by the host so the memory sub-system can ensure the signature of the host is valid and was created by the host system [0055]. The authentication request may be part of an authentication process that determines whether a host (120) is able to access a memory subsystem (110) through a debug port according to an identified privilege level corresponding to the received authentication key [Fig. 6]. Depending on the determined level of privilege, the host is sent a privilege key by the memory as part of an authentication response (606). The authenticated host may then send the privilege key with a request to enable the debug port or to access the debug information [Fig. 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access or debug information as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Regarding claim 16:
The system of claim 15 is made obvious by Cariello-Alfano-Mendes.
Cariello further discloses, wherein the controller is further configured to enable the host to issue the first command to modify the reserved byte (i.e., the secure lock bytes of the flash memory as taught by Alfano) by teaching that only an authenticated host may send the command to modify the secure value to enable access to the memory device by the test pads [0014] [0030] [0074]).
Cariello does not explicitly disclose, but Mendes teaches that the authentication procedure includes the controller being configured to transmit a response code to the host in response to the second command that enables the host to request debug access through the debug port (by teaching that a host (120) may send an authentication request (i.e. second command) with an authentication key (604) to a memory sub-system (110) [Fig. 6]. The authentication key may be a public key that corresponds to a private key held by the host so the memory sub-system can ensure the signature of the host is valid and was created by the host system [0055]. The authentication request may be part of an authentication process that determines whether a host (120) is able to access a memory subsystem (110) through a debug port according to an identified privilege level corresponding to the received authentication key [Fig. 6]. Depending on the determined level of privilege, the host is sent a privilege key by the memory as part of an authentication response (606). The authenticated host may then send the privilege key with a request to enable the debug port or to access the debug information [Fig. 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified authentication of the host as taught by Cariello to include the host sending an authentication key for authentication by the memory device, which may respond with a privilege key corresponding to the authentication key for future requests by the host for debug port access (i.e., to modify the value stored in secure memory that enables the test pads as taught by Cariello) or debug information as taught by Mendes.
One of ordinary skill in the art would have been motivated to make this modification because it ensures that only authenticated entities are granted access, and only the amount of access to which the corresponding host system is entitled as taught by Mendes in [0055].
Conclusion
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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