DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 14 are objected to because of the following informalities:
Regarding claim 1, the limitations “the accumulated plurality of samples” should be amended to read ---an accumulated plurality of samples---.
Regarding claim 14, the limitations “wherein CIC filter of claim 4” should be amended to read ---wherein the CIC filter---.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitations “the demodulator”, “the SDM”, “the second integrator”, “the first and second integrators”, and “the single comb circuit”. There is insufficient antecedent basis for these limitations in the claim.
Claim 18 recites the limitation “the CIC filter”. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitations “the integrated circuit” and “the receive electrode”. There is insufficient antecedent basis for these limitations in the claim.
Claims 19-20 are dependent upon claim 17 and inherit the rejection under 35 U.S.C. 112(b).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 4 and 7-8 of U.S. Patent No. 12,360,634 in view of Ogirko (US 2021/0226626) and YU (US 2020/0266800).
Below is a comparison between present claim 1 and patented 1.
Present claim 1
Patented claim 1
A cascaded integrator-comb (CIC) filter comprising: a first integrator for receiving a plurality of samples from an analog-to-digital converter, the first integrator having a first register and a first summer; a second integrator arranged in a cascaded configuration with the first integrator, the second integrator having a second register and a second summer; and a comb circuit coupled to an output of the second integrator, the comb circuit to generate a measured amplitude bitstream from the accumulated plurality of samples on the second integrator.
An integrated circuit comprising: a sigma-delta modulator (SDM) coupled to a receive electrode, which is selectively coupled to multiple unit cell sensors; a demodulator coupled directly to the SDM, the demodulator to generate a multibit digital signal by demodulating a digital pulse density modulated (PDM) signal received from the SDM, wherein the demodulating comprises multiplying digitized cosine values with the digital PDM signal; and
a cascaded integrator-comb (CIC) filter coupled to the demodulator, the CIC filter comprising: a first integrator and a second integrator cascaded together and to accumulate, at the second integrator, a plurality of samples of the multibit digital signal; and a single comb circuit coupled to the second integrator, the single comb circuit to generate a measured amplitude bitstream from the accumulated samples.
As can be seen above, the main difference between claims is that patented claim 1 fail to teach wherein the sigma-delta modulator (SDM) is an analog-to-digital converter, the first integrator has a first register and a first summer and the second integrator has a second register and a second summer.
However, Ogirko discloses a sensing device (Fig. 5; [0039], e.g., a touch system 500) comprising:
a sigma-delta modulator (SDM) is an analog-to-digital converter for converting a signal from a touch sensor into a digital value (Fig. 4A; [0029], [0041], e.g., the accumulated sigma-delta ADC 400 converts a current or charge from a touch sensor into a digital value. The accumulated sigma-delta ADC includes a sigma-delta modulator).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Ogirko in the invention as taught by patented claim 1 for receiving a plurality of samples of a digital signal from a sigma-delta ADC by using a first integrator in order to accumulate the plurality of samples at a second integrator.
patented claim 1 in view of Ogirko does not specifically disclose wherein the first integrator has a first register and a first summer and the second integrator has a second register and a second summer.
However, YU discloses a CIC filter (Fig. 3; [0021], e.g., 300) comprising:
a first integrator having a first register and a first summer (e.g., integrator 120A has a first adder 305A and a first register 310A); and a second integrator arranged in a cascaded configuration with the first integrator (e.g., a second integrator 120X), the second integrator having a second register and a second summer (e.g., a second register 310X and a second summer 305X).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of YU in the invention of patented claim 1 in view of Ogirko for including a first register and a first summer in a first integrator and a second register and a second summer in a second integrator in order to add a received signal to an output of their respective register and store the added signal to their respect register for addition during a next clock cycle (see [0022] of YU).
Regarding claim 2, patented claim 1 in view of Ogirko and YU further discloses the CIC filter of claim 1, wherein the plurality of samples are digital values representative of at least one capacitance formed an at intersection of a transmit electrode and a receive electrode (Ogirko, Fig. 5; [0039], e.g., digital output data of the ADC 512 representative of a mutual capacitance formed at intersection of a transmit electrode TX and a receive electrode RX).
Regarding claim 3, patented claim 1 in view of Ogirko and YU further discloses further discloses the CIC filter of claim 2, where the first integrator is for receiving the plurality of samples from the analog-to-digital converter coupled to the receive electrode (Ogirko, Fig. 5; [0039], e.g., receive the plurality of samples from the ADC 512 coupled to the receive electrode RX).
Claim 4 is similarly rejected over patented claim 2 in view of Ogirko and YU.
Claim 5 is similarly rejected over patented claim 2 in view of Ogirko and YU.
Claim 6 is similarly rejected over patented claim 4 in view of Ogirko and YU.
Claim 7 is similarly rejected over patented claim 7 in view of Ogirko and YU.
Claim 8 is similarly rejected over patented claim 8 in view of Ogirko and YU.
Claim 9 is similarly rejected over patented claim 1 in view of Ogirko and YU.
Claim 10 is similarly rejected over patented claim 1 in view of Ogirko and YU.
Claim 11 is similarly rejected over patented claim 2 in view of Ogirko and YU.
Claim 12 is similarly rejected over patented claim 2 in view of Ogirko and YU.
Claim 13 is similarly rejected over patented claim 4 in view of Ogirko and YU.
Claim 14 is similarly rejected over patented claim 7 in view of Ogirko and YU.
Claim 15 is similarly rejected over patented claim 8 in view of Ogirko and YU.
Claim 16 is similarly rejected over patented claim 7 in view of Ogirko and YU.
Claims 17-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-21 of U.S. Patent No. 12,360,634 in view of Ogirko (US 2021/0226626).
Below is a comparison between present claim 17 and patented 17.
Present claim 17
Patented claim 17
A method for measuring a capacitance on a unit cell sensor,
the method comprising: generating, by the demodulator, a multibit digital signal by demodulating a digital pulse density modulated (PDM) signal received from the SDM, wherein the demodulating comprises multiplying digitized cosine values with the digital PDM signal; accumulating, at the second integrator, using the first and second integrators, a plurality of samples of the multibit digital signal; and generating, by the single comb circuit, a measured amplitude bitstream from the accumulated samples.
A method of operating an integrated circuit comprising a sigma-delta modulator (SDM) selectively coupled to a receive electrode, a demodulator coupled directly to the SDM, and a cascaded integrator-comb (CIC) filter coupled to the demodulator and comprising cascaded first and second integrators and a single comb circuit,
the method comprising: generating, by the demodulator, a multibit digital signal by demodulating a digital pulse density modulated (PDM) signal received from the SDM, wherein the demodulating comprises multiplying digitized cosine values with the digital PDM signal; accumulating, at the second integrator, using the first and second integrators, a plurality of samples of the multibit digital signal; and generating, by the single comb circuit, a measured amplitude bitstream from the accumulated samples.
As can be seen, the main difference between claims is that patented claim 17 fails to teach a method for measuring a capacitance on a unit cell sensor.
However, Ogirko discloses a method for measuring a capacitance on a unit cell sensor (Fig. 1; [0018], e.g., a capacitance on a touch sensor 102), the method comprising: generating, by ae demodulator (e.g., demodulator 108), a multibit digital signal by demodulating a digital pulse density modulated (PDM) signal received from a SDM (e.g., generate a multibit digital signal by demodulating bitstream 105 received from a sigma-delta modulator 104), wherein the demodulating comprises multiplying digitized cosine values with the digital PDM signal ([0025], e.g., demodulate the sigma-delta modulator's bit stream by multiplying the bitstream with cosine data. The cosine data can be multiplied by +1 and −1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Ogirko in the invention as taught by patented claim 17 for measuring a capacitance on a unit cell sensor in order to detect the presence and location of an object within a touch area of a touch sensor.
Claim 18 is similarly rejected over patented claim 18 in view of Ogirko and Huang.
Claim 19 is similarly rejected over patented claim 19 in view of Ogirko and Huang.
Claim 20 is similarly rejected over patented claim 20 in view of Ogirko and Huang.
Claim 21 is similarly rejected over patented claim 21 in view of Ogirko and Huang.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 12,159,007) in view of YU (US 2020/0266800).
Regarding claim 1, Huang discloses a cascaded integrator-comb (CIC) filter (Figs 5B and 5D, col. 25, lines 11-27; e.g., the first decimation filter 551 is a cascaded integrator-comb (CIC)) comprising:
a first integrator (e.g., the integrator stages 558 comprise a first integrator) for receiving a plurality of samples from an analog-to-digital converter (e.g., digital output data of ADC 516), the first integrator having a first summer (e.g., first addition circuit 564);
a second integrator arranged in a cascaded configuration with the first integrator, the second integrator having a second summer (e.g., the integrator stages 558 comprise a second integrator which includes second addition circuit 564); and
a comb circuit coupled to an output of the second integrator (e.g., the comb states 559 comprises a comb circuit), the comb circuit to generate a measured amplitude bitstream from the accumulated plurality of samples on the second integrator (Fig. 5B; col. 24, lines 34-47, e.g., generate and output a measure amplitude digital output data to a touch and display IC 212).
Huang does not specifically disclose wherein the first integrator includes a first register and the second integrator includes a second register.
However, YU discloses a CIC filter (Fig. 3; [0021], e.g., 300) comprising:
a first integrator having a first register and a first summer (e.g., integrator 120A has a first adder 305A and a first register 310A); and a second integrator arranged in a cascaded configuration with the first integrator (e.g., a second integrator 120X), the second integrator having a second register and a second summer (e.g., a second register 310X and a second summer 305X).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of YU in the invention of Huang for including a first register in a first integrator and a second register in a second integrator in order to store added signals for a next clock cycle (see [0022] of YU).
Regarding claim 2, Huang further discloses the CIC filter of claim 1, wherein the plurality of samples are digital values representative of at least one capacitance formed an at intersection of a transmit electrode and a receive electrode (Fig. 5B; col. 5, lines 66-67, col. 6, lines 1-30; col. 24, lines 34-47, e.g., digital output data of the ADC 516 representative of a mutual capacitance formed at intersection of a drive line and a sense line).
Regarding claim 3, Huang further discloses the CIC filter of claim 2, where the first integrator is for receiving the plurality of samples from the analog-to-digital converter coupled to the receive electrode (Figs 5A-5B and 5D, e.g., the first integrator of the integrator stages 558 (e.g., 551) receives the digital output data from the ADC 516 coupled to the receive electrode (e.g., the sense line)).
Claim(s) 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ogirko (US 2021/0226626) in view of Huang et al. (US 12,159,007), and further in view of YU (US 2020/0266800).
Regarding claim 9, Ogirko discloses a sensing device (Fig. 5; [0039], e.g., a touch system 500) comprising:
a receive electrode selectively coupled to multiple unit cell sensors ([0039], e.g., a receive electrode RX is selectively coupled to multiple unit cell sensors via a multiplex circuit 510);
an analog front end (AFE) for converting a signal received on the receive electrode to at least one digital bitstream ([0023], [0029], [0039], e.g., an accumulated sigma-delta converter 512 converts a current or charge received on the receive electrode RX to digital bitstream); and
a decimator (Fig. 1; [0018], e.g., decimator 114).
Ogirko does not specifically disclose a cascaded integrator-comb (CIC) filter comprising:
a first integrator for receiving the at least one digital bitstream, the first integrator having a first register and a first summer,
a second integrator arranged in a cascaded configuration with the first integrator, the second integrator having a second register and a second summer, and
a comb circuit coupled to an output of the second integrator, the comb circuit to generate a measured amplitude bitstream from an accumulated plurality of samples of the digital bitstream on the second integrator.
However, Huang discloses a touch system (Fig. 2, e.g., a touch system) comprising a cascaded integrator-comb (CIC) filter (Figs 5B and 5D, col. 25, lines 11-27; e.g., the first decimation filter 551 is a cascaded integrator-comb (CIC)) comprising:
a first integrator (e.g., the integrator stages 558 comprise a first integrator) for receiving at least one digital bitstream from an analog-to-digital converter (col. 23, lines 20-21, e.g., ADC 516 can be a delta-sigma ADC), the first integrator having a first summer (e.g., first addition circuit 564);
a second integrator arranged in a cascaded configuration with the first integrator, the second integrator having a second summer (e.g., the integrator stages 558 comprise a second integrator which includes a second addition 564); and
a comb circuit coupled to an output of the second integrator (e.g., the comb circuit 559), the comb circuit to generate a measured amplitude bitstream from the accumulated plurality of samples on the second integrator (Fig. 5B; col. 24, lines 34-47, e.g., generate and output a measure amplitude digital output data to a touch and display IC 212).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of Huang in the invention of Ogirko for implement a decimator with a cascaded integrator-comb (CIC) filter in order to filter and downsample digital output data of ADC for touch processing.
Ogirko in view of Huang does not specifically disclose wherein the first integrator includes a first register and the second integrator includes a second register.
However, YU discloses a CIC filter (Fig. 3; [0021], e.g., 300) comprising:
a first integrator having a first register and a first summer (e.g., integrator 120A has a first adder 305A and a first register 310A); and a second integrator arranged in a cascaded configuration with the first integrator (e.g., a second integrator 120X), the second integrator having a second register and a second summer (e.g., a second register 310X and a second summer 305X).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the teachings of YU in the invention of Ogirko in view of Huang for including a first register in a first integrator and a second register in a second integrator in order to store added signals for a next clock cycle (see [0022] of YU).
Regarding claim 10, Ogirko further discloses the sensing device of claim 9, wherein the at least one digital bitstream is representative of a capacitance of first unit cell sensor of the multiple unit cell sensors (Fig. 1; [0018], [0023], e.g., a digital bitstream represents a capacitance of touch sensor 102).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tanaka et al. (US 2018/0113534) discloses a sensing system comprising: a delta-sigma ADC, a demodulator and a digital filter comprising an integrator and a single comb circuit.
Wang (US 2025/00038763) discloses a cascaded integrator comb (CIC) filter comprising a first integrator having a first register and a first summer, a second integrator having a second register and a second summer and two comb filter circuits.
Cappello (US 2023/0017433) discloses a CIC filter comprises a single integrator and a single comb.
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/HONG ZHOU/Primary Examiner, Art Unit 2629