DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent/Application No. 18/582,926, patented as US patent 12,367,156..
Although the conflicting claims are not identical, they are not patentably distinct because the instant claims merely recite an obvious variation of the invention claimed in Application No. 18/582,926.
Specifically, claim 1 of the instant application recites storing, for each logical-to-physical (L2P) entry, a block number and page table index corresponding to a physical location and storing, for each physical-to-logical (P2L) mapping data structure identified by the page table index, logical addresses corresponding to physical addresses. Parent claim 1 recites substantially the same L2P/P2L mapping architecture in the context of performing a memory access operation, including identifying a P2L data structure using an L2P entry indexed by a logical address and searching the identified P2L data structure to translate the logical address to a physical address. The instant claims merely relocate structural aspects of the mapping organization into an independent claim while moving the memory access functionality into dependent claim 2. Such redistribution of limitations among claims does not render the claimed invention patentably distinct.
Instant claim 2 recites receiving a memory access request, identifying a P2L data structure based on an L2P entry indexed by the logical address, searching the P2L data structure for a matching logical address, and performing the memory access operation using the translated physical address. These limitations correspond directly to the subject matter already recited in parent claim 1.
Likewise, instant claims 3 and 4 respectively correspond to parent claims 6 and 7 by reciting searching the P2L data structure in reverse order and partitioning the P2L data structure into multiple portions for parallel reverse traversal.
Instant claims 5-7 recite determining whether entries of a P2L data structure contain a predetermined value, correlating the P2L entry with a corresponding L2P entry, performing a media management operation using the associated physical address, and replacing entries having been processed with the predetermined value. These limitations merely apply the same L2P/P2L translation architecture already claimed in the parent application to a media-management operation. Applying the previously claimed address translation mechanism during maintenance or media-management operations would have been an obvious variation to one of ordinary skill in the art because both sets of claims employ the identical mapping structures and translation relationships to locate physical addresses within the same memory system.
Independent method claim 8 and computer-readable medium claim 15 similarly correspond to parent independent claims 8 and 15, respectively, while their dependent claims correspond to the respective dependent claims of the parent application in substantially the same manner discussed above. The additional media-management limitations of claims 12-14 and 19-20 likewise constitute obvious variations of the previously claimed mapping architecture.
Accordingly, the claims of the instant application do not define a patentably distinct invention over the claims of Application No. 18/582,926. The claimed subject matter merely reorganizes claim scope, changes claim dependency, and applies the same L2P/P2L mapping framework to a closely related operational context, all of which would have been obvious to a person of ordinary skill in the art.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 1 recites a system with the following allowable subject matter: “for each entry of a logical-to-physical (L2P) data structure, storing, in a respective entry associated with a logical address, a block number and a page table index corresponding to a physical location on the non-volatile memory device;”
Closest prior art Choi [US 2019/0138454] appears to teach a non-volatile memory device generate the first mapping information L2P and the second mapping information P2L corresponding to an operation of storing the write data, and manage the first mapping information L2P and the second mapping information P2L as tables.
Johnson [US 2019/0130102] appears to teach page tables typically operate based on deconstructing a virtual address into a page table index that is used to locate an appropriate logical/virtual to physical address mapping.
Lin [US 2022/0214808] appears to teach each logical address of the L2P mapping table has a fixed field, which is sorted according to the lowest to highest (or highest to lowest) logical address.
However, the prior arts alone or in combination do not appear to teach or fairly suggest each L2P table entry is indexed by a respective logical address and comprises a block number and a page table index associated with a physical-to-logical (P2L) data structure of a plurality of P2L data structures.
Based on this rationale, claim 1 and its dependent claims 2-7 are considered to contain allowable subject matter.
Independent claim 8 recites a method with the following allowable subject matter: “for each entry of a logical-to-physical (L2P) data structure, storing, in a respective entry associated with a logical address, a block number and a page table index corresponding to a physical location on a non-volatile memory device;”
Closest prior art Choi [US 2019/0138454] appears to teach a non-volatile memory device generate the first mapping information L2P and the second mapping information P2L corresponding to an operation of storing the write data, and manage the first mapping information L2P and the second mapping information P2L as tables.
Johnson [US 2019/0130102] appears to teach page tables typically operate based on deconstructing a virtual address into a page table index that is used to locate an appropriate logical/virtual to physical address mapping.
Lin [US 2022/0214808] appears to teach each logical address of the L2P mapping table has a fixed field, which is sorted according to the lowest to highest (or highest to lowest) logical address.
However, the prior arts alone or in combination do not appear to teach or fairly suggest each L2P table entry is indexed by a respective logical address and comprises a block number and a page table index associated with a physical-to-logical (P2L) data structure of a plurality of P2L data structures.
Based on this rationale, claim 8 and its dependent claims 9-14 are considered to contain allowable subject matter.
Independent claim 15 recites a computer program product with the following allowable subject matter: “for each entry of a logical-to-physical (L2P) data structure, storing, in a respective entry associated with a logical address, a block number and a page table index corresponding to a physical location on a non-volatile memory device;”
Closest prior art Choi [US 2019/0138454] appears to teach a non-volatile memory device generate the first mapping information L2P and the second mapping information P2L corresponding to an operation of storing the write data, and manage the first mapping information L2P and the second mapping information P2L as tables.
Johnson [US 2019/0130102] appears to teach page tables typically operate based on deconstructing a virtual address into a page table index that is used to locate an appropriate logical/virtual to physical address mapping.
Lin [US 2022/0214808] appears to teach each logical address of the L2P mapping table has a fixed field, which is sorted according to the lowest to highest (or highest to lowest) logical address.
However, the prior arts alone or in combination do not appear to teach or fairly suggest each L2P table entry is indexed by a respective logical address and comprises a block number and a page table index associated with a physical-to-logical (P2L) data structure of a plurality of P2L data structures.
Based on this rationale, claim 15 and its dependent claims 16-20 are considered to contain allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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