CTNF 19/251,072 CTNF 90177 DETAILED ACTION This office action is in response to an application filed 6/26/2025, wherein claims 1-5 are pending and being examined. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) was submitted on 6/26/2025, 8/27/2025, 12/10/2025, 1/30/2026. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-5 of U.S. Patent No. 12,028,513 . Although the claims at issue are not identical, they are not patentably distinct from each other because of the following . Instant Application U.S. Patent No. 12,028,513 1. An encoder comprising: 1. An encoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, when an intra block copy (IBC) mode is used in the generating of the prediction image of the current block, the circuitry: in the updating of the HMVP table, when an intra block copy (IBC) mode is used in the generating of the prediction image of the current block, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size, wherein skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size. the size of the current block is defined by a width multiplied by a height of the current block . Claim 1 of US Patent No. 12,028,513 does not explicitly disclose “ the size of the current block is defined by a width multiplied by a height of the current block .” However the examiner takes official notice it is unquestionably well-known in the art that the size of a current block in video coding is defined by the width of the current block multiplied by the height of the current block. That is, in the art of video encoding and decoding, blocks are known to have a set size that is defined by a width of the block times the height of the block, in units of pixels. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to define a size of a current block by a width multiplied by a height, as unquestionably well-known in the art, as the current block size of claim 1 of US Patent No. 12,028,513 in order to use block sizes of standard size and shape, which allows for proper compression/decompression of the video data. In regard to claim 2, this claim is drawn to a decoder corresponding to the decoder of claim 2 of U.S. Patent No. 12,028,513, wherein claim 2 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 3 , this claim is drawn to an encoding method corresponding to the encoding method of claim 3 of U.S. Patent No. 12,028,513, wherein claim 3 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 4 , this claim is drawn to an decoding method corresponding to the decoding method of claim 4 of U.S. Patent No. 12,028,513, wherein claim 4 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 5 , this claim is drawn to a non-transitory medium storing a bitstream corresponding to the non-transitory medium storing a bitstream of claim 5 of U.S. Patent No. 12,028,513, wherein claim 5 is therefore rejected for the same reasons noted in the rejection of claim 1 . 08-34 AIA Claim s 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-5 of U.S. Patent No. 12,395,626 . Although the claims at issue are not identical, they are not patentably distinct from each other because of the following . Instant Application U.S. Patent No. 12,395,626 1. An encoder comprising: 1. An encoder comprising: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: circuitry; and memory coupled to the circuitry, wherein in operation, the circuitry: generates a prediction image of a current block to be processed, using a first motion vector; and generates a prediction image of a current block to be processed, using a first motion vector; and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and updates a history based motion vector predictor (HMVP) table using a first candidate having the first motion vector, the HMVP table storing, in a first in first out (FIFO) method, a plurality of second candidates each having a second motion vector used for a processed block, and in the updating of the HMVP table, when an intra block copy (IBC) mode is used in the generating of the prediction image of the current block, the circuitry: in the updating of the HMVP table, when an intra block copy (IBC) mode is used in the generating of the prediction image of the current block, the circuitry: determines whether a size of the current block is less than or equal to a threshold size; and determines whether a size of the current block is less than or equal to a threshold size; and skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size, wherein skips the updating of the HMVP table when the size of the current block is determined to be less than or equal to the threshold size, wherein the size of the current block is defined by a width multiplied by a height of the current block . the threshold size is equal to 16 pixels. Claim 1 of US Patent No. 12,395,626 does not explicitly disclose “ the size of the current block is defined by a width multiplied by a height of the current block .” However the examiner takes official notice it is unquestionably well-known in the art that the size of a current block in video coding is defined by the width of the current block multiplied by the height of the current block. That is, in the art of video encoding and decoding, blocks are known to have a set size that is defined by a width of the block times the height of the block, in units of pixels. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to define a size of a current block by a width multiplied by a height, as unquestionably well-known in the art, as the current block size of claim 1 of US Patent No. 12,395,626 in order to use block sizes of standard size and shape, which allows for proper compression/decompression of the video data. In regard to claim 2, this claim is drawn to a decoder corresponding to the decoder of claim 2 of U.S. Patent No. 12,395,626, wherein claim 2 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 3 , this claim is drawn to an encoding method corresponding to the encoding method of claim 3 of U.S. Patent No. 12,395,626, wherein claim 3 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 4 , this claim is drawn to an decoding method corresponding to the decoding method of claim 4 of U.S. Patent No. 12,395,626, wherein claim 4 is therefore rejected for the same reasons noted in the rejection of claim 1. In regard to claim 5 , this claim is drawn to a non-transitory medium storing a bitstream corresponding to the non-transitory medium storing a bitstream of claim 5 of U.S. Patent No. 12,395,626, wherein claim 5 is therefore rejected for the same reasons noted in the rejection of claim 1 . Allowable Subject Matter Claims 1-5 would be allowable if terminal disclaimers are filed to overcome the double patenting rejections noted herein. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xu et al. (US 10,440,378) – Discloses decoding, a current block from the plurality of blocks using an entry from a history motion vector (HMVP) buffer [Abstract], wherein processing circuitry is configured to update the HMVP buffer with a motion vector of the decoded current block [Col 3, lines 12-45]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to REBECCA A VOLENTINE whose telephone number is (571)270-7261. The examiner can normally be reached Monday-Friday 9am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joe Ustaris can be reached at (571)272-7383. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REBECCA A VOLENTINE/Primary Examiner, Art Unit 2483 May 26, 2026 Application/Control Number: 19/251,072 Page 2 Art Unit: 2483 Application/Control Number: 19/251,072 Page 3 Art Unit: 2483 Application/Control Number: 19/251,072 Page 4 Art Unit: 2483 Application/Control Number: 19/251,072 Page 5 Art Unit: 2483 Application/Control Number: 19/251,072 Page 6 Art Unit: 2483 Application/Control Number: 19/251,072 Page 7 Art Unit: 2483 Application/Control Number: 19/251,072 Page 8 Art Unit: 2483
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