DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 1:
The term “the first control portion” in line 6 of claim 1 is followed by the function “to control” without reciting sufficient structure for performing the function in the claims. The corresponding structure is disclosed in the specification as element 10 in at least paragraphs [0175] and [0127] and the structure is illustrated as having multiple transistors and capacitors in figure 20.
The term “the second control portion” in line 9 of claim 1 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims. The structure is disclosed in the specification as element 20 in at least paragraph [0134] and the structure is illustrated as having multiple transistors and capacitors in figure 20.
The term “first control unit” in line 12 of claim 1 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims for the term “first control unit”. The structure is disclosed in the specification as element 21 in at least paragraphs [0107] and [0118] and the structure is illustrated as having a transistor in figure 20.
The term “second control unit” in line 14 of claim 1 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims for the term “second control unit”. The structure is disclosed in the specification as element 22 in paragraphs [0118] and [0119] and the structure is illustrated as having multiple transistors and a capacitor in figure 20.
Claim 20:
The term “the first control portion” in line 6 of claim 20 is followed by the function “to control” without reciting sufficient structure for performing the function in the claims. The corresponding structure is disclosed in the specification as element 10 in at least paragraphs [0175] and [0127] and the structure is illustrated as having multiple transistors and capacitors in figure 20.
The term “the second control portion” in line 9 of claim 20 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims. The structure is disclosed in the specification as element 20 in at least paragraph [0134] and the structure is illustrated as having multiple transistors and capacitors in figure 20.
The term “first control unit” in line 12 of claim 20 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims for the term “first control unit”. The structure is mentioned in the specification as element 21 in paragraph [0118] and the structure is shown as having a transistor in figure 20.
The term “second control unit” in line 14 of claim 20 is followed by the function “to receive” without reciting sufficient structure for performing the function in the claims for the term “second control unit”. The structure is disclosed in the specification as element 22 in paragraphs [0118] and [0119] and the structure is illustrated as having multiple transistors and a capacitor in figure 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 20 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,367,818 in view of Lai (U.S. Pub. No. 2022/0076618).
Current application 19/251,232
Patent No. 12,367,818
1. A display panel, comprising: a driver circuit, comprising shift registers with N stages and being cascaded with each other, wherein N≥2; wherein a shift register of the shift registers comprises a first control portion and a second control portion; the first control portion is configured to control a first output signal, wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers, and 1≤i≤N, 1≤j≤N; the second control portion is configured to at least receive the first output signal and a frequency control signal, and control a second output signal; and
1. A display panel, comprising: a driver circuit, comprising shift registers with N stages and being cascaded with each other, wherein N≥2; wherein a shift register of the shift registers comprises a first control portion and a second control portion; the first control portion is configured to control a first output signal, wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers, and 1≤i≤N, 1≤j≤N; the second control portion is configured to at least receive the first output signal and a frequency control signal, and control a second output signal; and
control a second output signal; and wherein the second control portion comprises a first control unit and a second control unit; the first control unit is configured to at least receive the first output signal and the frequency control signal, and control a signal of a first node; and the second control unit is configured to at least receive the signal of the first node and control the second output signal.
See the secondary reference
20. A display device, comprising
See the secondary reference
a display panel, wherein the display panel comprises: a driver circuit, comprising shift registers with N stages and being cascaded with each other, wherein N≥2; wherein a shift register of the shift registers comprises a first control portion and a second control portion; the first control portion is configured to control a first output signal, wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers, and 1≤i≤N, 1≤j≤N; the second control portion is configured to at least receive the first output signal and a frequency control signal, and control a second output signal; and
1. A display panel, comprising: a driver circuit, comprising shift registers with N stages and being cascaded with each other, wherein N≥2; wherein a shift register of the shift registers comprises a first control portion and a second control portion; the first control portion is configured to control a first output signal, wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers, and 1≤i≤N, 1≤j≤N; the second control portion is configured to at least receive the first output signal and a frequency control signal, and control a second output signal; and
wherein the second control portion comprises a first control unit and a second control unit; the first control unit is configured to at least receive the first output signal and the frequency control signal, and control a signal of a first node; and the second control unit is configured to at least receive the signal of the first node and control the second output signal.
See the secondary reference
The secondary reference of Lai (U.S. Pub. No. 2022/0076618) teaches the limitation of claim 1 below that is not covered by the Patent No. 12,367,818. The secondary limitation of Lai teaches control a second output signal (the circuit 201 of the second control portion controls a signal at node N4, [0035], lines 36-37, that is being applied to the circuit 203, Fig. 6); and
wherein the second control portion (20) comprises a first control unit (Fig. 6, 201) and a second control unit (Fig. 6, 203);
the first control unit (201) is configured to at least receive the first output signal and the frequency control signal (Fig. 6 clearly shows that the unit 201 receives the first output signal via node N3 by the transistor M1’s source terminal and receives the frequency control signal CRL via the gate terminal of transistor M1), and control a signal of a first node (first node is N4, [0035], lines 24-27); and
the second control unit (203) is configured to at least receive the signal of the first node (signal of node N4) and control the second output signal (controlling the OUT signal shown in Fig. 15, [0054], lines 14-16).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the shift register structure of Lia to the patent No. 12,367,818 because solve the problem that the shift register in the display panel cannot satisfy different voltage requirements of the pixel circuit for different signals. [0005].
The secondary reference of Lai (U.S. Pub. No. 2022/0076618) teaches the limitation of claim 20 below that is not covered by the Patent No. 12,367,818. The secondary limitation of Lai teaches a display device (90, Fig. 18) having a display panel (91) and control a second output signal (the circuit 201 of the second control portion controls a signal at node N4, [0035], lines 36-37, that is being applied to the circuit 203, Fig. 6); and
wherein the second control portion (20) comprises a first control unit (Fig. 6, 201) and a second control unit (Fig. 6, 203);
the first control unit (201) is configured to at least receive the first output signal and the frequency control signal (Fig. 6 clearly shows that the unit 201 receives the first output signal via node N3 by the transistor M1’s source terminal and receives the frequency control signal CRL via the gate terminal of transistor M1), and control a signal of a first node (first node is N4, [0035], lines 24-27); and
the second control unit (203) is configured to at least receive the signal of the first node (signal of node N4) and control the second output signal (controlling the OUT signal shown in Fig. 15, [0054], lines 14-16).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the shift register structure of Lia to the patent No. 12,367,818 because solve the problem that the shift register in the display panel cannot satisfy different voltage requirements of the pixel circuit for different signals. [0005].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (U.S. Pub. No. 2022/0076618).
As to claim 1, Lai teaches a display panel (display panel shown in Fig. 1), comprising:
a driver circuit (100), comprising shift registers with N stages (Fig. 2, there are shift registers with N number of stages) and being cascaded with each other (the ASG1 shift register is connected to shift register ASG2, shift register ASG2 is connected to shift register ASG3 and so on, therefore the shift registers are connected in a cascade formation), wherein N≥2 (there are more than two shift registers, therefore N is greater than 2);
wherein a shift register of the shift registers comprises a first control portion and a second control portion (Fig. 4 shows the shift register has a first control portion 10 and second control portion 20);
the first control portion (10) is configured to control a first output signal (first control signal outputs an N3 output signal, the signal N3 is shown in Fig. 15),
wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers (Fig. 2 shows that the first output signal N3 of the first stage (i=1) is an input signal of a second stage, wherein j=2), and 1≤i≤N, 1≤j≤N (it is true that i=1 and j=2);
the second control portion (20) is configured to at least receive the first output signal and a frequency control signal (Fig. 17 shows that the second control portion 20 receives a first output signal via node N3 and a frequency control signal CRL, [0035], line 27), and control a second output signal (the circuit 201 of the second control portion controls a signal at node N4, [0035], lines 36-37, that is being applied to the circuit 203, Fig. 6); and
wherein the second control portion (20) comprises a first control unit (Fig. 6, 201) and a second control unit (Fig. 6, 203);
the first control unit (201) is configured to at least receive the first output signal and the frequency control signal (Fig. 6 clearly shows that the unit 201 receives the first output signal via node N3 by the transistor M1’s source terminal and receives the frequency control signal CRL via the gate terminal of transistor M1), and control a signal of a first node (first node is N4, [0035], lines 24-27); and
the second control unit (203) is configured to at least receive the signal of the first node (signal of node N4) and control the second output signal (controlling the OUT signal shown in Fig. 15, [0054], lines 14-16).
As to claim 20, Lai teaches a display device (device shown in Fig. 18), comprising a display panel (display panel shown in Fig. 1), wherein the display panel comprises:
a driver circuit (100), comprising shift registers with N stages (Fig. 2, there are shift registers with N number of stages) and being cascaded with each other (the ASG1 shift register is connected to shift register ASG2, shift register ASG2 is connected to shift register ASG3 and so on, therefore the shift registers are connected in a cascade formation), wherein N≥2 (there are more than two shift registers, therefore N is greater than 2);
wherein a shift register of the shift registers comprises a first control portion and a second control portion (Fig. 4 shows the shift register has a first control portion 10 and second control portion 20);
the first control portion (10) is configured to control a first output signal (first control signal outputs an N3 output signal, the signal N3 is shown in Fig. 15),
wherein the first output signal of an i-th stage of shift register of the shift registers is an input signal of a j-th stage of shift register of the shift registers (Fig. 2 shows that the first output signal N3 of the first stage (i=1) is an input signal of a second stage, wherein j=2), and 1≤i≤N, 1≤j≤N (it is true that i=1 and j=2);
the second control portion (20) is configured to at least receive the first output signal and a frequency control signal (Fig. 17 shows that the second control portion 20 receives a first output signal via node N3 and a frequency control signal CRL, [0035], line 27), and control a second output signal (the circuit 201 of the second control portion controls a signal at node N4, [0035], lines 36-37, that is being applied to the circuit 203, Fig. 6); and
wherein the second control portion (20) comprises a first control unit (Fig. 6, 201) and a second control unit (Fig. 6, 203);
the first control unit (201) is configured to at least receive the first output signal and the frequency control signal (Fig. 6 clearly shows that the unit 201 receives the first output signal via node N3 by the transistor M1’s source terminal and receives the frequency control signal CRL via the gate terminal of transistor M1), and control a signal of a first node (first node is N4, [0035], lines 24-27); and
the second control unit (203) is configured to at least receive the signal of the first node (signal of node N4) and control the second output signal (controlling the OUT signal shown in Fig. 15, [0054], lines 14-16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lai (U.S. Pub. No. 2022/0076618) in view of Lai (U.S. 2022/0076611).
As to claim 5, Lai (‘618) teaches a frequency control signal CRL,
Lai (‘618) does not teach the structure of the first control unit,
Lai(‘611) teaches the first control unit (121, Fig. 17) comprises a first transistor (M2), a gate of the first transistor is configured to receive the first output signal (gate of transistor M2 receives the first output signal via node N3), a first electrode of the first transistor is configured to receive the frequency control signal (the first electrode of the first transistor M2 receives the signal CRL), and a second electrode of the first transistor is connected to the first node (second electrode of transistor M2 is connected to first node, which is node N4).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the shift register structure of Lai (‘611) to the shift register of Lai (‘618) because to create a display with simple structure and stable output, [0005].
As to claim 6, Lai (‘618) teaches the display panel of claim 1,
Lai (‘618) does not teach the structure of the first control unit,
Lai (‘611) teaches in a case where the first transistor is a P-type transistor (Fig. 17, the first transistor M2 is a P-type transistor), an ineffective pulse of the first output signal is a low level signal (Fig. 20, the signal N3 to turn ON the transistor M2 must be low, which is during the period T2-T5), and an effective pulse of the first output signal is a high level signal (the effective pulse of N3 is high during periods T1 and T6, Fig. 20, which will turn OFF transistor M2); or in a case where the first transistor is an N-type transistor, an ineffective pulse of the first output signal is a high level signal, and an effective pulse of the first output signal is a low level signal (there is an OR between the limitations and the first limitation is fulfilled).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the shift register structure of Lai (‘611) to the shift register of Lai (‘618) because to create a display with simple structure and stable output, [0005].
Allowable Subject Matter
Claims 2-4 and 7-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 is objected to because the prior art references do not teach the effective and ineffective pulses and how they control the display components in the limitation of in a case where the first output signal is an ineffective pulse, the first control unit is turned on; and in a case where the first output signal is an effective pulse, the first control unit is turned off.
Claim 3 is objected to because the prior art references do not teach in a case where the first output signal is an effective pulse and the frequency control signal is an effective pulse, the first control unit is turned off and an effective pulse of the frequency control signal is not transmitted to the first node.
Claim 4 is objected to because the prior art references do not teach in a case where the first output signal is an ineffective pulse and the frequency control signal is an effective pulse, the first control unit is turned on, an effective pulse of the frequency control signal is transmitted to the first node, and the second output signal is an ineffective pulse.
Claim 7 is objected to because the prior art references do not teach the structure and signals of the second control unit is configured to at least receive the first output signal, the signal of the first node, a first voltage signal and a second voltage signal, and control the second output signal; and one of the first voltage signal and the second voltage signal is a high level signal, and the other one of the first voltage signal and the second voltage signal is a low level signal.
Claim 13 is objected to because the prior art references do not teach in a case where at least part of the first output signal is an effective pulse and a time period of an effective pulse partially overlaps with a time period of an effective pulse of the frequency control signal, the second output signal is an ineffective pulse.
Claim 14 is objected to because the prior art references do not teach a frequency difference when combined with the structure mentioned in claim 1 wherein a pulse variation frequency of the first output signal is F1, and a pulse variation frequency of the second output signal is F2, wherein F1≥F2.
Claim 15 is objected to because the prior art references do not teach the time period and structure in the limitation below when combined with the structure of claim 1 wherein within at least a part of time periods that the display panel works, in case where the first output signal is an effective pulse, the second output signal is an effective pulse.
Claim 16 is objected to because the prior art references do not teach the time period and structure in the limitation below when combined with the structure of claim 1 wherein within at least a part of time periods that the display panel works, in case where the first output signal is an effective pulse, the second output signal is an ineffective pulse.
Claim 17 is objected to because the prior art references do not teach structure in the limitation below when combined with the structure of claim 1 wherein the second output signal of the driver circuit is a control signal of a preset module of the pixel circuit; in a case where the second output signal is an effective pulse, the preset module is turned on; and in a case where the second output signal is an ineffective pulse, the preset module is turned off.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lai (U.S. Pub. No. 2022/0076604) teaches a display panel and shift registers.
Feng (U.S. Pub. No. 2021/0358365) teaches a shift register.
Inquiry
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/PEGEMAN KARIMI/ Primary Examiner, Art Unit 2623