DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 24 September 2025 is in compliance with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609. Accordingly, the IDS is being considered by this Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-8, 11-17 and 20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 2, line 1, “the available units represent a programming mode” is indefinite as it is unclear how memory storage units can represent or be a depiction of a mode of programming the memory. The specification states in paragraph [291] that “each unit representing a set of the erase blocks that can be programmed in a plurality of modes”. It would be more appropriate to amend the claim to include similar language. Furthermore, “the available units” is indefinite as claim 1 teaches “a number of available units” on line 4 and “one or more the available units” on lines 7-8. It is unclear which available units are referred to as “the available units”.
Per claim 3, line 1, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 4, lines 2-3, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 6, line 1, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 8, line 2, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 11, line 1, “the available units” and “the available units representing a programming mode” are indefinite for the same reason set forth above for claim 2.
Per claim 12, line 1, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 13, line 2, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 15, line 1, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 17, line 2, “the available units” is indefinite for the same reason set forth above for claim 2.
Per claim 20, lines 1-2, “the available units” and “the available units representing a programming mode” are indefinite for the same reason set forth above for claim 2.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Yeh [Pub.No.: US 20170322727 A1] (hereinafter “Yeh”).
Independent Claims:
Per claim 1, Yeh teaches:
A storage device (see Fig. 1, memory storage apparatus 10) comprising:
a plurality of erase blocks (the physical programming units of each physical erasing unit can be construed as erase blocks; see paragraphs [0074]-[0075], physical erasing unit 410(0) includes at least the 0-th and 1-st physical programming units; see paragraph [0043], the physical programming units of the same physical erase unit may erased simultaneously, as such the physical programming units may be mapped to the claimed plurality of erase blocks); and
a storage device controller, operatively coupled to the plurality of erase blocks (see paragraph [0070], lines 1-9, memory control circuit unit 404 or memory management circuit 502), configured to:
provide, through an interface (see Fig. 4, the interconnection/interfacing between memory control circuit unit 404 and memory model 406 can be viewed as the claimed interface), a number of available units that represent a set of erase blocks of the plurality of erase blocks (see paragraphs [0054] and [0074]-[0075], physical erasing units 410(0)-410(N) are mapped to the claimed number of available units) that can be programmed in a plurality of modes having differing effective capacities (see paragraph [0070], lines 1-9, programming data into physical erasing units with different programming modes; see paragraph [0071], lines 5-9, data capacities of the physical erasing units programmed by different programming modes are also different);
receive a plurality of requests to form unit sets comprising one or more of the available units (see paragraph [0055], the memory control circuit unit 404 logically group the physical erasing units 410(0) to 410(N) into unit sets such as data area 602, spare area 604, system area 606 and replacement area 608) and configured to be programmed in one or more of the plurality of modes (see paragraph [0070], lines 1-9 for programming with different programming modes), resulting virtually addressable capacity corresponding to effective capacity for the unit sets when programmed in the one or more of the plurality of modes (see paragraphs [0054], [0060] lines 1-7 and [0062] lines 6-7, the physical storage locations are addressed logically, and the logically addressed capacities correspond to the data capacities of the physical erasing unit based on the programing mode used, see paragraph [0071], lines 1-9); and
store data into erase blocks of the one or more of the available units of the unit sets using the one or more of the plurality of modes (see paragraph [0070], lines 1-9, programming data into physical erasing units with different programming modes).
Per independent claim 10, the claim is the method performed by the storage device of claim 1. As such it is rejected on the same grounds mutatis mutandis.
Per independent claim 19, the claim is the non-transitory computer readable storage medium storing instructions which when executed causes a storage device controller to perform the same functions performed by the storage device controller of claim 1’s storage device. As such it is rejected on the same grounds mutatis mutandis.
Dependent Claims:
Per claim 2, Yeh further teaches the available units represent a programming mode applied to blocks of one or more flash die of the storage device (see paragraph [0070], lines 1-9, physical erasing units are programmed with different programming modes; see paragraph [0043], lines 1-10, the physical erasing units belong to one or more dies; see paragraph [0045] for flash memory).
Per claim 3, Yeh further teaches the available units can be operated in parallel with one another (physical erasing units 410(0)-410(N) can be grouped into a data area 602, and they can be operated in parallel when data is accessed across more than one physical erasing unit; furthermore, keeping the physical erasing units powered on at the same time is operating the physical erasing units in parallel).
Per claim 4, Yeh further teaches a request to the storage device can prevent and subsequently allow performance of storage device background operations of a particular unit of the available units (see entire paragraph [0101], entering a foreground execution mode previous the background operations, subsequently entering the background execution mode allow performance of background operations of the memory device, which comprises any particular physical erasing units 410(0)-410(N)).
Per claim 5, Yeh further teaches the storage device background operations are prevented for one or more flash dies of the particular unit (see entire paragraph [0101], entering a foreground execution mode previous the background operations; see paragraph [0043], lines 1-10, the physical erasing units belong to one or more dies; see paragraph [0045] for flash memory).
Per claim 6, Yeh further teaches the available units can be programmed with additional redundancy (see paragraph [0044], lines 1-10, the physical erasing units are programmed with redundancy bit areas).
Per claim 7, Yeh further teaches the additional redundancy comprises storing data segments using erasure codes across flash die of the storage device (see paragraph [0069], data is written with ECC code).
Per claim 8, Yeh further teaches the plurality of requests comprises one or more virtual addresses associated with one or more of the available units (see paragraph [0060], lines 1-13, paragraph [0062], lines 4-25 for logical block address/LBAs).
Per claim 9, Yeh further teaches the one or more of the plurality of modes comprises a first mode of the plurality of modes that is different than a second mode of the plurality of modes (see entire paragraph [0070], programming data into physical erasing units with different programming modes such as SLC, TLC and MLC).
Per claim 11, the claim is the method performed by the storage device of claim 2. As such it is rejected on the same grounds mutatis mutandis.
Per claim 12, the claim is the method performed by the storage device of claim 3. As such it is rejected on the same grounds mutatis mutandis.
Per claim 13, the claim is the method performed by the storage device of claim 4. As such it is rejected on the same grounds mutatis mutandis.
Per claim 14, the claim is the method performed by the storage device of claim 5. As such it is rejected on the same grounds mutatis mutandis.
Per claim 15, the claim is the method performed by the storage device of claim 6. As such it is rejected on the same grounds mutatis mutandis.
Per claim 16, the claim is the method performed by the storage device of claim 7. As such it is rejected on the same grounds mutatis mutandis.
Per claim 17, the claim is the method performed by the storage device of claim 8. As such it is rejected on the same grounds mutatis mutandis.
Per claim 18, the claim is the method performed by the storage device of claim 9. As such it is rejected on the same grounds mutatis mutandis.
Per claim 20, the claim is the non-transitory computer readable storage medium storing instructions which when executed causes a storage device controller to perform the same functions performed by the storage device controller of claim 2’s storage device. As such it is rejected on the same grounds mutatis mutandis.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
22 August 2026
Prosecution Insights