NON-FINAL OFFICE ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2020/0410354 to Zejda et al. (“Zejda”).
Zejda discloses:
1. A computing system, comprising:
a core to perform one or more workloads in an execution of a neural network (paras. [0016], [0020] – data processing units, target processor); and
a debugging module to:
receive a breakpoint configuration signal that indicates a debug event associated with the execution of the neural network (para. [0078]),
compile the neural network based on the breakpoint configuration signal to generate a compiled neural network (paras. [0021], [0069]),
provide the compiled neural network to the core (paras. [0021], [0046]),
receive an output tensor generated by the core from performing the one or more workloads using the compiled neural network (paras. [0037], [0045]), and
detect an error associated with the neural network based on the output tensor (paras. [0021], [0037]).
2. The computing system of claim 1, further comprising one or more other cores, wherein the one or more other cores and the core are to execute in parallel a plurality of workloads including the one or more workloads in the execution of the neural network (paras. [0016], [0116]).
3. The computing system of claim t, wherein the debugging module is further to transmit the output tensor to a memory (paras. [0068], [0098]).
4. The computing system of claim 3, wherein the output tensor is generated by the core using input data, wherein the debugging module is further to transmit the input data to the memory (paras. [0043], [0068], [0091]).
5. The computing system of claim 4, wherein the debugging module is further to detect the error based on the input data (paras. [0021], [0037]).
6. The computing system of claim 1, wherein the debugging module is further to halt the execution of the neural network after detecting the error (paras. [0021], [0053]).
7. The computing system of claim 6, wherein the debug event is specific to a workload in the execution of the neural network, and the debugging module is to halt the execution of the neural network by halting the workload (paras. [0021], [0053]).
Claims 8-14 are a method identical to the steps performed by the computing system of claims 1-7, and are rejected under the same rationale.
Claims 15-20 one or more non-transitory computer-readable media for performing identical steps performed by the computing system of claims 1-6, and are rejected under the same rationale.
Conclusion
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/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
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