DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 11/03/2025 and 05/11/2026 are in compliance with the provisions of 37 CFR 1.97, 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 3, 6, 9, and 10 are objected to because of the following informalities:
Claim 3: Change to “…when the fault information table is different from the first fault information table stored in the computer device, updating the fault information table [[into]] in the computer device.” (page 1).
Claim 6: Change to “6. The method according to claim 5, further comprising:…” (page 2).
Claim 9: Change to “…obtain the fault information table and a flag bit, and check the fault information table based on the flag bit; and…” (page 2).
Claim 10: Change to “…when the fault information table is different from the first fault information table stored in the computer device, update the fault information table [[into]] in the computer device.” (page 3).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the register" in various places of the claim on page 1. It is unclear as to which register is being referred to:
Claim 1: “…obtaining a fault information table, wherein the fault information table indicates a correspondence between a plurality of pieces of hardware and a register, and a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware; and…”
Claim 1: “…obtaining fault information of first hardware fed back by a register corresponding to the first hardware,…”
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2, 3, and 5-10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to (an) abstract idea(s) without significantly more.
Claims 2 (in combination with independent Claim 1) and 9 recite:
obtaining a fault information table, wherein the fault information table indicates a correspondence between a plurality of pieces of hardware and a register, and a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware; and
based on the fault information table, obtaining fault information of first hardware fed back by a register corresponding to the first hardware, wherein the fault information of the first hardware is stored in the register corresponding to the first hardware, and the first hardware is any one of the plurality of pieces of hardware.
wherein obtaining the fault information table comprises: obtaining the fault information table and a flag bit, and
checking the fault information table based on the flag bit; and
when the fault information table is successfully checked, obtaining the fault information of the first hardware fed back by the register corresponding to the first hardware.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes:
Claim 2 is a process.
Claim 9 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘checking’ limitation in # 4 above, as claimed and under broadest reasonable interpretation (BRI), is a mental process that covers performance of the limitation in the mind. For example, “checking” in the context of this claim encompasses a person evaluating data.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘obtaining’ limitations in # 1-3 and 5 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “obtaining” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
Additionally, the claims recite the following additional elements:
a computer device (Claim 7),
a management controller (Claim 7),
a processor (Claim 7),
a plurality of pieces of hardware (Claims 2 and 7),
a register (Claims 2 and 7),
a register corresponding to each piece of hardware (Claims 2 and 7),
at least one piece of hardware (Claims 2 and 7),
first hardware (Claims 2 and 7), and
a register corresponding to the first hardware (Claims 2 and 7).
These additional elements are recited at a high level of generality (i.e. as generic computer components) such that they amount to no more than components comprising mere instructions to apply an exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply an exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 1-3 and 5 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claims 3 (in combination with Claim 1) and 10 recite:
obtaining a fault information table, wherein the fault information table indicates a correspondence between a plurality of pieces of hardware and a register, and a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware; and
based on the fault information table, obtaining fault information of first hardware fed back by a register corresponding to the first hardware, wherein the fault information of the first hardware is stored in the register corresponding to the first hardware, and the first hardware is any one of the plurality of pieces of hardware.
wherein the method is applied to a computer device, and
the method further comprises: determining whether the fault information table is the same as a first fault information table stored in the computer device; and
when the fault information table is different from the first fault information table stored in the computer device, updating the fault information table into the computer device.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes:
Claim 3 is a process.
Claim 10 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘determining’ limitation in # 9 above, as claimed and under BRI, is a mental process that covers performance of the limitation in the mind. For example, “determining” in the context of this claim encompasses the person evaluating data.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘obtaining’ limitations in # 6 and 7 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “obtaining” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
In # 8 above, the claimed method is further described in the context of a mere field of use. See MPEP 2106.05(h).
The ‘updating’ limitation in # 10 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “updating” in the context of this claim encompasses mere data outputting / data manipulation. See MPEP 2106.05(g).
Additionally, the claims recite the following additional elements:
a computer device (Claim 7),
a management controller (Claim 7),
a processor (Claim 7),
a plurality of pieces of hardware (Claims 3 and 7),
a register (Claims 3 and 7),
a register corresponding to each piece of hardware (Claims 3 and 7),
at least one piece of hardware (Claims 3 and 7),
first hardware (Claims 3 and 7), and
a register corresponding to the first hardware (Claims 3 and 7).
These additional elements are recited at a high level of generality (i.e. as generic computer components) such that they amount to no more than components comprising mere instructions to apply an exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply an exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 6, 7, and 10 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
iii. Electronic recordkeeping, Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 225, 110 USPQ2d 1984 (2014) (creating and maintaining "shadow accounts"); Ultramercial, 772 F.3d at 716, 112 USPQ2d at 1755 (updating an activity log); and
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claim 5 recites:
generating a correspondence between a plurality of pieces of hardware and a register to form a fault information table, wherein a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware; and
sending the fault information table to the processor.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: a process.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘generating’ limitation in # 11 above, as claimed and under BRI, is a mental process that covers performance of the limitation in the mind. For example, “generating” in the context of this claim encompasses the person evaluating data to make a simple table using, e.g., pen and paper.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘sending’ limitation in # 12 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “sending” in the context of this claim encompasses mere data transmission. See MPEP 2106.05(d)(II) and MPEP 2106.05(g).
Additionally, the claim recites the following additional elements:
a management controller,
a computer device,
a processor,
a plurality of pieces of hardware,
a register,
a register corresponding to each piece of hardware, and
at least one piece of hardware.
These additional elements are recited at a high level of generality (i.e. as generic computer components) such that they amount to no more than components comprising mere instructions to apply an exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply an exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 12 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network).
Claims 6 and 8 recite:
based on fault information of first hardware indicated by a user, updating fault information associated with a register corresponding to the first hardware to obtain an updated correspondence, wherein the first hardware is any one of the plurality of pieces of hardware; and
sending the updated correspondence to the processor.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes:
Claim 6 is a process.
Claim 8 is a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s). The abstract idea(s) of Claims 5 and 7 is/are the same as the abstract idea(s) of Claims 6 and 8, respectively.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘updating’ limitation in # 13 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “updating” in the context of this claim encompasses mere data outputting / data manipulation. See MPEP 2106.05(g).
The ‘sending’ limitation in # 14 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “sending” in the context of this claim encompasses mere data transmission. See MPEP 2106.05(d)(II) and MPEP 2106.05(g).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
With regards to # 13 and 14 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); and
iii. Electronic recordkeeping, Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 225, 110 USPQ2d 1984 (2014) (creating and maintaining "shadow accounts"); Ultramercial, 772 F.3d at 716, 112 USPQ2d at 1755 (updating an activity log).
Claim 7 recites:
generate a correspondence between a plurality of pieces of hardware and a register to form a fault information table, wherein a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware; and
send the correspondence between the plurality of pieces of hardware and the register to the processor; and
obtain the fault information table from the management controller; and
based on the fault information table, obtain fault information of first hardware fed back by a register corresponding to the first hardware,
wherein the fault information of the first hardware is stored in the register corresponding to the first hardware, and the first hardware is any one of the plurality of pieces of hardware.
Step 1: Is the claim to a process, machine, manufacture, or composition of matter?
Yes: a machine.
Step 2A, Prong I: Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The ‘generate’ limitation in # 15 above, as claimed and under BRI, is a mental process that covers performance of the limitation in the mind. For example, “generating” in the context of this claim encompasses the person evaluating data to make a simple table using, e.g., pen and paper.
Step 2A, Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The ‘send’ limitation in # 16 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “sending” in the context of this claim encompasses mere data transmission. See MPEP 2106.05(d)(II) and MPEP 2106.05(g).
The ‘obtain’ limitations in # 17 and 18 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “obtaining” in the context of this claim encompasses mere data gathering. See MPEP 2106.05(g).
The ‘is stored’ limitation in # 19 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, “storing” in the context of this claim encompasses mere data storing / data manipulation. See MPEP 2106.05(d)(II) and MPEP 2106.05(g).
Additionally, the claim recites the following additional elements:
a computer device,
a management controller,
a processor,
a plurality of pieces of hardware,
a register,
a register corresponding to each piece of hardware,
at least one piece of hardware,
first hardware, and
a register corresponding to the first hardware.
These additional elements are recited at a high level of generality (i.e. as generic computer components) such that they amount to no more than components comprising mere instructions to apply an exception. Accordingly, these additional elements do not integrate the abstract idea(s) into a practical application because they do not impose any meaningful limits on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
As discussed above with respect to integration of the abstract idea(s) into a practical application, the aforementioned additional elements amount to no more than components comprising mere instructions to apply an exception. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept.
Additionally, with regards to # 16-19 above, per MPEP 2106.05(d)(Il), the courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
i. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network);
iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mukherjee et al. (U.S. Patent No. US 7,409,594 B2), hereinafter “Mukherjee.”
With regards to Claim 1, Mukherjee teaches:
a fault detection method, comprising:
obtaining a fault information table, wherein the fault information table indicates a correspondence between a plurality of pieces of hardware and a register, and a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; regarding, e.g., at least memory, disk drive, and processor components [a plurality of pieces of hardware]; Fig. 4; and col. 8, lines 13-48; regarding, e.g., intermediate fault information table[s] or master device fault information table[s] associated with satellite diagnosis processors [a fault information table].); and
based on the fault information table, obtaining fault information of first hardware fed back by a register corresponding to the first hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; Fig. 4; col. 8, lines 13-48; col. 3, lines 23-29; Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7; regarding, e.g., fault data from a disk read from a disk fault register.), wherein the fault information of the first hardware is stored in the register corresponding to the first hardware (Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7.), and the first hardware is any one of the plurality of pieces of hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7.).
With regards to Claim 2, Mukherjee teaches the method of Claim 1 as referenced above. Mukherjee further teaches:
wherein obtaining the fault information table comprises:
obtaining the fault information table and a flag bit, and checking the fault information table based on the flag bit (Fig. 6; col. 11, lines 63-67; and col. 12, lines 1-22.); and
when the fault information table is successfully checked, obtaining the fault information of the first hardware fed back by the register corresponding to the first hardware (Fig. 6; col. 11, lines 63-67; and col. 12, lines 1-22.).
With regards to Claim 5, Mukherjee teaches:
a fault detection method, comprising, with a management controller (Fig. 2; col. 4, lines 59-67; and col. 5, lines 1-4; regarding, e.g., satellite diagnosis processor 210.) of a computer device (Fig. 1 and col. 2, lines 42-47; regarding, e.g., system hardware chassis / shelf 102.) comprising the management controller and a processor (Fig. 1 and col. 2, lines 61-67; regarding, e.g., diagnosis processor 106.), performing steps of:
generating a correspondence between a plurality of pieces of hardware and a register to form a fault information table, wherein a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; regarding, e.g., at least memory, disk drive, and processor components [a plurality of pieces of hardware]; Fig. 4; and col. 8, lines 13-48; regarding, e.g., intermediate fault information table[s] or master device fault information table[s] associated with satellite diagnosis processors [a fault information table].); and
sending the fault information table to the processor (Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.).
With regards to Claim 7, Mukherjee teaches:
a computer device (Fig. 1 and col. 2, lines 42-47; regarding, e.g., system hardware chassis / shelf 102.), comprising a management controller (Fig. 2; col. 4, lines 59-67; and col. 5, lines 1-4; regarding, e.g., satellite diagnosis processor 210.) and a processor (Fig. 1 and col. 2, lines 61-67; regarding, e.g., diagnosis processor 106.), wherein the management controller is configured to:
generate a correspondence between a plurality of pieces of hardware and a register to form a fault information table, wherein a register corresponding to each piece of hardware is associated with fault information of at least one piece of hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; regarding, e.g., at least memory, disk drive, and processor components [a plurality of pieces of hardware]; Fig. 4; and col. 8, lines 13-48; regarding, e.g., intermediate fault information table[s] or master device fault information table[s] associated with satellite diagnosis processors [a fault information table].); and
send the correspondence between the plurality of pieces of hardware and the register to the processor (Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.); and
the processor is configured to: obtain the fault information table from the management controller (Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.); and
based on the fault information table, obtain fault information of first hardware fed back by a register corresponding to the first hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; Fig. 4; col. 8, lines 13-48; col. 3, lines 23-29; Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7; regarding, e.g., fault data from a disk read from a disk fault register.), wherein the fault information of the first hardware is stored in the register corresponding to the first hardware (Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7.), and the first hardware is any one of the plurality of pieces of hardware (Fig. 1; Fig. 2; col. 5, lines 50-67; Fig. 6; col. 10, lines 63-67; and col. 11, lines 1-7.).
With regards to Claim 9, Mukherjee teaches the device of Claim 7 as referenced above. Mukherjee further teaches:
wherein the processor is further configured to:
obtain the fault information table and a flag bit, and check the fault information table based on the flag bit (Fig. 6; col. 11, lines 63-67; and col. 12, lines 1-22.);
when the fault information table is successfully checked, obtain the fault information of the first hardware fed back by the register corresponding to the first hardware (Fig. 6; col. 11, lines 63-67; and col. 12, lines 1-22.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee, and further in view of Reza et al. (U.S. Patent No. US 10,007,585 B2), hereinafter “Reza.”
With regards to Claim 3, Mukherjee teaches the method of Claim 1 as referenced above. Mukherjee further teaches:
wherein the method is applied to a computer device (Fig. 1 and col. 2, lines 42-47; regarding, e.g., system hardware chassis / shelf 102.), and the method further comprises:
when the fault information table is different from the first fault information table stored in the computer device, updating the fault information table into the computer device (Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.).
Mukherjee does not explicitly teach:
determining whether the fault information table is the same as a first fault information table stored in the computer device in accordance with the method of Claim 1.
However, Reza teaches:
determining whether the fault information table is the same as a first fault information table stored in the computer device (Fig. 8; col. 19, lines 2-10; and col. 19, lines 22-33; regarding, e.g., determining a version mismatch of table records.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Mukherjee with the determination of table record data mismatch[es] as taught by Reza because only handling updates based on mismatching data prevents entire data sets from being needlessly overwritten, thereby improving overall efficiency of the system (Reza: col. 4, lines 44-50).
With regards to Claim 10, Mukherjee teaches the device of Claim 7 as referenced above. Mukherjee further teaches:
wherein the processor is further configured to:
when the fault information table is different from the first fault information table stored in the computer device, update the fault information table into the computer device (Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.).
Mukherjee does not explicitly teach:
determine whether the fault information table is the same as a first fault information table stored in the computer device in accordance with the device of Claim 7.
However, Reza teaches:
determine whether the fault information table is the same as a first fault information table stored in the computer device (Fig. 8; col. 19, lines 2-10; and col. 19, lines 22-33; regarding, e.g., determining a version mismatch of table records.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Mukherjee with the determination of table record data mismatch[es] as taught by Reza because only handling updates based on mismatching data prevents entire data sets from being needlessly overwritten, thereby improving overall efficiency of the system (Reza: col. 4, lines 44-50).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee, and further in view of Kawakami et al. (U.S. Patent Application Publication No. US 2022/0300288 A1), hereinafter “Kawakami.”
With regards to Claim 4, Mukherjee teaches the method of Claim 1 as referenced above. Mukherjee further teaches:
wherein the fault information table further comprises information about the register (Fig. 4; col. 8, lines 13-48; col. 8, lines 61-67; and col. 9, lines 1-3; regarding, e.g., physical fault address field data.), and the information about the register comprises a register parameter (Fig. 4; col. 8, lines 61-67; and col. 9, lines 1-3.).
Mukherjee does not explicitly teach:
a register type, a register bit width in accordance with the method of Claim 1.
However, Kawakami teaches:
a register type (Fig. 33 and ¶ 0361.), a register bit width (Fig. 33 and ¶ 0355.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Mukherjee with information such as register data type and register size as taught by Kawakami because a simple substitution of one known element (detailed fault information table entry data – Mukherjee: Fig. 4; Mukherjee: col. 8, lines 61-67; and Mukherjee: col. 9, lines 1-3) for another (register data type and register size) can be performed to obtain predictable results (providing known register data field entries for identifying and/or recording fault information).
Claims 6 and 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mukherjee, and further in view of Yadav et al. (U.S. Patent Application Publication No. US 2023/0229545 A1), hereinafter “Yadav.”
With regards to Claim 6, Mukherjee teaches the method of Claim 5 as referenced above. Mukherjee further teaches:
wherein the method further comprises:
based on fault information of first hardware, updating fault information associated with a register corresponding to the first hardware to obtain an updated correspondence, wherein the first hardware is any one of the plurality of pieces of hardware (Fig. 6; col. 10, lines 50-67; and col. 11, lines 1-13; regarding, e.g., updating a master device fault table either periodically or when more faults have been detected.); and
sending the updated correspondence to the processor (Fig. 6; col. 10, lines 50-67; col. 11, lines 1-13; Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.).
Mukherjee does not explicitly teach:
indicated by a user in accordance with the method of Claim 5.
However, Yadav teaches:
indicated by a user (Fig. 5; ¶ 0046; and ¶ 0051: “user configurable.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Mukherjee with user-configurable table data as taught by Yadav because a simple substitution of one known element (detailed fault information table entry data – Mukherjee: Fig. 4; Mukherjee: col. 8, lines 61-67; and Mukherjee: col. 9, lines 1-3) for another (user-configurable table data) can be performed to obtain predictable results (providing known register data field entries for identifying and/or recording fault information).
With regards to Claim 8, Mukherjee teaches the device of Claim 7 as referenced above. Mukherjee further teaches:
wherein the management controller is further configured to:
based on fault information of the first hardware, update fault information associated with the register corresponding to the first hardware to obtain an updated correspondence (Fig. 6; col. 10, lines 50-67; and col. 11, lines 1-13; regarding, e.g., updating a master device fault table either periodically or when more faults have been detected.); and
send the updated correspondence to the processor (Fig. 6; col. 10, lines 50-67; col. 11, lines 1-13; Fig. 4; col. 8, lines 13-48; Fig. 1; and col. 3, lines 23-29.).
Mukherjee does not explicitly teach:
indicated by a user in accordance with the method of Claim 5.
However, Yadav teaches:
indicated by a user (Fig. 5; ¶ 0046; and ¶ 0051: “user configurable.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Mukherjee with user-configurable table data as taught by Yadav because a simple substitution of one known element (detailed fault information table entry data – Mukherjee: Fig. 4; Mukherjee: col. 8, lines 61-67; and Mukherjee: col. 9, lines 1-3) for another (user-configurable table data) can be performed to obtain predictable results (providing known register data field entries for identifying and/or recording fault information).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chaiken et al. (U.S. Patent Application Publication No. US 2021/0255939 A1); teaching an information handling system including a non-volatile storage device communicatively coupled to a boot processor and an application processor. The boot processor, prior to the execution of a hang sensitive transaction, stores information associated with the hang sensitive transaction at a memory device. The application processor is configured to detect a catastrophic failure of the hang sensitive transaction. In response to the detection of the catastrophic failure, the application processor retrieves the information stored at the memory device and store the information at the non-volatile storage device.
Nagaraj et al. (U.S. Patent Application Publication No. US 2023/0236917 A1); teaching determining, by an operating system agent of a computer system, a first profile that is associated with an input/output (I/O) peripheral of the computer system. The first profile is associated with an error register of the I/O peripheral, and the first profile represents a configuration of the computer system that is associated with the I/O peripheral. The process includes, responsive to a notification of an error being associated with the I/O peripheral, determining, by the operating system agent, a second profile that is associated with the I/O peripheral. The second profile is associated with the error register. Moreover, responsive to the notification of the error, the process includes comparing, by a baseboard management controller of the computer system, the second profile to the first profile. Based on the comparison, the process includes determining, by the baseboard management controller, whether the error is attributable to a driver for the I/O peripheral.
Hong et al. (U.S. Patent No. US 11,720,438 B2); teaching a system, method and apparatus to record data relevant to hardware errors identified by microprocessors. For example, in response to a hardware error, a microprocessor can store first data about the error in registers in the microprocessor and start to execute instructions configured in firmware and/or in an operating system. Execution of the instructions in response to the hardware error causes the microprocessor to: generating second data about the error based at least in part on the first data in the registers; and store the second data at a location not affected by restarting execution of an operating system in the processor. For example, the execution of the instructions can cause the microprocessor to decode the first data to obtain a temperature of the computing device as part of the second data.
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/JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114
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