Prosecution Insights
Last updated: July 17, 2026
Application No. 19/252,330

METHOD FOR IMPROVING WRITE PERFORMANCE OF MIRRORED REDUNDANT ARRAY OF INDEPENDENT DISKS CONFIGURATION THAT USES DISK STRIPING WITH PARITY RAID5 AND DEVICE

Non-Final OA §103
Filed
Jun 27, 2025
Priority
Dec 30, 2022 — CN 202211737093.7 +1 more
Examiner
MCCARTHY, CHRISTOPHER S
Art Unit
2113
Tech Center
2100 — Computer Architecture & Software
Assignee
XFUSION DIGITAL TECHNOLOGIES CO., LTD.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
730 granted / 849 resolved
+31.0% vs TC avg
Minimal -5% lift
Without
With
+-4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
13 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
7.5%
-32.5% vs TC avg
§103
59.4%
+19.4% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 849 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. U.S. Patent 10,754,574 in view of Gupta U.S. Patent Application Publication US2019/0286374A1. As per claim 1, Jo teaches a method for improving write performance, comprising: acquiring a data write request, wherein the data write request includes one or more pieces of data to be written and a respective hard disk location to be written corresponding to each piece of the one or more pieces of data to be written; and in response to the data write request, writing each piece of the one or more pieces of data to be written into the respective hard disk location to be written corresponding to the each piece of the one or more pieces of data to be written (column 3, lines 21-32). Gupta teaches a redundant array of independent disks (RAID) configuration that uses disk striping with parity (¶ 0024), and adjusting data bit state information corresponding to the respective hard disk location to be written (¶ 0018). It would have been obvious to one of ordinary skill in the art to use the process of Gupta in the process of Jo. One of ordinary skill in the art would have been motivated to use the process of Gupta in the process of Jo because using the process of Gupta would yield the predictable result of ensuring data access regulation in a memory system, an explicit desire of Jo. As per claim 2, Gupta teaches the method according to claim 1, wherein the data bit state information comprises hard disk state information and flag bit state information; and wherein adjusting the data bit state information corresponding to the respective hard disk location to be written, comprises: after writing the one or more pieces of data to be written into the respective hard disk location to be written corresponding to each piece of the one or more pieces of data to be written, acquiring a number of times data is written into each hard disk location to be written, and adjusting the hard disk state information corresponding to the each hard disk location to be written, wherein the hard disk state information corresponding to the each hard disk location to be written is configured to indicate that the each hard disk location to be written has been used; and adjusting the flag bit state information corresponding to each hard disk location to be written based on the number of times the data is written into the each hard disk location to be written, wherein the flag bit state information corresponding to the each hard disk location to be written is configured to indicate the number of times the data is written into the each hard disk location to be written (¶ 0018, wherein each data location mapping comprises a data write value that is adjusted with each write to the location and a write counter that indicates how many times each location has been written upon). As per claim 13, Jo teaches a computing device, comprising a processor and a memory connected to the processor, wherein the memory is configured to store a computer program, the computer program comprises a program instruction, and the processor is configured to execute the program instruction to cause the computing device to perform operations comprising: acquiring a data write request, wherein the data write request includes one or more pieces of data to be written and a respective hard disk location to be written corresponding to each piece of the one or more pieces of data to be written; and in response to the data write request, writing each piece of the one or more pieces of data to be written into the respective hard disk location to be written corresponding to the each piece of the one or more pieces of data to be written (column 3, lines 21-32). Gupta teaches adjusting data bit state information corresponding to the respective hard disk location to be written (¶ 0018). It would have been obvious to one of ordinary skill in the art to use the process of Gupta in the process of Jo. One of ordinary skill in the art would have been motivated to use the process of Gupta in the process of Jo because using the process of Gupta would yield the predictable result of ensuring data access regulation in a memory system, an explicit desire of Jo. As per claim 14, Gupta teaches the method according to claim 1, wherein the RAID configuration is a mirrored RAID configuration that uses disk striping with parity (RAID5) (¶ 0024, wherein Gupta teaches a RAID with striping and parity and also teaches that all levels of a RAID can be used, which inherently includes RAID 5). As per claim 15, Jo teaches a non-transitory computer readable storage medium having stored thereon computer instructions that, when executed by a processor of a computing device, causes the computing device to perform operations comprising: acquiring a data write request, wherein the data write request includes one or more pieces of data to be written and a respective hard disk location to be written corresponding to each piece of the one or more pieces of data to be written; and in response to the data write request, writing each piece of the one or more pieces of data to be written into the respective hard disk location to be written corresponding to the each piece of the one or more pieces of data to be written (column 3, lines 21-32). Gupta teaches adjusting data bit state information corresponding to the respective hard disk location to be written (¶ 0018). It would have been obvious to one of ordinary skill in the art to use the process of Gupta in the process of Jo. One of ordinary skill in the art would have been motivated to use the process of Gupta in the process of Jo because using the process of Gupta would yield the predictable result of ensuring data access regulation in a memory system, an explicit desire of Jo. Allowable Subject Matter Claims 3-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 8,882,599 to Grube et al.: Metadata to indicate write threshold for slices in a RAID system. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER S MCCARTHY whose telephone number is (571)272-3651. The examiner can normally be reached Monday-Friday 8:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER S MCCARTHY/Primary Examiner, Art Unit 2113
Read full office action

Prosecution Timeline

Jun 27, 2025
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
81%
With Interview (-4.8%)
2y 6m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 849 resolved cases by this examiner. Grant probability derived from career allowance rate.

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