Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 27 June 2025 for application number 19/252,465. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 15 February 2023 (Provisional 63/445, 812).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04 November 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 – 6, 8 – 11, 13, and 15 – 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 4, 6 – 11, 13, 15 – 18, and 20 of U.S. Patent No. 12,386,515. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the conflicting application disclose the limitations required of the claims in the instant application.
Claims 1 – 6, 8 – 11, 13, and 15 – 19 of the instant application are compared to claims 1 – 4, 6 – 11, 13, 15 – 18, and 20 of U.S. Patent No. 12,386,515 in the following table:
Instant Application
U.S. Patent No. 12,386,515
A method, comprising:
identifying, by a processing device, a value of a media endurance metric associated with one or more memory blocks of a memory device;
performing a programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 1)
The method of claim 1, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 2)
The method of claim 1, further comprising:
identifying a read level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 3)
The method of claim 3, wherein determining the read voltage offset further comprises:
accessing a look-up table stored on the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the read voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 4)
The method of claim 1, wherein identifying the value of the media endurance metric associated with the one or more memory blocks further comprises:
accessing a program-erase counter stored in a metadata of the memory device; and
identifying, based on a value of the program-erase counter, a number of program-erase operations performed on the one or more memory blocks. (claim 5)
The method of claim 1, wherein determining the program-verify voltage offset further comprises:
accessing a look-up table stored on the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 6)
A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a value of a media endurance metric associated with one or more memory blocks of a memory device;
performing a programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 8)
The system of claim 8, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 9)
The system of claim 8, wherein the operations further comprise:
identifying a read level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 10)
The system of claim 10, wherein determining the read voltage offset further comprises:
accessing a look-up table stored on the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the read voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 11)
The system of claim 8, wherein determining the program-verify voltage offset further comprises:
accessing a look-up table stored on the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 13)
A non-transitory computer-readable storage medium comprising instructions that,
when executed by a processing device, cause the processing device to perform operations comprising:
identifying a value of a media endurance metric associated with one or more memory blocks of a memory device;
performing a programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 15)
The non-transitory computer-readable storage medium of claim 15, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 16)
The non-transitory computer-readable storage medium of claim 15, further comprising instructions that, when executed by the processing device, cause the processing device to perform operations comprising:
identifying a read level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 17)
The non-transitory computer-readable storage medium of claim 15, wherein identifying the value of the media endurance metric associated with the one or more memory blocks further comprises:
accessing a program-erase counter stored in a metadata of the memory device; and
identifying, based on a value of the program-erase counter, a number of program-erase operations performed on the one or more memory blocks. (claim 18)
The non-transitory computer-readable storage medium of claim 15, wherein determining the program-verify voltage offset further comprises:
accessing a look-up table stored on the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 19)
A method, comprising:
receiving, by a processing device, a request for performing a programming operation on one or more memory blocks of a memory device;
identifying a value of a media endurance metric associated with the one or more memory blocks;
determining a programming voltage offset corresponding to the value of the media endurance metric;
performing, using the programming voltage offset, the programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 1)
The method of claim 1, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 2)
The method of claim 1, further comprising:
identifying a read voltage level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 3)
The method of claim 3, wherein determining the read voltage offset further comprises:
accessing an offset look-up table stored in a metadata of the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the read voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 7)
The method of claim 1, wherein identifying the value of the media endurance metric associated with the one or more memory blocks further comprises:
accessing a program-erase counter stored in a metadata of the memory device; and
identifying, based on a value of the program-erase counter, a number of program-
erase operations performed on the one or more memory blocks. (claim 4)
The method of claim 1, wherein determining the program-verify voltage offset further comprises:
accessing an offset look-up table stored in a metadata of the memory device;
identifying a voltage bin associated with the one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 6)
A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a value of a media endurance metric associated with the one or more memory blocks of the memory device;
determining a programming voltage offset corresponding to the value of the media endurance metric;
performing, using the programming voltage offset, a programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 8)
The system of claim 8, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 9)
The system of claim 8, wherein the operations further comprise:
identifying a read voltage level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 10)
The system of claim 8, wherein identifying the value of the media endurance metric associated with the one or more memory blocks further comprises:
accessing a program-erase counter stored in a metadata of the memory device; and
identifying, based on the value of the program-erase counter, a number of program-erase operations performed on the one or more memory blocks. (claim 11)
The system of claim 8, wherein determining the program-verify voltage offset further comprises:
accessing an offset look-up table stored in a metadata of the memory device;
identifying a voltage bin associated with one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 13)
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving a request for performing a programming operation on one or more memory blocks of a memory device;
identifying a value of a media endurance metric associated with the one or more memory blocks of the memory device;
determining a programming voltage offset corresponding to the value of the media endurance metric;
performing, using the programming voltage offset, the programming operation on the one or more memory blocks;
identifying a program-verify voltage level associated with the one or more memory blocks;
determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and
performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks. (claim 15)
The non-transitory computer-readable storage medium of claim 15, wherein the media endurance metric reflects a number of program-erase cycles performed on the one or more memory blocks. (claim 16)
The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise:
identifying a read voltage level associated with the one or more memory blocks;
determining a read voltage offset associated with the read voltage level and the value of the media endurance metric; and
performing, using the read voltage level and the read voltage offset, a read operation on the one or more memory blocks. (claim 17)
The non-transitory computer-readable storage medium of claim 15, wherein identifying the value of the media endurance metric associated with the one or more memory blocks further comprises:
accessing a program-erase counter stored in a metadata of the memory device; and
identifying, based on a value of the program-erase counter, a number of program-erase operations performed on the one or more memory blocks. (claim 18)
The non-transitory computer-readable storage medium of claim 15, wherein determining the program-verify voltage offset further comprises:
accessing an offset look-up table stored in a metadata of the memory device;
identifying a voltage bin associated with one or more memory blocks; and
determining the program-verify voltage offset corresponding to the voltage bin and the value of the media endurance metric. (claim 20)
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 1 – 6, 8 – 11, 13, and 15 – 19 are rejected under a Double Patenting rejection. Claims 7, 12, 14, and 20 are rejected based on their dependency.
Allowable Subject Matter
Claims 1 – 20 would be allowable upon a timely filed terminal disclaimer to overcome the Double Patenting rejection set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: for independent claims 1, 8, and 15 the prior art of record, neither anticipates, nor renders obvious a program-verify offset that is determined based on both a program-verify voltage level and a value of a media endurance metric for memory blocks, and performing a program-verify operation on the memory blocks by using the program-verify voltage level and the determined program-verify voltage offset. Claims 2 – 7, 9 – 14, and 16 – 20 depend from claims 1, 8, and 15 respectively and would be allowable, subject to the Double Patenting rejection.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prakash et al., US Pub. No. 2024/0185928 A1 – teaches “A method for performing a read operation of a fully programmed non-volatile memory that, initially, was partially programmed, the method comprising: selecting a word line within an initially programmed portion; applying a read to the selected word line, determining a first “optimal” read verify voltage level for each program state; once fully programmed, applying a read to the selected word line, determining a second “optimal” read verify voltage level for each program state; for each program state, determining a difference between the first “optimal” read verify voltage level and the second “optimal” read verify voltage level, the difference defining a supplemental offset value; determining an “optimal” read verify voltage level for each program state by applying the supplemental offset value in conjunction with an initial offset value defined in a pre-calibrated “lookup” table; and applying a read to each word line according to each determined “optimal” read verify voltage level.” [Abstract]
Liang et al., US Patent No. 9,275,741 B1 – teaches “In certain embodiments, in addition to program verify level offset, voltage read levels may also be offset to account for the offset program verify levels.” [col. 6, lines 50-52]
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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