DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
As required by M.P.E.P. ' 609 (C), the applicant's submission of the Information Disclosure Statement dated July 7th, 2025 and February 24th, 2026, are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. ' 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 10, 14-15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin [CN106708542]. Jin teaches an embedded operating system code loading method and device.
Regarding claims 10, 1, 14, and 19, Jin teaches a method comprising:
executing a first service scenario [Jin middle page 3, “…obtaining current usage scenes…”];
obtaining a first call frequency of a first function [Jin middle of page 2, “…obtaining the recovery code and calling function…” and “…dividing the first memory area according to the call frequency code is divided into a plurality of memory sub areas…”] and a second call frequency of a second function [Jin middle of page 2, “…code transfer frequency greater than the second in sub-secondary area…”], wherein the first function and the second function are called after execution of the first service scenario starts [Jin middle page 3, “…obtaining current usage scenes…”(Current would imply after it starts.)], and wherein the first call frequency is higher than the second call frequency [Jin bottom half of page 2, “…and the code transfer frequency in the first memory sub area code transfer frequency greater than the second in sub-secondary area…”];
adjusting a first storage location of the first function to a first location [Jin top of page 5, “…the first memory area is used for storing the embedded operation system frequently scheduling code in the memory area, and the memory of the first memory area is small…” and full paragraph, bottom half page 3, “…obtaining the recovery code and call function, and finally loads the needed recovery code, and loading other code corresponding to the current usage scenes according to the transfer function from the second memory area. The invention can recovery code and calling function according to the need so as to directly load other code corresponding to the current usage scenes from the second memory area, there is no need to recover all code in the first memory area…”(Where loading between the first and second storage areas reads on the BRI of adjusting.)], wherein the first location is in a first storage area of a computer device [Jin top of page 2, “…internal Inter Ram inner Inter Ram instruction access speed is fast…”]; and
adjusting a second storage location of the second function to a second location [Jin full paragraph, bottom half page 3, “…obtaining the recovery code and call function, and finally loads the needed recovery code, and loading other code corresponding to the current usage scenes according to the transfer function from the second memory area. The invention can recovery code and calling function according to the need so as to directly load other code corresponding to the current usage scenes from the second memory area, there is no need to recover all code in the first memory area…”(Where loading between the first and second storage areas reads on the BRI of adjusting.)],
wherein the second location is in the first storage area [Jin top of page 2, “…the access speed is slow for fetch access DDR…” and 2nd paragraph, page 5, “…a second memory sub area of the area space and the third memory sub area of the area space can be 68KB…”(Internal cache and DDR are located on the same computer system.)], and
wherein a first address of the first location is lower than a second address of the second location or a first access rate of the first location is higher than a second access rate of the second location [Jin 2nd paragraph on 5th page, “…the first code transfer frequency in the memory sub area transfer frequency greater than the second memory sub area…”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin [CN106708542]. Jin teaches an embedded operating system code loading method and device.
Regarding claims 2, 15, and 20, as per claim 1, Jin teaches further comprising:
obtaining a third call frequency of a third function [Jin middle of page 2, “…obtaining the recovery code and calling function…” and “…dividing the first memory area according to the call frequency code is divided into a plurality of memory sub areas…”] and a fourth call frequency of a fourth function [Jin middle of page 2, “…code transfer frequency greater than the second in sub-secondary area…”], wherein the third function and the fourth function are called after execution of the first service scenario starts [Jin middle page 3, “…obtaining current usage scenes…”(Current would imply after it starts.)], and wherein the third call frequency is higher than the fourth call frequency [Jin bottom half of page 2, “…and the code transfer frequency in the first memory sub area code transfer frequency greater than the second in sub-secondary area…”];
adjusting a third storage location of the third function to a third location [Jin top of page 5, “…the first memory area is used for storing the embedded operation system frequently scheduling code in the memory area, and the memory of the first memory area is small…” and full paragraph, bottom half page 3, “…obtaining the recovery code and call function, and finally loads the needed recovery code, and loading other code corresponding to the current usage scenes according to the transfer function from the second memory area. The invention can recovery code and calling function according to the need so as to directly load other code corresponding to the current usage scenes from the second memory area, there is no need to recover all code in the first memory area…”(Where loading between the first and second storage areas reads on the BRI of adjusting.)]; and
adjusting a fourth storage location of the fourth function to a fourth location [Jin full paragraph, bottom half page 3, “…obtaining the recovery code and call function, and finally loads the needed recovery code, and loading other code corresponding to the current usage scenes according to the transfer function from the second memory area. The invention can recovery code and calling function according to the need so as to directly load other code corresponding to the current usage scenes from the second memory area, there is no need to recover all code in the first memory area…”(Where loading between the first and second storage areas reads on the BRI of adjusting.)], wherein the third location and the fourth location are in the first storage area [Jin top of page 2, “…the access speed is slow for fetch access DDR…” and 2nd paragraph, page 5, “…a second memory sub area of the area space and the third memory sub area of the area space can be 68KB…”(Internal cache and DDR are located on the same computer system.)], and wherein either a third address of the third location is lower than a fourth address of the fourth location or a third access rate of the third location is higher than a fourth access rate of the fourth location [Jin 2nd paragraph on 5th page, “…the first code transfer frequency in the memory sub area transfer frequency greater than the second memory sub area…”].
The examiner has determined it would have been obvious to duplicate the same function as taught in claims 10, 1, 14, and 19. The claims add no additional features and it would have been obvious at the time of the invention for the same process/method to receive multiple functions for which the operation would have to operate on after the first and second were processed. Those third and forth functions would be processed the same way as the first and second ones. The MPEP clearly states that duplication is a relational for an obviousness rejection as seen in MPEP 2144.04(VI)(B).
Allowable Subject Matter
Claims 3-6, 7-9, 11-13, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Doshi et al. [US2019/0042124] Doshi teaches hot paths and cold paths for allocating malloc call functions.
Haber et [US2002/0196678] Haber teaches hot and cold compiler code blockes.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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