DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 18-37 are pending.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Receipt is acknowledged of certified copies or papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 07/14/2025, 09/19/2025 and 03/10/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 18, 22-25, 29-31 and 35-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Serebrin et al. (US Pub. No. 2011/0197003 A1 hereinafter “Serebrin” – IDS Submission).
Referring to claim 18, Serebrin discloses a method applied to a node device (Serebrin – Fig. 2, host hardware 20), the method comprising:
obtaining an interrupt event (Serebrin – Fig. 3 & par. [0076-0077] disclose the interrupt may be transmitted in the form of a message-signaled interrupt (MSI).);
generating an interrupt message of the interrupt event (Serebrin – Fig. 3 & par. [0078] disclose if the G/H indication indicates host, the device interrupt manager 38 may transmit an interrupt message to the APICs 32A-32B, and the interrupt may be handled according to the APIC specification (Interrupt Message (Host), arrow F).), wherein the interrupt message comprises an interrupt vector and an interrupt address (Serebrin – Par. [0062] discloses interrupts may have associated interrupt vectors, and the interrupt vector may be part of the interrupt message. The interrupt message may also include the destination ID (e.g. logical or physical APIC ID).), the interrupt vector is obtained from an interrupt vector table, and the interrupt address is obtained from an interrupt address table (Serebrin – Fig. 3, interrupt vector C1 received from device table 52 and interrupt address, DestID, C2 received from interrupt remapping table 64); and
sending the interrupt message to a network node through a bus system (Serebrin – See Par. [0062, 0078]).
Referring to claim 22, Serebrin discloses the method according to claim 18, wherein the node device comprises one or more of: a graphics card, a hard disk, a network interface card, or an audio card (Serebrin – Par. [0072] discloses the peripherals 52a-52B may include networking devices.).
Referring to claim 23, Serebrin discloses the method according to claim 18, wherein: the interrupt vector table comprises an address index corresponding to the interrupt vector; and the interrupt address is obtained from the interrupt address table based on the address index (Serebrin – Par. [0077] discloses the IOMMU 40 (and more particularly the device interrupt manager 38, in this embodiment), may index into the device table 62 using the BDF (arrow B), and may identify a device table entry corresponding to the peripheral 52A. The entry may include the APIC ID table pointer (arrow C). In this embodiment, the device table entry may also include an interrupt remapping table pointer (IRTP) that may identify an interrupt remapping table 64 corresponding to the device (arrow C1). The interrupt remapping table 64 may be indexed by the original interrupt vector, and may provide an output vector and destination ID (DestID, e.g. logical or physical APIC ID) for the interrupt (arrow C2).).
Referring to claim 24, Serebrin discloses the method according to claim 18, wherein the interrupt vector table and the interrupt address table are stored on the node device (Serebrin – Fig. 2, host hardware 20 having a memory 56 storing the device table 62 and the interrupt remapping table 64.).
Referring to claim 25, note the rejections of claim 18 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 29 and 37, note the rejections of claim 22 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 30 and 35, note the rejections of claim 23 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Related Prior Art
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. IIan et al. (US Pub. No. 2023/0057562 A1 hereinafter “Han”) discloses an example method may include allocating, on a host computer system, a memory page in a memory of an input/output (I/O) device, mapping the memory page into a memory space of a virtual machine associated with a first virtual processor, creating a first entry in an interrupt mapping table in the memory of the I/O device, where the first entry includes a memory address that is associated with a second virtual processor identifier and further includes an interrupt vector identifier; and creating a second entry in an interrupt injection table of an interrupt injection unit of the host computer system, where the second entry is associated with a memory address that corresponds to a second virtual processor, the second entry includes the interrupt vector identifier, and the second entry is further associated with the second virtual processor identifier.
b. Winkler et al. (US Pub. No. 2006/0047877 A1 hereinafter “Winkler”) discloses an interrupt processing technique is provided where an interrupt message is sent to an interrupt controller of a processor in response to an interrupt request from an individual device. The interrupt message comprises a memory address and interrupt status information. The memory address is specifically allocated to the device that has issued the interrupt request. The interrupt status information indicates an interrupt status of the device. An interrupt table that is stored in the memory is updated by the interrupt controller using the interrupt status information comprised in the interrupt message. The interrupt table holds device specific interrupt statuses. Updating the interrupt table comprises addressing the memory using the memory address in the interrupt message.
c. Baker et al. (US Patent No. 5,369,749 hereinafter “Baker”) discloses the functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.
Allowable Subject Matter
9. Claims 19-21, 26-28 and 32-34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein: the interrupt vector table comprises a plurality of first entries, each first entry of the plurality of first entries comprising one interrupt vector and corresponding to one interrupt event; the interrupt address table comprises at least one second entry, each second entry of the at least one second entry comprising one interrupt address; and the plurality of first entries comprise M first entries corresponding to M interrupt events, each interrupt event of the M interrupt events corresponding to a same second entry in the at least one second entry, wherein M is a positive integer greater than or equal to 2.”, in combination with other recited limitations in dependent claims 19, 26 and 32.
Claims 20, 21, 27, 28, 33 and 34 would be allowable based on their dependencies of claims 19, 26 and 32.
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Ill(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 2707754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
Prosecution Insights