DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: Please update the status of the parent application, referenced to in the first paragraph of the specification.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3, 5, 9 and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3, 5 and 10 of U.S. Patent No.12,348,256. Although the claims at issue are not identical, they are not patentably distinct from each other because:
12,348,256
Instant Application: 19/254,068
1. A circuit comprising: a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal, the differential input circuit including: a first transistor having a first transistor control terminal and first and second terminals; and a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together; a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal; a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal; a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal; and a differential output circuit having a first output at a first inverter output, having a second output at a second inverter output, having a third transistor control terminal coupled to the second terminal of the first transistor, and having a fourth transistor control terminal coupled to the second terminal of the second transistor.
2. The circuit of claim 1, further comprising: a first resistor having a first terminal coupled to the first transistor control terminal, and having a second terminal as the first offset correction input; and a second resistor having a first terminal coupled to the second transistor control terminal, and having a second terminal as the second offset correction input.
3. The circuit of claim 2, further comprising a capacitor digital-to-analog converter coupled to the second terminals of the first and second resistors.
1. An electronic circuit comprising: a differential input circuit comprising first and second transistors; a first capacitor coupled to a control terminal of the first transistor; a second capacitor coupled to a control terminal of the second transistor; a differential output circuit comprising: a third transistor having a control terminal coupled to a first current path terminal of the first transistor; a fourth transistor having a control terminal coupled to a first current path terminal of the second transistor; and a digital-to-analog converter (DAC) having a first output coupled to a first intermediate node that is between the control terminal of the first transistor and the first capacitor, and a second output coupled to a second intermediate node that is between the control terminal of the second transistor and the second capacitor.
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2. The electronic circuit of claim 1, further comprising: a first resistor coupled between the first output of the DAC and the first intermediate node; and a second resistor coupled between the second output of the DAC and the second intermediate node.
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3. The electronic circuit of claim 1, further comprising a pre-amplifier comprising: a first terminal coupled to the first current path terminal of the first transistor; and a second terminal coupled to the first current path terminal of the second transistor.
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9. The electronic circuit of claim 1, wherein the DAC is a capacitor DAC.
Claim 3 recites electronic components in the body of the claim. One skill in the art would know that a circuit reciting electronic components is an electronic circuit.
5. The circuit of claim 4, wherein the differential output circuit includes: a first inverter having the first inverter output and having an input coupled to the second terminal of the fourth transistor; and a second inverter having the second inverter output and having an input coupled to the second terminal of the third transistor.
5. The electronic circuit of claim 1, wherein the differential output circuit comprises: first and second output terminals; a first inverter having an input coupled to a first current path terminal of the third transistor, and an output coupled to the first output terminal of the differential output circuit; and a second inverter having an input coupled to a first current path terminal of the fourth transistor, and an output coupled to the second output terminal of the differential output circuit.
8. A circuit comprising: a differential input circuit including: a first transistor having a first transistor control terminal and first and second terminals; and a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together; a first capacitor coupled to the control terminal of the first transistor; a second capacitor coupled to the control terminal of the second transistor; an offset correction circuit having a first terminal coupled to the control terminal of the first transistor and having a second terminal coupled to the control terminal of the second transistor; a differential output circuit including: a third transistor having a third transistor control terminal coupled to the second terminal of the first transistor; and a fourth transistor having a fourth transistor control terminal coupled to the second terminal of the second transistor; and a pre-amplifier circuit having a first terminal coupled to the second terminal of the first transistor and to the control terminal of the third transistor, and having a second terminal coupled to the second terminal of the second transistor and to the control terminal of the fourth transistor.
9. The circuit of claim 8, wherein the offset correction circuit includes: a first resistor having the first terminal of the offset correction circuit, which is coupled to the first transistor control terminal, and having a second terminal; and a second resistor having the second terminal of the offset correction circuit, which is coupled to the second transistor control terminal, and having a second terminal.
10. The circuit of claim 9, wherein the offset correction circuit includes a capacitor digital-to-analog converter coupled to the second terminals of the first and second resistors.
14. An electronic circuit comprising: a differential input circuit comprising first and second transistors; a first capacitor coupled to a control terminal of the first transistor; a second capacitor coupled to a control terminal of the second transistor; a preamplifier circuit comprising: a third transistor having a control terminal coupled to a clock terminal, and a first current path terminal coupled to a first current path terminal of the first transistor; a fourth transistor having a control terminal coupled to the clock terminal, and a first current path terminal coupled to a first current path terminal of the second transistor; and a fifth transistor having a control terminal coupled to the clock terminal, and a current path coupled between the first current path terminal of the first transistor and the first current path terminal of the second transistor; and a digital-to-analog converter (DAC) having a first output coupled to a first intermediate node that is between the control terminal of the first transistor and the first capacitor, and a second output coupled to a second intermediate node that is between the control terminal of the second transistor and the second capacitor.
Claim 8 recites electronic components in the body of the claim. One skill in the art would know that a circuit reciting electronic components is an electronic circuit.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Allowable Subject Matter
Claims 4, 6-8, 10-13, and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20100019848 A1, discloses(fig. 3) An electronic circuit comprising: a input circuit comprising first and second transistors (MP1 and MN1) ;a first capacitor ( C1/C3)coupled to a control terminal of the first transistor (MN1);a second capacitor (C2/C4) coupled to a control terminal of the second transistor (MP1) ;a output circuit comprising: a third transistor (MMN2) having a control terminal coupled to a first current path terminal of the first transistor (MN1) ;a fourth transistor (MP2) having a control terminal coupled to a first current path terminal of the second transistor (MP1); However, it fails to teach or fairly suggest “a digital-to-analog converter (DAC) having a first output coupled to a first intermediate node that is between the control terminal of the first transistor and the first capacitor, and a second output coupled to a second intermediate node that is between the control terminal of the second transistor and the second capacitor”.
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/JEAN B CORRIELUS/Primary Examiner, Art Unit 2633
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