DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9,20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al. (US 2013/0257846) in view of Teranishi (US 2011/0316897).
As to Claim 1, Matsuda et al. discloses A liquid crystal display device comprising: a pixel including a first memory circuit (fig.2-4; data retention section DS1; para.0061,0073; fig.11,14), a second memory circuit (fig.2-4; data retention section DS2; para.0061,0075), and a display circuit including a liquid crystal capacitance and connected to the first memory circuit and the second memory circuit (fig.4, liquid crystal capacitor Clc, para.0110);
a first power source line and a second power source line each connected to the display circuit
a refresh circuit configured to read memory data stored in the first memory circuit and write back the memory data to the first memory circuit in accordance with a result of the reading (figs.2-4; para.0083, 0087-0089,0093-0094,0096; first data retention section DS1 transfers binary logic level to second data retention DS2, which in turn provides control information to the refresh output control section RS1 indicating the first electric potential is being retained in DS2, the refresh output section RS1 then writes a second electric potential level over the binary logic that has been retained until then in retention data section DS1); and
a control circuit configured to control the refresh circuit (fig.2-4; refresh output control line RC1 controls the refresh output section RS1; para.0087,0090);
wherein one of potentials of the first power source line or potentials of the second power source line are written to the liquid crystal capacitance before the write back of the memory data; and
another of the potentials of the first power source line or the potentials of the second power source line are written to the liquid crystal capacitance after the write back of the memory data.
Matsuda et al. does not expressly disclose a first power source line and a second power source line each connected to the display circuit ; a refresh circuit configured to read memory data stored in the first memory circuit; wherein one of potentials of the first power source line or potentials of the second power source line are written to the liquid crystal capacitance before the write back of the memory data; and another of the potentials of the first power source line or the potentials of the second power source line are written to the liquid crystal capacitance after the write back of the memory data.
Teranishi discloses a pixel comprising a first power source line and a second power source line each connected to the display circuit (fig.3-4, potential Vsig/Vxcs, Vcs, Vdd, Vss connected to liquid crystal capacitance 21; para.0114, 0128-129,0139-0140); a refresh circuit configured to read memory data stored in the first memory circuit (fig.4, transistors 24-27 and inverter 23 collectively; para.0114,0116-0120,0123-0125; the held potential of holding capacitance 22 is read out and provided to the inverter 23, the inverter then inverts the polarity of the held potential, and inverted potential is then written to the holding capacitance 22),
wherein one of potentials of the first power source line or potentials of the second power source line are written to the liquid crystal capacitance before the write back of the memory data (para.0151, 0155; before the refresh operation, Vsig/Vxcs reflecting grayscale is written to holding capacitance 22 via transistor 25; para.0170 memory display mode, writing the signal potential reflecting grayscale from the signal line 31 to holding capacitance 22 is the same as in analog display mode); and
another of the potentials of the first power source line or the potentials of the second power source line are written to the liquid crystal capacitance after the write back of the memory data (para.0156,0164-0167- signal potential Vdd, that reflects the grayscale is obtained by polarity inversion (i.e. after writing back the potential) is written to the holding capacitance 22; para.0171-0173, in memory display mode, in a polarity inversion refresh operation (after memory data is read and written back), Vcs written to the holding capacitance 22).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Matsuda et al., with the teachings of Teranishi, the motivation being to provide a refresh operation enabling performance enhancement such as power consumption reduction and improvement in the operating margin of DRAM
As to Claim 2, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit writes back inverted data of the memory data read from the first memory circuit to the first memory circuit (Matsuda-figs.2-4,11,14; para.0093-0094,0096; Teranishi-figs.3-4-para. 0123-0125).
As to Claim 3, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit writes back the same data as the memory data read from the first memory circuit to the second memory circuit (Matsuda-figs.2-4; para.0074,0083- binary logic level retained in data retention section DS1 is transferred to second data retention section DS2).
As to Claim 4, Matsuda et al. in view of Teranishi disclose wherein potentials of the first power source line and the second power source line are exchanged to each other in accordance with the writing-back (Matsuda-para.0218; Teranishi- para.0266; fig.11).
As to Claim 5, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit receives an instruction from the control circuit and performs the writing-back within a memory maintaining period of the first memory circuit (Matsuda-para.0116, 0121- period t6 refresh output is high within memory period MRY).
As to Claim 6, Matsuda et al. in view of Teranishi disclose wherein the control circuit includes a timer and a timing controller, and the timing controller activated by the timer controls the refresh circuit (Matsuda-fig.1, para.0064; Teranishi-fig.1, para.0106,0150)).
As to Claim 7, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit stops after the writing-back (Matsuda-para.0093; Ternanishi-para.0227,0229,0231)
As to Claim 8, Matsuda et al. in view of Teranishi do not expressly disclose wherein the timing controller stops after the writing-back. However, in Matsuda et al. in view of Teranishi, Teranishi discloses where during a rewriting operation switch elements 27 and 25 are in on state, and where the timing generator 60 controls the on/off states of the switch elements 24-27 (para.0121, 0124,0156). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Matsuda et al. in view of Teranishi, such that the timing control 60 stops the switch elements 27,25 after rewriting operation is performed. The motivation being to aid in reduction in the power consumption of the device.
As to Claim 9, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit includes a reading circuit configured to read memory data and a latch circuit configured to latch the read memory data (Teranishi- fig.3-4,15 para.0123-0125; 0269-0270; transistors 25-26 are on state, during which the capacitance is read out and sent to the inverter circuit 23, where the inverter may have a latch configuration).
As to Claim 20, Matsuda et al. in view of Teranishi disclose wherein the refresh circuit reads memory data stored in the second memory circuit, and notifies the timing controller when the memory data stored in the first memory circuit and the memory data stored in the second memory circuit are not in an inverted relationship (para.0088, RS1 is brought into active state, and refresh operation is performed; para.0064,0076- driving signal generating circuit controls memory operation).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda et al. (US 2013/0257846) in view of Teranishi (US 2011/0316897), further in view of Tobita et al. (US 20020180675).
As to Claim 23, Matsuda et al. in view of Teranishi disclose a display region in which a pixel group including the pixel is provided (Matsuda-fig.1; Teranishi-fig.1).
Matsuda et al. in view of Teranishi do not expressly disclose a non-display region in which the refresh circuit is provided.
Tobita et al. discloses a non-display region in which the refresh circuit is provided (fig.1-2, refresh circuit 6 separate from the pixel area 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Matsuda et al. in view of Teranishi, with the teachings of Tobita et al., the motivation being to provide the refresh circuit in area separate from the pixel matrix.
Allowable Subject Matter
Claims 10-19, 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent Claim 10 is allowable over the prior art of record for the reasons noted in office action 04/22/2026.
Response to Arguments
Applicant's arguments filed 07/20/2026 have been fully considered but they are not persuasive.
Re Claim 1, applicant argues Matsuda et al. in view of Teranishi do no disclose the newly added limitations “ wherein one of potentials of the first power source line or potentials of the second power source line are written to the liquid crystal capacitance before the write back of the memory data; and another of the potentials of the first power source line or the potentials of the second power source line are written to the liquid crystal capacitance after the write back of the memory data”.
However, the examiner respectfully disagrees. Matsuda et al. in view of Teranishi disclose the new added limitations as claimed, as set forth above. (See claim rejection)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
