DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 and 4-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 17 of U.S. Patent No. 12,375,068. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application and the claims of the patent commonly claim, as follows:
19/254,813
12,375,068
1.
A control circuit for a switching stage of an electronic converter, the control circuit
comprising:
a pulse-width modulated (PWM) signal generator configured to generate a PWM signal;
a voltage generator configured to generate an offset voltage based on a digital word
signal,
a comparator circuit configured to generate a comparison signal based on a comparison
between a regulated output voltage and a sum signal;
wherein, in a first operating mode, the PWM signal generator is configured to repeat the
following switching phases for each switching cycle of a sequence of switching cycles:
for a first switching phase, generate the PWM signal having a first logic value, and
for a subsequent second switching phase, generate the PWM signal having a second
logic value,
wherein, in the first operating mode, the PWM generator is configured to generate the
PWM signal based on an error signal, and
wherein, in a second operating mode, the PWM generator is configured to generate the
PWM signal based on the comparison signal; and
a feedback circuit coupled to the comparator circuit and the PWM signal generator, the
feedback circuit comprising:
flagging circuitry configured to measure a difference between the duration of at least
one of the first switching phase or the second switching phase between consecutive switching cycles during the first operating mode and to generate a flag signal based on the measured difference, and
logic circuitry configured to, based on at least one of the flag signal or the comparison
signal, adjust the digital word signal to vary the offset voltage.
1.
A control circuit for a switching stage of an electronic converter configured to provide a regulated output voltage at an output node based on an input voltage received at an input node, the switching stage configured to be coupled to a reactive network referred to ground, the control circuit comprising:
a pulse-width modulated (PWM) signal generator configured to generate a PWM signal to drive the switching stage;
an error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to a reference voltage, the error amplifier configured to generate an error signal based on a difference between the reference voltage and the regulated output voltage;
a programmable voltage generator configured to generate a programmable offset voltage based on a digital word signal;
an adder circuit coupled to the programmable voltage generator and configured to receive the programmable offset voltage, the adder circuit being configured to generate a sum signal based on a sum of a reference voltage level and the programmable offset voltage;
a loop comparator circuit having a first comparator node coupled to the output node and configured to receive the regulated output voltage and a second comparator node coupled to the adder circuit and configured to receive the sum signal, the loop comparator circuit configured to generate a comparison signal having a first logic value in response to the regulated output voltage reaching a level of the sum signal and having a second logic value in response to the regulated output voltage failing to reach the level of the sum signal;
wherein, in a first operating mode, the PWM signal generator is configured to repeat the following switching phases for each switching cycle of a sequence of switching cycles:
for a first switching phase, generate the PWM signal having a first logic value, and for a subsequent second switching phase, generate the PWM signal having a second logic value,
wherein, in the first operating mode, the PWM generator is configured to determine the duration of the first switching phase or the second switching phase based on the error signal,
wherein, in a second operating mode, the PWM generator is configured to determine the duration of the first switching phase or the second switching phase based on the comparison signal;
the control circuit further comprising: a feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator, the feedback circuit configured to receive the comparison signal, receive the PWM signal, and to provide the digital word signal to the programmable voltage generator, the feedback circuit comprising:
flagging circuitry configured to measure a difference between the duration of at least one of the first switching phase or the second switching phase between consecutive switching cycles of the sequence of switching cycles during the first operating mode and to generate a flag signal having the first logic value in response to the measured difference reaching a threshold value and having the second logic value in response to the measured difference failing to reach the threshold value; and
logic circuitry configured to, based on at least one of the flag signal or the comparison signal, increase or decrease the digital word signal with respect to a preset digital word value, and vary the offset voltage generated by the programmable voltage generator.
2.
The control circuit of claim 1, wherein the flagging circuitry is configured to generate the flag signal having a first logic value in response to the measured difference reaching a threshold value and having a second logic value in response to the measured difference failing to reach the
threshold value.
1.
… generate a flag signal having the first logic value in response to the measured difference reaching a threshold value and having the second logic value in response to the measured difference failing to reach the threshold value;…
4.
The control circuit of claim 1, wherein the feedback circuit is coupled to the comparator
circuit, the PWM signal generator, and the voltage generator, and is configured to receive the comparison signal, receive the PWM signal, and provide the digital word signal to the voltage generator.
1.
… a feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator, the feedback circuit configured to receive the comparison signal, receive the PWM signal, and to provide the digital word signal to the programmable voltage generator,…
5.
The control circuit of claim 1, further comprising an adder circuit configured to generate the sum signal based on a sum of a reference voltage level and the offset voltage.
1.
… an adder circuit coupled to the programmable voltage generator and configured to receive the programmable offset voltage, the adder circuit being configured to generate a sum signal based on a sum of a reference voltage level and the programmable offset voltage;…
6.
The control circuit of claim 1, further comprising an error amplifier configured to
generate the error signal based on a difference between a reference voltage and the regulated output voltage.
1.
… an error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to a reference voltage, the error amplifier configured to generate an error signal based on a difference between the reference voltage and the regulated output voltage;
7.
The control circuit of claim 1, wherein the voltage generator comprises a programmable
voltage generator configured to generate a programmable offset voltage as the offset voltage.
1.
… a programmable voltage generator configured to generate a programmable offset voltage based on a digital word signal;
8. An electronic converter system, comprising:
a switching stage;
a reactive network coupled to the switching stage;
a PWM signal generator configured to generate a PWM signal to drive the switching
stage;
a programmable circuit configured to generate an offset value based on a control signal;
a comparator configured to generate a comparison signal based on a comparison
between an output voltage and a reference level;
wherein, in a first operating mode, the PWM signal generator is configured to repeat the
following switching phases for each switching cycle of a sequence of switching cycles:
for a first switching phase, generate the PWM signal having a first logic value, and
for a subsequent second switching phase, generate the PWM signal having a second
logic value, wherein, in the first operating mode, the PWM generator is configured to generate the PWM signal based on an error signal,
wherein, in a second operating mode, the PWM generator is configured to generate the
PWM signal based on the comparison signal; and
a feedback circuit coupled to the comparator and the PWM signal generator,
the feedback circuit comprising:
flagging circuitry configured to measure a difference between the duration of at least one of the first switching phase or the second switching phase between consecutive switching cycles during the first operating mode and to generate a flag signal having a first value in response to the measured difference reaching a threshold value and having a second value in response to the
measured difference failing to reach the threshold value, and
logic circuitry configured to, based on at least one of the flag signal or the comparison
signal, adjust the control signal to vary the offset value.
9. An electronic converter, comprising:
a first node configured to receive an input voltage; an output node configured to provide a regulated output voltage; a load coupled to the output node and configured to receive the regulated output voltage;
a switching node coupled to a reactive network referred to ground;
a switching stage coupled to the first node and to the switching node;
and a control circuit coupled to the switching stage and configured to provide at least one pulse-width modulated (PWM) signal to the switching stage based on the regulated output voltage and a reference voltage, the control circuit comprising:
a PWM signal generator configured to generate the PWM signal to drive the switching stage;
an error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to the reference voltage, the error amplifier configured to generate an error signal based on a difference between the reference voltage and the regulated output voltage;
a programmable voltage generator configured to generate a programmable offset voltage based on a digital word signal;
an adder circuit coupled to the programmable voltage generator and configured to receive the programmable offset voltage, the adder circuit being configured to generate a sum signal based on a sum of a reference voltage level and the programmable offset voltage;
a loop comparator circuit having a first comparator node coupled to the output node and configured to receive the regulated output voltage and a second comparator node coupled to the adder circuit and configured to receive the sum signal, the loop comparator circuit configured to generate a comparison signal having a first logic value in response to the regulated output voltage reaching a level of the sum signal and having a second logic value in response to the regulated output voltage failing to reach the level of the sum signal;
wherein, in a first operating mode, the PWM signal generator is configured to repeat the following switching phases for each switching cycle of a sequence of switching cycles:
for a first switching phase, generate the PWM signal having a first logic value, and
for a subsequent second switching phase, generate the PWM signal having a second logic value, wherein, in the first operating mode, the PWM generator is configured to determine the duration of the first switching phase or the second switching phase based on the error signal,
wherein, in a second operating mode, the PWM generator is configured to determine the duration of the first switching phase or the second switching phase based on the comparison signal;
the control circuit further comprising: a feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator, the feedback circuit configured to receive the comparison signal, receive the PWM signal, and to provide the digital word signal to the programmable voltage generator, the feedback circuit comprising: flagging circuitry configured to measure a difference between the duration of at least one of the first switching phase or the second switching phase between consecutive switching cycles of the sequence of switching cycles during the first operating mode and to generate a flag signal having the first logic value in response to the measured difference reaching a threshold value and having the second logic value in response to the measured difference failing to reach the threshold value; and
logic circuitry configured to, based on at least one of the flag signal or the comparison signal, increase or decrease the digital word signal with respect to a preset digital word value, and vary the offset voltage generated by the programmable voltage generator.
9. The electronic converter system of claim 8, wherein the logic circuitry is configured to:
increase a digital word value of the control signal in response to the flag signal having the first value and the comparison signal having the second value over an entire switching cycle; and
decrease the digital word value of the control signal in response to the flag signal having the first value and the comparison signal having the first value over an entire switching cycle.
10. The electronic converter of claim 9, wherein, during the first operating mode, the logic circuitry is configured to: in response to the flag signal having the first logic value and the comparison signal having the second logic value over an entire switching cycle, increase the digital word value of the digital word signal;
in response to the flag signal having the first logic value and the comparison signal having the first logic value over an entire switching cycle, decrease the digital word value of the digital word signal; and in response to the flag signal having the second logic value, store the digital word value of the digital word signal.
10.
The electronic converter system of claim 8, wherein the control signal comprises a digital
word signal, and the logic circuitry is configured to increase or decrease the digital word signal with respect to a preset digital word value.
9.
… logic circuitry configured to, based on at least one of the flag signal or the comparison signal, increase or decrease the digital word signal with respect to a preset digital word value, and vary the offset voltage generated by the programmable voltage generator.
11.
The electronic converter system of claim 8, wherein the feedback circuit is coupled to the comparator, the PWM signal generator, and the programmable circuit, and is configured to receive the comparison signal, receive the PWM signal, and provide the control signal to the programmable circuit.
9.
… the control circuit further comprising: a feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator, the feedback circuit configured to receive the comparison signal, receive the PWM signal, and to provide the digital word signal to the programmable voltage generator,…
12.
The electronic converter system of claim 8, further comprising an adder circuit
configured to generate the reference level based on a sum of a reference voltage and the offset value.
9.
… an adder circuit coupled to the programmable voltage generator and configured to receive the programmable offset voltage, the adder circuit being configured to generate a sum signal based on a sum of a reference voltage level and the programmable offset voltage;…
13.
The electronic converter system of claim 8, wherein the programmable circuit comprises
a programmable voltage generator configured to generate the offset value as a programmable offset voltage.
9.
… a programmable voltage generator configured to generate a programmable offset voltage based on a digital word signal;…
14.
The electronic converter system of claim 8, further comprising an error amplifier
configured to generate the error signal based on a difference between a reference voltage and the output voltage.
9.
… an error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to the reference voltage, the error amplifier configured to generate an error signal based on a difference between the reference voltage and the regulated output voltage;…
15.
A method for controlling a switching stage of an electronic converter, the method
comprising:
generating a PWM signal to drive the switching stage,
wherein generating the PWM signal includes, in a first operating mode, repeating the following switching phases for each
switching cycle of a sequence of switching cycles: for a first switching phase, generating the PWM signal having a first logic value, and
for a subsequent second switching phase, generating the PWM signal having a
second logic value;
generating the PWM signal based on an error signal in a first operating mode;
generating the PWM signal based on a comparison signal in a second operating mode, the comparison signal being based on a comparison between an output voltage and a reference level adjusted by an offset value;
measuring a difference between the duration of at least one of the first switching phase
or the second switching phase between consecutive switching cycles during the first operating mode;
generating a flag signal based on the measured difference; and
adjusting the offset value based on at least one of the flag signal or the comparison
signal.
17.
A method, comprising:
generating, by a pulse-width modulated (PWM) signal generator of a control circuit of an electronic converter, a PWM signal and providing the PWM signal to a switching stage of the electronic converter, the switching stage configured to provide a regulated output voltage at an output node based on an input voltage received at an input node, the switching stage configured to be coupled to a reactive network referred to ground, the generating the PWM signal including: in a first operating mode, repeating the following switching phases for each switching cycle of a sequence of switching cycles: for a first switching phase, generating the PWM signal having a first logic value, and for a subsequent second switching phase, generating the PWM signal having a second logic value;
determining, by the PWM generator in the first operating mode, a duration of the first switching phase or the second switching phase based on an error signal;
determining, by the PWM generator in a second operating mode, the duration of the first switching phase or the second switching phase based on a comparison signal;
generating, by an error amplifier of the control circuit, the error signal based on a difference between a reference voltage and the regulated output voltage, the error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to the reference voltage;
generating, by a programmable voltage generator of the control circuit, a programmable offset voltage based on a digital word signal;
generating, by an adder circuit of the control circuit, a sum signal based on a sum of a reference voltage level and the programmable offset voltage;
generating, by a loop comparator circuit of the control circuit having a first comparator node coupled to the output node and configured to receive the regulated output voltage and a second comparator node coupled to the adder circuit and configured to receive the sum signal, the comparison signal having a first logic value in response to the regulated output voltage reaching a level of the sum signal and having a second logic value in response to the regulated output voltage failing to reach the level of the sum signal;
providing, by a feedback circuit of the control circuit, the digital word signal to the programmable voltage generator, the feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator;
measuring, by flagging circuitry of the feedback circuit, a difference between the duration of at least one of the first switching phase or the second switching phase between consecutive switching cycles of the sequence of switching cycles during the first operating mode;
generating, by the flagging circuitry, a flag signal having the first logic value in response to the measured difference reaching a threshold value and having the second logic value in response to the measured difference failing to reach the threshold value;
and varying the offset voltage generated by the programmable voltage generator by increasing or decreasing the digital word signal with respect to a preset digital word value by logic circuitry of the feedback circuit based on at least one of the flag signal or the comparison signal.
16.
The method of claim 15, wherein generating the flag signal comprises generating the flag
signal having a first logic value in response to the measured difference reaching a threshold value and having a second logic value in response to the measured difference failing to reach the threshold value.
17.
… generating, by the flagging circuitry, a flag signal having the first logic value in response to the measured difference reaching a threshold value and having the second logic value in response to the measured difference failing to reach the threshold value;…
17.
The method of claim 15, wherein adjusting the offset value comprises increasing or
decreasing a digital word signal with respect to a preset digital word value to vary the offset value.
17.
… and varying the offset voltage generated by the programmable voltage generator by increasing or decreasing the digital word signal with respect to a preset digital word value by logic circuitry of the feedback circuit based on at least one of the flag signal or the comparison signal.
18.
The method of claim 15, further comprising receiving the comparison signal and the
PWM signal by a feedback circuit coupled to a comparator circuit, the PWM signal generator, and a voltage generator.
17.
… providing, by a feedback circuit of the control circuit, the digital word signal to the programmable voltage generator, the feedback circuit coupled to the loop comparator circuit, the PWM signal generator, and the programmable voltage generator; …
19.
The method of claim 15, wherein the reference level is generated by adding a reference voltage and the offset value.
17.
… generating, by an adder circuit of the control circuit, a sum signal based on a sum of a reference voltage level and the programmable offset voltage;…
20.
The method of claim 15, further comprising generating the error signal based on a
difference between a reference voltage and the output voltage.
17.
… generating, by an error amplifier of the control circuit, the error signal based on a difference between a reference voltage and the regulated output voltage, the error amplifier having a first error amplifier node coupled to the output node and configured to receive the regulated output voltage, and a second error amplifier node coupled to the reference voltage;…
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Borghese (US 12,375,068) is the parent of the instant application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CASSANDRA F COX/Primary Examiner, Art Unit 2836
Prosecution Insights