Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Preliminary Amendment
Applicant's amendment, filed September 03, 2025 are respectfully acknowledged and have been fully considered.
Claim 1 is cancelled. Claims 2-15 are newly added.
Claims 2-15 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-4, 7, 9-11, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hokazono et al. (U.S. Patent Application 20140132175 A1, hereinafter “Hokazono”).
Regarding Claim 2 (New), Hokazono teaches a display device (par 0070 Fig 4 display device) comprising:
a light emitting element (par 0071 Figs 3,6D ELP);
a first capacitor (par 0071 Figs 1,3,6D capacitor C1);
a second capacitor (par 0090 Figs 1,3,6D a parasitic capacitance exists between facing diffusion areas 34 and 25 of the driving transistor TRDrv and of the sampling transistor TRSig);
a sampling transistor configured to supply a data signal voltage corresponding to a data signal to the first capacitor according to a control signal supplied from a control signal line (par 0090 Figs 1,3,6D sampling transistor TRSig supplies a data signal voltage from signal line DTL to capacitor C1 according to the scan signal on scan line SCL); and
a driving transistor configured to supply a driving current from a power potential to the light emitting element according to a voltage stored in the first capacitor (paras 0106,0107 Figs 1,3,6D driving transistor TRDrv supplies current from a power potential Vcc to the ELP corresponding according to the voltage stored in the first capacitor C1), wherein
a first electrode of the first capacitor is disposed in a first layer and is electrically connected to a gate of the driving transistor (par 0092 Figs 1,3,6D first electrode 42 of the first capacitor C1 corresponds to the driving gate electrode 21 and is disposed in a first layer on dielectric layer (insulating layer) 43 and is electrically connected to gate electrode 21 of the driving transistor TRDrv),
a second electrode of the first capacitor is disposed in a second layer different from the first layer and is electrically connected to a first source/drain of the driving transistor (par 0092 Figs 1,3,6D second electrode 41 of the first capacitor C1 is disposed in a second layer, above insulating layer 61),
a first electrode of the second capacitor is disposed in a third layer different from the first layer and the second layer, and is electrically connected to the first source/drain of the driving transistor (par 0090 Figs 1,3,6D a parasitic capacitance exists between facing diffusion areas 34 of the driving transistor TRDrv and 25 of the sampling transistor TRSig, the parasitic capacitance, such that a first electrode of the parasitic capacitance is disposed in a third layer [through isolation region layer 14] different from the first layer and the second layer, and is electrically connected to the first source/drain 23 of the driving transistor TRDrv),
a first source/drain of the sampling transistor is disposed closer to the first source/drain of the driving transistor than to a second source/drain of the driving transistor (par 0119 Fig 1,3,6D first source/drain 34 of the sampling transistor TRSig is disposed closer to the first source/drain 23 of the driving transistor TRDrv than to a second source/drain 24 of the driving transistor TRDrv),
the first source/drain of the sampling transistor being electrically connected to the gate of the driving transistor (par 0119 Fig 1,3,6D first source/drain 34 of the sampling transistor TRSig being electrically connected to the gate 21 of the driving transistor TRDrv), the first source/drain of the driving transistor being electrically connected to the power potential (par 0127,0234 Fig 1,3,6D first source/drain 23 of the driving transistor TRDrv electrically connected to the power potential Vcc, e.g. par 0121 Fig 6D when TREL on), and
the second source/drain of the driving transistor being electrically connected to an anode of the light emitting element (par 0107 Figs 1,3,6D second source/drain 24 of the driving transistor TRDrv electrically connected to an anode 51 of the light emitting element ELP),
at least a portion of a wiring path is adjacent to at least a portion of the power potential, the wiring path being electrically connecting the first source/drain of the sampling transistor and the gate of the driving transistor (par 0119 Fig 1,3,6D at least a portion of a wiring path 42 is vertically adjacent to at least a portion of the power potential Vcc path CSL1, the wiring path 42 being electrically connecting first source/drain 34 of the sampling transistor TRSig and the gate 21 of the driving transistor TRDrv), and
at least a portion of the power potential overlaps the gate of the driving transistor in a plan view (par 0119 Fig 1 at least a portion of the power potential Vcc path CSL1 overlaps the gate 21 of the driving transistor TRDrv in a plan view).
Regarding Claim 3 (New), Hokazono teaches the display device according to claim 2, wherein
the wiring path is electrically connected to the first electrode of the first capacitor (par 0092 Figs 1,3,6D the wiring path 41 is electrically connected to first electrode 42 of the first capacitor C1).
Regarding Claim 4 (New), Hokazono teaches the display device according to claim 2, wherein
a channel length direction of the sampling transistor and a channel length direction of the driving transistor are a same direction (Fig 1 teaches both channel lengths are a same first direction).
Regarding Claim 7 (New), Hokazono teaches the display device according to claim 2, wherein
a second electrode of the second capacitor is disposed in the third layer (par 0090 Figs 1,3,6D a parasitic capacitance exists between facing diffusion areas 34 of the driving transistor TRDrv and 25 of the sampling transistor TRSig, such that a second electrode of the parasitic capacitance is disposed in the third layer).
Regarding Claim 9 (New), Hokazono teaches an electronic device comprising the display device according to claim 2 (par 0158 electronic device comprising a game machine including the display device).
Regarding Claim 10 (New), Hokazono teaches the electronic device according to claim 9, wherein
the wiring path is electrically connected to the first electrode of the first capacitor (par 0092 Figs 1,3,6D the wiring path 41 is electrically connected to first electrode 42 of the first capacitor C1).
Regarding Claim 11 (New), Hokazono teaches the electronic device according to claim 9, wherein
a channel length direction of the sampling transistor and a channel length direction of the driving transistor are a same direction (Fig 1 teaches both channel lengths are a same first direction).
Regarding Claim 14 (New), Hokazono teaches the electronic device according to claim 9, wherein
a second electrode of the second capacitor is disposed in the third layer (par 0090 Figs 1,3,6D a parasitic capacitance exists between facing diffusion areas 34 of the driving transistor TRDrv and 25 of the sampling transistor TRSig, such that a second electrode of the parasitic capacitance is disposed in the third layer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hokazono et al. (U.S. Patent Application 20140132175 A1, hereinafter “Hokazono”) in view of Heo (U.S. Patent Application 20120205647 A1).
Regarding Claim 5, Hokazono teaches the display device according to claim 2. However, Hokazono appears not to expressly teach wherein the first capacitor is a MIM (Metal-Insulator-Metal) capacitor.
Heo teaches wherein the first capacitor is a MIM (Metal-Insulator-Metal) capacitor (par 0052 Fig 3A source/drain electrode 20 of the capacitor region Cst forms a metal-insulator-metal (MIM) capacitor together with the gate electrode 16 thereunder).
Hokazono and Heo are analogous art as they each pertain to OLED display driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the first capacitor of Hokazono with the inclusion of the metal electrodes of Heo. The motivation would have been in order to provide an OLED display in a simplified process [fewer mask steps] while minimizing parasitic capacitance (Heo paras 0017,0076, Fig. 7).
Regarding Claim 12 (New), Hokazono teaches the electronic device according to claim 9. However, Hokazono appears not to expressly teach wherein the first capacitor is a MIM (Metal-Insulator-Metal) capacitor.
Heo teaches wherein the first capacitor is a MIM (Metal-Insulator-Metal) capacitor (par 0052 Fig 3A source/drain electrode 20 of the capacitor region Cst forms a metal-insulator-metal (MIM) capacitor together with the gate electrode 16 thereunder).
Hokazono and Heo are analogous art as they each pertain to OLED display driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the first capacitor of Hokazono with the inclusion of the metal electrodes of Heo. The motivation would have been in order to provide an OLED display in a simplified process [fewer mask steps] while minimizing parasitic capacitance (Heo paras 0017,0076, Fig. 7).
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hokazono et al. (U.S. Patent Application 20140132175 A1, hereinafter “Hokazono”) in view of Park et al. (U.S. Patent Application 20140367664 A1, hereinafter “Park”).
Regarding Claim 6, Hokazono teaches the display device according to claim 3. However, Hokazono appears not to expressly teach wherein the gate electrode of the driving transistor is disposed in the first layer.
Park teaches wherein the gate electrode of the driving transistor is disposed in the first layer (Park par 0148 Figs 5,7 first electrode 158 of the first storage capacitor Cst/80 corresponds to the driving gate electrode 154b and is disposed in a first driving gate electrode layer on gate insulating layer 140 and is electrically connected to gate electrode 154b of the driving transistor Qd).
Hokazono and Park are analogous art as they each pertain to OLED display driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the gate electrode of the driving transistor is disposed in the first layer of Park. The motivation would have been in order to provide that an area of the storage capacitor Cst may be reduced. Accordingly, it is possible to prevent reduction in aperture ratio of the display device due to the formation of the storage capacitor Cst (Park par 0148).
Regarding Claim 13 (New), Hokazono teaches the electronic device according to claim 9. However, Hokazono appears not to expressly teach wherein the gate of the driving transistor is disposed in the first layer.
Park teaches wherein the gate of the driving transistor is disposed in the first layer (Park par 0148 Figs 5,7 first electrode 158 of the first storage capacitor Cst/80 corresponds to the driving gate electrode 154b and is disposed in a first driving gate electrode layer on gate insulating layer 140 and is electrically connected to gate electrode 154b of the driving transistor Qd).
Hokazono and Park are analogous art as they each pertain to OLED display driving circuits. It would have been obvious to a person of ordinary skill in the art to modify the device of Park with the inclusion of the gate of the driving transistor is disposed in the first layer of Park. The motivation would have been in order to provide that an area of the storage capacitor Cst may be reduced. Accordingly, it is possible to prevent reduction in aperture ratio of the display device due to the formation of the storage capacitor Cst (Park par 0148).
Allowable Subject Matter
Claims 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8:
While closest prior art Hokazono (20140132175 A1) teaches portions of the limitations of Claim 8, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 8, namely "wherein a second electrode of the second capacitor is electrically connected to the power potential" in combination with all other limitations of the claim and of claims on which the claim depends.
Claim 15:
While closest prior art Hokazono (20140132175 A1) teaches portions of the limitations of Claim 15, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 15, namely "wherein a second electrode of the second capacitor is electrically connected to the power potential" in combination with all other limitations of the claim and of claims on which the claim depends.
Conclusion
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/MARK EDWARDS/Primary Examiner, Art Unit 2624