DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
An information disclosure statement (IDS) was submitted on 30 June 2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-4 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3-4 and 18-19 recites the limitation "a second operation mode " and “the second operation mode”. Claims 1 and 12 also recites "a second operation mode " and “the second operation mode”, it is unclear if they are all the same “second operation mode”. Examiner interprets them to be all the same “second operation mode” for purposes of examination and suggests Applicant amend the claims for clarification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 7, 9-12, 14-16, 18, 20, 22, 24, and 25 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lee (US 20220035545 A1).
Referring to claims 1 and 12, taking claim 1 as exemplary, Lee teaches
A method for configuring a microcontroller: ([Lee abstract, 0006, 0022, Fig. 1] micro controller unit (MCU))
storing in at least one non-volatile memory: ([Lee abstract, 0006, 0022, Fig. 1] flash memory)
secret data comprising a first set of security configurations, ([Lee 0007-0009, 0030-0033, Fig. 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. the application block 22 can operate the software stored in the application area)
a second set of security configurations, ([Lee 0007-0009, 0030-0033, 0035, Fig. 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. the application key block 23 erases and resets an application key area corresponding to the active application. the application key block 23 writes a valid key value into an area corresponding to the application) and
a state of the microcontroller selected out of a first value indicative of a first operation mode of the microcontroller, ([Lee 0006, 0012, 0040, Fig. 3] when the MCU is powered on, determining, by the flash boot loader, an application key value in the application key block. The FBL 21 may determine whether a key value of an application that needs to be operated according to a command of the processor is valid (step S2).) a second value indicative of a transition from the first operation mode to a second operation mode, ([Lee 0048, Fig. 3] When the key value of the application is invalid as a determination result of the step S2) and a third value indicative of the second operation mode of the microcontroller; ([Lee 0048-0053, Fig. 3] When the key value of the application is invalid as a determination result of the step S2, a command may stay in the FBL 21 (step S8). That is, the flash memory 2 enters the FBL mode. When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11).)
if the state of the microcontroller is equal to the first value, operating the microcontroller in the first operation mode using the first set of security configurations; ([Lee 0041-0042, Fig. 3] When the key value of the corresponding application is valid as a result of the step S2, the command may be transmitted to the application block 22 from the FBL 21 (step S3). The application block 22 may perform the corresponding application according to the command (step S4).)
if the state of the microcontroller is equal to the second value, erasing the secret data and operating the microcontroller in the second operation mode using the second set of security configurations; ([Lee 0031-0033, 0048-0053, Fig. 3] In an FBL mode where commands stay in the FBL 21, the FBL 21 may erase software in an application area of the flash memory 2 and perform reprogramming. When the key value of the application is invalid as a determination result of the step S2, a command may stay in the FBL 21 (step S8). That is, the flash memory 2 enters the FBL mode. When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11). After the step S11, soft reset may be carried out (step S12). After the soft reset, the flash memory 2 enters the FBL mode according to the step S1 and then the process may be carried out from the step S2 again.) and
if the state of the microcontroller is equal to the third value, operating the microcontroller in the second operation mode using the second set of security configurations ([Lee 0031-0033, 0048-0053, Fig. 3] When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11). After the step S11, soft reset may be carried out (step S12). After the soft reset, the flash memory 2 enters the FBL mode according to the step S1 and then the process may be carried out from the step S2 again.).
With regards to the non-exemplary limitations of claim 12, Lee teaches a manager unit ([Lee 0057, Fig. 4] As shown in FIG. 4, a battery device 100 includes an MCU 120, and the MCU 120 may store a plurality of applications required for battery monitoring and management.) wherein said manager unit is configured to configure the microcontroller ([Lee 0057, Fig. 4] As shown in FIG. 4, a battery device 100 includes an MCU 120, and the MCU 120 may store a plurality of applications required for battery monitoring and management.).
Referring to claims 3 and 18, taking claim 3 as exemplary, Lee teaches
The method according to claim 1, further comprising storing a second operation mode enabling variable indicating to enable or to disable the second operation mode of the microcontroller in said at least one non-volatile memory ; ([Lee abstract, 0031-0033, 0048-0053, Fig. 3] the flash memory enters a mode that enables reprogramming of the flash memory. In an FBL mode where commands stay in the FBL 21, the FBL 21 may erase software in an application area of the flash memory 2 and perform reprogramming. When the key value of the corresponding application is valid as a result of the step S2, the command may be transmitted to the application block 22 from the FBL 21 (step S3). When the key value of the application is invalid as a determination result of the step S2, a command may stay in the FBL 21 (step S8).) wherein the state of the microcontroller is set to the first value; ([Lee 0006, 0012, 0040, Fig. 3] when the MCU is powered on, determining, by the flash boot loader, an application key value in the application key block. The FBL 21 may determine whether a key value of an application that needs to be operated according to a command of the processor is valid (step S2).) and further comprising: in response to the second operation mode enabling variable indicating to enable the second operation mode, setting the state of the microcontroller to the second value; and in response to said erasing of the secret data, setting the state of the microcontroller to the third value ([Lee 0031-0033, 0048-0053, Fig. 3] In an FBL mode where commands stay in the FBL 21, the FBL 21 may erase software in an application area of the flash memory 2 and perform reprogramming. When the key value of the application is invalid as a determination result of the step S2, a command may stay in the FBL 21 (step S8). That is, the flash memory 2 enters the FBL mode. When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11). After the step S11, soft reset may be carried out (step S12). After the soft reset, the flash memory 2 enters the FBL mode according to the step S1 and then the process may be carried out from the step S2 again.).
Referring to claims 5 and 20, taking claim 5 as exemplary, Lee teaches
The method according to claim 1, further comprising storing a third operation mode enabling variable indicating to enable or to disable a third operation mode of the microcontroller in said at least one non-volatile memory, said third operation mode being related to an unusable state of the microcontroller; ([Lee 0025, 0048-0053, Fig. 3] The flash memory 2 stores an application that is required by a device to which the MCU 1 is applied, executes software of the application, reprograms the corresponding software when reprogramming is requested, and deletes and resets an application key area when a CPU core exception occurs (i.e. unusable state) due to an ECC error and the error has occurred in the key application area such that the flash memory 2 may operate in a state of being capable of reprogramming. When the key value of the application is invalid as a determination result of the step S2, a command may stay in the FBL 21 (step S8). That is, the flash memory 2 enters the FBL mode. In this case, a CPU core exception due to an ECC error may occur. When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11).)
further comprising in response to the third operation mode enabling variable indicating to enable the third operation mode, operating the microcontroller in the third operation mode ([Lee 0031-0033, 0048-0053, Fig. 3] When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11). After the step S11, soft reset may be carried out (step S12). After the soft reset, the flash memory 2 enters the FBL mode according to the step S1 and then the process may be carried out from the step S2 again.).
Referring to claims 7, 15, 16, and 22, taking claim 7 as exemplary, Lee teaches
The method according to claim 1, wherein said microcontroller is embedded in a battery, in particular, a vehicle battery, and is configured to manage said battery ([Lee 0016, Fig. 4] A battery device according to another aspect of the present invention includes: a battery cell assembly that includes a plurality of battery cells that are electrically connected to each other, a micro controller unit (MCU) that includes a flash memory, the flash memory being configured to store an application for battery management of the battery cell assembly; and a battery management system that performs the battery management according to the application executed by the MCU. Examiner notes a vehicle battery is intended use, batteries serve many purposes and can be implemented/used in varied products and applications including vehicles.).
Referring to claims 9 and 24, taking claim 9 as exemplary, Lee teaches
The method according to claim 1, wherein said first set of security configurations comprises data used to configure the microcontroller during a boot of the microcontroller or in response to a reset or a power-on operation ([Lee abstract, 0006, 0012, 0040, Fig. 3] when the MCU is powered on, determining, by the flash boot loader).
Referring to claim 10, Lee teaches
The method according to claim 9, wherein said data used to configure the microcontroller comprises security functions of the microcontroller ([Lee 0007-0009, 0030-0033, Fig. 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. the application block 22 can operate the software stored in the application area).
Referring to claims 11 and 25, taking claim 11 as exemplary, Lee teaches
The method according to claim 1, wherein said microcontroller is a secure microcontroller (Examiner notes this is intended use however [Lee 0007-0009, 0030-0033, 0063, Fig. 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. the application block 22 can operate the software stored in the application area, protection operation).
Referring to claim 14, Lee teaches
The microcontroller according to claim 12, wherein said manager unit comprises:
a register interface used to access memory locations in said at least one non-volatile memory; ([Lee abstract, 0026, Figs. 1, 2] The processor 3 may transmit information input through the peripheral device 4 to the flash memory 2 while networking with the flash memory 2 and the peripheral device 4 through an interface, and may transmit commands to control operations of the flash memory 2 and the peripheral device 4. When the MCU 1 is powered on, a power-on signal P_ON is input to the processor 3, and the processor 3 transmits commands for execution of an application to the flash memory 2.)
at least one non-volatile memory interface used to perform memory reading, writing, and erasing operations; ([Lee abstract, 0026, 0029-0031, Figs. 1, 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. In an FBL mode where commands stay in the FBL 21, the FBL 21 may erase software in an application area of the flash memory 2 and perform reprogramming. The processor 3 may transmit information input through the peripheral device 4 to the flash memory 2 while networking with the flash memory 2 and the peripheral device 4 through an interface, and may transmit commands to control operations of the flash memory 2 and the peripheral device 4. When the MCU 1 is powered on, a power-on signal P_ON is input to the processor 3, and the processor 3 transmits commands for execution of an application to the flash memory 2.) and/or a configuration interface used to select the first operation mode using the first set of security configurations or the second operation mode using the second set of security configurations ([Lee abstract, 0026, 0029-0031, 0038-0040, Figs. 1, 2, 3] FIG. 3 is a flowchart of a restoring method according to an exemplary embodiment. As shown in FIG. 3, the MCU 1 may be powered on or reset (step S1). The FBL 21 may determine whether a key value of an application that needs to be operated according to a command of the processor is valid (step S2). As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. In an FBL mode where commands stay in the FBL 21, the FBL 21 may erase software in an application area of the flash memory 2 and perform reprogramming. The processor 3 may transmit information input through the peripheral device 4 to the flash memory 2 while networking with the flash memory 2 and the peripheral device 4 through an interface, and may transmit commands to control operations of the flash memory 2 and the peripheral device 4. When the MCU 1 is powered on, a power-on signal P_ON is input to the processor 3, and the processor 3 transmits commands for execution of an application to the flash memory 2.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 6, 13, 17, 19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220035545 A1) as applied to claims 1 and 12 above, and further in view of Aune (US 20210240870 A1).
Referring to claims 2 and 17, taking claim 2 as exemplary, Lee teaches
The method according to claim 1 ([see above]).
Lee does not explicitly disclose wherein said erasing of the secret data is performed via an atomic operation.
Aune teaches wherein said erasing of the secret data is performed via an atomic operation ([Aune 0040] In this case, though, the device preferably comprises erase logic that prevents any address register from being erased unless the key register associated with the address register is also erased (which could mean previously erased, or simultaneously erased with the key register in a common erase operation). The erase logic may require that the entire key storage memory be erased in a single erase operation (i.e., an atomic operation), such that every key is guaranteed to be wiped before any address register can be written to again.).
Lee and Aune are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee and Aune before him or her to modify the flash memory of Lee to include the erase logic of Aune, thereafter the flash memory is connected to erase logic. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory have ability to erase entire key in single erase operation as suggested by Aune. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee with Aune to obtain the invention as specified in the instant application claims.
Referring to claims 4 and 19, taking claim 4 as exemplary, Lee teaches
The method according to claim 3, wherein: the second operation mode enabling variable indicates to disable the second operation mode; ([Lee 0048, Fig. 3] When the key value of the application is invalid as a determination result of the step S2).
Lee does not explicitly disclose and said second operation mode enabling variable is set to indicate to enable the second operation mode by a user.
Aune teaches and said second operation mode enabling variable is set to indicate to enable the second operation mode by a user ([Aune 0028, 0039] In this way, a manufacturer, distributer or user of the integrated-circuit device can decide precisely how many keys to store for any particular destination address on the device, without this being predetermined by the physical design of the integrated-circuit device. The write-once logic may also prevent a cryptographic key being written to the key register unless the key register is in an erased state. In this way, a manufacturer or distributer or user may write one or more cryptographic keys once during a configuration phase (e.g., by writing the key over the system bus using a secure bootloader, or secure-mode software, executing on the processor, or via a debug or test interface), and thereafter prevent any modifications to the keys.).
Lee and Aune are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee and Aune before him or her to modify the flash memory of Lee to include the key storage memory and key management unit of Aune, thereafter the flash memory is connected to key storage memory and key management unit. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory have user decide precisely how many keys to store as suggested by Aune. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee with Aune to obtain the invention as specified in the instant application claims.
Referring to claims 6 and 21, taking claim 6 as exemplary, Lee teaches
The method according to claim 5, wherein:
the third operation mode enabling variable indicates to disable the third operation mode; ([Lee 0031-0033, 0048-0053, Fig. 3] When the flash memory 2 receives data for reprogramming from the processor 3, the FBL 21 may reprogram an application area (step S9). When it determined that the reprogramming is completed in the step S10, the application key block 23 may write a valid application key value (step S11). After the step S11, soft reset may be carried out (step S12). After the soft reset, the flash memory 2 enters the FBL mode according to the step S1 and then the process may be carried out from the step S2 again.). Lee does not explicitly teach and said third operation mode enabling variable is set to indicate to enable the third operation mode by a user.
Aune teaches and said third operation mode enabling variable is set to indicate to enable the third operation mode by a user ([Aune 0028, 0039] In this way, a manufacturer, distributer or user of the integrated-circuit device can decide precisely how many keys to store for any particular destination address on the device, without this being predetermined by the physical design of the integrated-circuit device. The write-once logic may also prevent a cryptographic key being written to the key register unless the key register is in an erased state. In this way, a manufacturer or distributer or user may write one or more cryptographic keys once during a configuration phase (e.g., by writing the key over the system bus using a secure bootloader, or secure-mode software, executing on the processor, or via a debug or test interface), and thereafter prevent any modifications to the keys.).
Lee and Aune are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee and Aune before him or her to modify the flash memory of Lee to include the key storage memory and key management unit of Aune, thereafter the flash memory is connected to key storage memory and key management unit. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory have user decide precisely how many keys to store as suggested by Aune. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee with Aune to obtain the invention as specified in the instant application claims.
Referring to claim 13, Lee teaches
The microcontroller according to claim 12 (see above).
Lee does not explicitly disclose wherein said manager unit is implemented via a finite state machine.
Aune teaches wherein said manager unit is implemented via a finite state machine ([Aune 0068] Access control to the key storage memory 12a is enforced by a hardware Finite State Machine (FSM) that can allow or block transactions depending both on the security of the transaction (Secure or Non-Secure) and the type of register being written and/or read. Access control can be configured individually for each key slot; the FSM operates on only one key slot at a time, and the read permissions and usage restrictions for the key value associated with the key slot can be set individually.).
Lee and Aune are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee and Aune before him or her to modify the flash memory of Lee to include the key storage memory and key management unit of Aune, thereafter the flash memory is connected to key storage memory and key management unit. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory have ability to allow access control to be configured individually for each key as suggested by Aune. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee with Aune to obtain the invention as specified in the instant application claims.
Claim(s) 8 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20220035545 A1) as applied to claims 1 and 12 above, and further in view of Aune (US 20210240870 A1) and Chew (US 20110154478 A1).
Referring to claims 8 and 23, taking claim 8 as exemplary, Lee teaches
The method according to claim 1 (see above) and said first set of security configurations ([Lee 0007-0009, 0030-0033, Fig. 2] As shown in FIG. 2, the flash memory 2 includes a flash bootloader (FBL) 21, an application block 22, and an application key block 23. the application block 22 can operate the software stored in the application area).
Lee does not explicitly disclose wherein said at least one non-volatile memory comprises a Hardware Security Module, HSM, and wherein said secret data comprises: cryptographic keys; a set of passwords.
Aune teaches wherein said at least one non-volatile memory comprises a Hardware Security Module, HSM, and wherein said secret data comprises: cryptographic keys ([Aune abstract, 0002-0007, 0029, 0068] The hardware key-storage system comprises a non-volatile key storage memory, which includes a key register, for storing a cryptographic key, and an address register, for storing a destination memory address for the cryptographic key. approach provides increased security for the cryptographic keys).
Lee and Aune are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee and Aune before him or her to modify the flash memory of Lee to include the key storage memory and key management unit of Aune, thereafter the flash memory is connected to key storage memory and key management unit. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory have ability to allow access control to be configured individually for each key as suggested by Aune. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee with Aune to obtain the invention as specified in the instant application claims.
Lee in view of Aune does not explicitly disclose a set of passwords.
Chew teaches a set of passwords ([Chew 0044-0048] The atomic operation can also be accomplished by having a mechanism that takes-in 2 passwords as a single IO operation and then internally write the first (original) password into NEW_USER_PWD_REG 420, and the second (new) password into DEV_PWD_REG 415.).
Lee, Aune, and Chew are analogous art because they are from the same field of endeavor in memory systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lee, Aune, and Chew before him or her to modify the flash memory of Lee and Aune to include the password support of Chew, thereafter the flash memory is connected to password support. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the flash memory to have password protected storage as suggested by Chew. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lee and Aune with Chew to obtain the invention as specified in the instant application claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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