Notice of Pre-AIA or AIA Status
DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application 19/255,301 filed on 6/30/2025, which is a continuation of application 18/660.070 filed on 5/9/2024, which is a continuation of application 17/396,529 filed on 8/6/2021 which claims priority to 63/068,044 filed on 8/20/2020.
Claims 1-20 have been examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 6-11, 13-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanbe (US 2020/0244458), and Teegavarapu et al. (US 2017/0262626).
With respect to claim 1, Kanbe teaches of a memory system, comprising: one or more memory devices (fig. 1; paragraph 22, 24; SSD containing NAND flash memory); and
one or more controllers coupled with the one or more memory devices (fig. 1; paragraph 22, 28-29, 35; the controller is connected to the NAND flash via the NAND interface) and
configured to cause the memory system to: receive, at a memory device of the one or more memory devices, an identifier of a host device (fig. 12; paragraph 22, 139-140; where the SSD controller receives an authentication request command from a host containing authentication information of the host)
after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device (fig. 12; paragraph 39, 145; as the SSD controller received the authentication request, it must be presently in a powered on state (claimed second power mode). This powered on state can only be achieved by the SSD being turned on from a powered off state (claimed first power mode)),
the second power mode comprising the first functionality mode and a second functionality mode (fig. 12; paragraph 39, 139, 144-145; When the request is received, no successful authentication and access has yet occurred. This is the dividing line between the claimed first and second functionality modes of the second power mode. The claimed first functionality mode being that an authentication match hasn’t occurred yet and the second claimed functionality mode being that an authentication match and access has occurred);
transmit a first value that is generated based at least in part on the identifier of the host device, the first value comprising a random set of bits (fig. 12; paragraph 61-65, 141; when authentication using the identifier of the host is successful, a temporary authentication code that may be a random number or can be generated using the host identifier and a random number is sent to the host);
receive, in response to transmitting the first value, a signal that comprises a third value (fig. 12; paragraph 67-68, 142-143; where the host requests access to the flash in an access command that includes the encrypted temporary authentication code); and
refrain from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value (fig. 12; paragraph 78, 142-144; a host sends a command to the ssd controller and upon comparing the temporary authentication codes, they do not match and the host is notified of the error and not allowed access to the memory).
Knabe fails to explicitly teach of a fourth value that is generated based at least in part on the first value and a secret stored at the memory device.
However, Teegavarapu teaches of a fourth value that is generated based at least in part on the first value and a secret stored at the memory device (paragraph 23, 32-33, 57-59; where a seed of a random seed table is used to generate host device data. In the combination with Knabe, it is used to generate the temporary authentication code. The random seed table is stored in the host as well as the storage device, thus it is a secret shared between them).
The combination of Knabe and Teegavarapu teaches of refrain from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value and a secret stored at the memory device (Knabe fig. 12; paragraph 78, 142-144; Teegavarapu paragraph 23, 32-33, 57-59; where in the combination the temporary authentication code is generated using random bits via the seed table of Teegavarapu, thus they are compared when the temporary authentication codes are compared).
Kanbe and Teegavarapu are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of Kanbe and Teegavarapu before the time of the effective filing of the claimed invention to encrypt the host commands of Kanbe by using the seed from the seed table of Teegavarapu. Their motivation would have been to make it host and storage more secure (Teegavarapu, paragraph 7-10).
With respect to claim 8, the combination of Kanbe and Teegavarapu teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Kanbe also teaches of receive an access command and a first value associated with an identification of the access command (fig. 12; paragraph 67-68, 142-143; where the host requests access to the flash in an access command that includes the encrypted temporary authentication code); and
The combination of Kanbe and Teegavarapu teaches of refrain from executing the access command based at least in part on determining that the first value is different from a second value generated based at least in part on the first value and a secret stored at the memory device (Knabe fig. 12; paragraph 78, 142-144; Teegavarapu paragraph 23, 32-33, 57-59; where in the combination the temporary authentication code is generated using random bits via the seed table of Teegavarapu, thus they are compared when the temporary authentication codes are compared and when they do not match and the host is notified of the error and not allowed access to the memory).
The reasoning for obviousness is the same as indicated above with respect to claim 1.
With respect to claim 14, the combination of Kanbe and Teegavarapu teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
With respect to claims 2 and 16, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: increment a counter associated with the third value to a first count value based at least in part on determining that the third value is different from the fourth value; and determine that the first count value satisfies a threshold value based at least in part on comparing the third value with the fourth value (paragraph 144; where when the number of successive mismatches is greater than a specific number, the controller will no longer accept read commands. Thus, Kanbe tracks the quantity of mismatch errors and compares it to the specific number in order to determine whether or not to accept read commands in the controller).
With respect to claim 9, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: increment a counter associated with the first value to a first count value based at least in part on determining that the first value is different from the second value; and determine that the first count value satisfies a threshold quantity of invalid access commands based at least in part on comparing the first value with the second value (paragraph 144; where when the number of successive mismatches is greater than a specific number, the controller will no longer accept read commands. Thus, Kanbe tracks the quantity of mismatch errors and compares it to the specific number in order to determine whether or not to accept read commands in the controller).
With respect to claims 3, 10, and 17, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: disable the second functionality mode of the memory device based at least in part on determining that the first count value satisfies the threshold value (paragraph 144; when the number of successive mismatches is greater than a specific number, the controller will no longer accept read commands).
With respect to claims 4, 11, and 18, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: transmit an alert based at least in part on determining that the first count value satisfies the threshold value (paragraph 144; where the host is notified of the errors).
With respect to claim 6, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: generate the fourth value using a randomization process on the first value before receiving the third value (fig. 12; paragraph 64-65, 141-143; where the temporary authentication code is generated and sent to the host, before the controller receives an access request that includes the temporary authentication code).
With respect to claims 7 and 20, Kanbe teaches of wherein the one or more controllers are further configured to cause the memory system to: disable the second functionality mode of the memory device before a process associated with the transition is completed (fig. 12; paragraph 39, 139, 144-145; whereas there has been no successful authentication of a host when the storage is powering on, no authentication has been granted).
With respect to claim 13, Kanbe teaches of wherein the access command and the first value are received concurrently (paragraph 140, 143; where the command contains an authentication code).
With respect to claim 15, Kanbe teaches of receiving, in the signal, an access command and the third value, wherein the third value is associated with an identification of the access command (fig. 12; paragraph 67-68, 142-143; where the host requests access to the flash in an access command that includes the encrypted temporary authentication code for the command); and
refraining from executing the access command based at least in part on refraining from validating the host device (fig. 12; paragraph 78, 142-144; a host sends a command to the ssd controller and upon comparing the temporary authentication codes, they do not match. As they do not match, the host hasn’t been authenticated because it doesn’t have the temporary authentication code. As a result, the host is notified of the error and not allowed access to the memory).
Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanbe and Teegavarapu as applied to claims 2, 9, and 16 above, and further in view of Ueda (US 2007/0017977).
With respect to claims 5, 12, and 19, the combination of Kanbe and Teegavarapu fails to explicitly teach of wherein the one or more controllers are further configured to cause the memory system to: adjust the threshold value based at least in part on one or more events at the memory device.
However, Ueda teaches of wherein the one or more controllers are further configured to cause the memory system to: adjust the threshold value based at least in part on one or more events at the memory device (paragraph 35-37; where after a reboot to clear the lock state, the current upper limit is decreased).
Kanbe, Teegavarapu, Ueda are analogous art because they are from the same field of endeavor, as they are directed to authentication.
It would have been obvious to one of ordinary skill in the art having the teachings of Kanbe, Teegavarapu, Ueda before the time of the effective filing of the claimed invention to reduce the specified limit of successive mismatch errors in the authentication code of the combination of Kanbe and Teegavarapu as taught in Ueda. Their motivation would have been to maintain authentication security when the system is rebooted to avoid the locked state.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 7-11, 13-18, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8-13, and 16-17 of U.S. Patent No. 12,353,755. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,353,755 include the limitations of the rejected claims and thus anticipate the rejected claims.
Claims 14-18 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9-12, 14, 16, and 19 of U.S. Patent No. 12,001,707. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of U.S. Patent No. 12,001,707 include the limitations of the rejected claims and thus anticipate the rejected claims.
Claims 1-4, 7-11, 13 are rejected on the ground of nonstatutory double patenting as being unpatentable via obviousness over claims 1, 9-12, 14, 16, and 19-21 of U.S. Patent No. U.S. Patent No. 12,001,707 in view of Kanbe (US 2020/0244458).
U.S. Patent No. 12,001,707 fails to explicitly claim one or more controllers coupled with the one or more memory devices. However, Kanbe teaches of this in fig. 1, paragraphs 22, 29-30, 35, where the controller is connected to the NAND flash memory trough the NAND interface.
U.S. Patent No. 12,001,707’s claims and Kanbe are analogous art because they are from the same field of endeavor, as they are directed to data storage.
It would have been obvious to one of ordinary skill in the art having the teachings of U.S. Patent No. 12,001,707’s claims and Kanbe before the time of the effective filing of the claimed invention to incorporate the controller of Kanbe into the claims of U.S. Patent No. 12,001,707. Their motivation would have been to more efficiently utilize the storage.
See the chart below for a mapping of the rejected claims.
Application 19/255,301
US 12,353,755
US 12,001,707
Claim 1: A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
Claim 1: A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
Claim 1: A method, comprising: receiving, from a host device at a memory device,
receive, at a memory device of the one or more memory devices, an identifier of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
receive, at a memory device of the one or more memory devices, a first value that is associated with an identification of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
receiving, from a host device at a memory device, a first value that is associated with an identification of the host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode…
transmit a first value that is generated based at least in part on the identifier of the host device, the first value comprising a random set of bits;
receive an access command; suspend executing the access command based at least in part on the memory device operating in the first functionality mode; transmit a second value that is based at least in part on the first value and comprises a random set of bits;
transmitting, to the host device from the memory device, a second value that is based at least in part on the first value and comprises a random set of bits;
receive, in response to transmitting the first value, a signal that comprises a third value; and
receive data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device; enable the second functionality mode of the second power mode of the memory device based at least in part on the encrypted third value; and cease suspension of the access command based at least in part on enabling the second functionality mode.
receiving, from the host device at the memory device, data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device; enabling the second functionality mode of the second power mode of the memory device based at least in part on the encrypted third value; and ceasing suspension of the access command based at least in part on enabling the second functionality mode.
refrain from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value and a secret stored at the memory device.
Claim 1: receive data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device…
Claim 8: wherein the one or more controllers are further configured to cause the memory system to: receive an encrypted fourth value after an event; compare the encrypted fourth value with a stored value generated by an algorithm based at least in part on receiving the encrypted fourth value; and refrain from validating the host device based at least in part on determining that the encrypted fourth value is different than the stored value.
Claim 1: receiving, from the host device at the memory device, data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device…
Claim 9: receiving, from the host device, an encrypted fourth value after an event; comparing the encrypted fourth value with a stored value generated by an algorithm based at least in part on receiving the encrypted fourth value; determining that the encrypted fourth value is different than the stored value based at least in part on the comparison; and refraining from validating the host device based at least in part on determining that the encrypted fourth value is different than the stored value.
Claim 2
Claim 9
Claim 10
Claim 3
Claim 10
Claim 11
Claim 4
Claim 11
Claim 12
Claim 7
Claim 12
Claim 14
Claim 8: A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
Claims 1, 8
Claim 13: A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
Claims 1, 9
Claim 16: A method, comprising: transitioning a memory device
transition a memory device of the one or more memory devices from a first power mode to a first functionality mode of a second power mode, the second power mode comprising the first functionality mode and a second functionality mode;
transition a memory device of the one or more memory devices from a first power mode to a first functionality mode of a second power mode, the second power mode comprising the first functionality mode and a second functionality mode;
transitioning a memory device from a first power mode to a first functionality mode of a second power mode, the second power mode comprising the first functionality mode and a second functionality mode…
receive an access command and a first value associated with an identification of the access command; and
receive an access command and a first value associated with an identification of the access command, the access command triggered by transitioning the memory device from the first power mode to the first functionality mode;
receiving, from the host device, an access command and a first value associated with an identification of the access command, the access command triggered by the transitioning;
refrain from executing the access command based at least in part on determining that the first value is different from a second value generated based at least in part on the first value and a secret stored at the memory device.
Claim 13: suspend executing the access command based at least in part on the memory device operating in the first functionality mode; generate a second value associated with the access command using a randomization process that is based at least in part on a random quantity and a secret shared between a host device and the memory device based at least in part on receiving the access command and the first value…
Claim 16: receive a second access command and a third value associated with the second access command; generate a fourth value associated with the second access command using the randomization process based at least in part on receiving the second access command with the third value; and refrain from executing the second access command based at least in part on determining that the fourth value is different than the third value.
Claim 16: suspending executing the access command based at least in part on the memory device operating in the first functionality mode and the access command being associated with a write operation on the memory device; generating, at the memory device, a second value associated with the access command using a randomization process that is based at least in part on a random quantity and a secret shared between the host device and the memory device based at least in part on receiving the access command and the first value;
Claim 19: receiving, from the host device, a second access command a third value associated with the second access command; generating a fourth value associated with the second access command using the randomization process based at least in part on receiving the second access command with the third value; determining the fourth value is different than the third value based at least in part on generating the fourth value; and refraining from executing the second access command based at least in part on determining that the fourth value is different than the third value.
Claim 9
Claim 9
Claim 20, 21
Claim 10
Claim 10
Claim 21
Claim 11
Claim 11
Claim 12
Claim 13
Claim 17
Claim 22
Claim 14: A method, comprising: receiving, at a memory device of one or more memory devices, an identifier of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
Claims 13, 16
Claim 1: A memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: receive, at a memory device of the one or more memory devices, a first value that is associated with an identification of a host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode;
Claim 16, 19
Claim 1: A method, comprising: receiving, from a host device at a memory device, a first value that is associated with an identification of the host device after a transition from a first power mode of the memory device to a first functionality mode of a second power mode of the memory device, the second power mode comprising the first functionality mode and a second functionality mode…
transmitting a first value that is generated based at least in part on the identifier of the host device, the first value comprising a random set of bits;
transmit a second value that is based at least in part on the first value and comprises a random set of bits;
transmitting, to the host device from the memory device, a second value that is based at least in part on the first value and comprises a random set of bits;
receiving, in response to transmitting the first value, a signal that comprises a third value; and
receive data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device; enable the second functionality mode of the second power mode of the memory device based at least in part on the encrypted third value; and cease suspension of the access command based at least in part on enabling the second functionality mode.
receiving, from the host device at the memory device, data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device; enabling the second functionality mode of the second power mode of the memory device based at least in part on the encrypted third value; and ceasing suspension of the access command based at least in part on enabling the second functionality mode.
refraining from validating the host device based at least in part on determining that the third value is different from a fourth value that is generated based at least in part on the first value and a secret stored at the memory device.
Claim 1: receive data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device…
Claim 8: wherein the one or more controllers are further configured to cause the memory system to: receive an encrypted fourth value after an event; compare the encrypted fourth value with a stored value generated by an algorithm based at least in part on receiving the encrypted fourth value; and refrain from validating the host device based at least in part on determining that the encrypted fourth value is different than the stored value.
Claim 1: receiving, from the host device at the memory device, data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device…
Claim 9: receiving, from the host device, an encrypted fourth value after an event; comparing the encrypted fourth value with a stored value generated by an algorithm based at least in part on receiving the encrypted fourth value; determining that the encrypted fourth value is different than the stored value based at least in part on the comparison; and refraining from validating the host device based at least in part on determining that the encrypted fourth value is different than the stored value.
Claim 15
Claim 13
Claim 16
Claim 16
Claim 9
Claim 10
Claim 17
Claim 10
Claim 11
Claim 18
Claim 11
Claim 12
Claim 20
Claim 12
Claim 14
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Johnson et al. (US 2009/0063802) discloses a dada security system that counts the number of unsuccessful unlocking attempts. When the number of unsuccessful attempts reaches a specified threshold, the unlocking mechanism changes slightly so that every entry fails, even a valid entry. This mechanism prevents unauthorized entry with no feedback to the hacker as to success or failure.
Araki et al (US 2008/0154839) discloses an optical disk drive where the drive operates in a read-only mode once a disk has been inserted and switches to a read/write mode in response to the authentication of the host apparatus (figure 3; paragraphs 69-74).
Cohen (US 2004/0230784) discloses suspending program execution when an invalid instruction is received and resuming execution when the instruction is validated.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138
MICHAEL C. KROFCHECK
Primary Examiner
Art Unit 2138
Prosecution Insights