DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is in response to communications filed 06/30/2025.
Claims 1-19 are pending.
Claims 1-19 are rejected.
The Examiner notes the current action does not include prior art rejections over the current presentation of the claims. The cited relevant prior art references made of record below are considered as pertinent to the claims and disclosed details provided in the Specification.
The claims are subject to the rejections provided herein which must be addressed accordingly.
Examiner’s Note
Claim 20 is herein renumbered and referenced by the Examiner to Claim 19 under rule CFR 1.126 for purposes of compact prosecution in order to address Applicant’s filing error wherein numbering the claims the number 19 is omitted. The Examiner requests Applicant to make appropriate amendments to address the issue in future response.
Priority
Applicant’s priority claim as a continuation of US Application 18/587,593 filed 02/26/2024, now US Patent No. 12,399,644, which claims priority to US Application 17/407,953 filed 08/20/2021, now US Patent No. 11,947,828, which claims priority to provisionally filed application 63/070,907 filed 08/27/2020 is herein acknowledged.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the applicant’s submission of the Information Disclosure Statement dated 07/03/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Drawings
The applicant’s drawings submitted on 06/30/2025 are acceptable for examination purposes.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,947,828, hereinafter referred to as “Patent”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are of a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrower scope.
Instant Application
US Patent 11,947,828
A memory device, comprising: a memory array comprising a plurality of memory cells; a selection circuit configured to determine a first faulty cell in the plurality of memory cells to have a highest priority for a replacing operation according to the first faulty cell storing an exponent field of a floating-point number; and a spare circuit configured to store an accurate value corresponding to the first faulty cell for the replacing operation to replace the first faulty cells with the accurate value.
A memory device, comprising: a memory array, wherein at least one first faulty cell and at least one second faulty cell that are in the memory array are configured to store data corresponding to, respectively, first and second fields of a floating-point number; a selection circuit configured to identify the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell, and further configured to determine that an address of the at least one first faulty cell matches one of a plurality of addresses of a group of memory cells to output the address of the at least one first faulty cell as a fault address, wherein the group of memory cells store data corresponding to an exponent field of the floating-point number, wherein the selection circuit is further configured to output the fault address to a redundancy analyzer circuit that is configured to perform a replacing operation of replacing the at least one first faulty cell; and a clipping circuit configured to output the floating-point number read out from the memory array as a read data when the floating-point number is between a first threshold value and a second threshold value smaller than the first threshold value.
The memory device of claim 1, wherein the selection circuit is further configured to identify a second faulty cell in the plurality of memory cells, wherein a first priority of the first faulty cell is higher than a second priority of the second faulty cell, wherein the memory device further comprises: a replacement circuit configured to perform the replacing operation to replace the first and second faulty cells according to the first priority and the second priority.
The memory device of claim 1, wherein the at least one first faulty cell has a stuck-at-1 fault, and the at least one second faulty cell has a stuck-at-0 fault.
The memory device of claim 2, wherein the first faulty cell has a stuck-at-1 fault, and the second faulty cell has a stuck-at-0 fault.
The memory device of claim 1, wherein the first field of the floating-point number is the exponent field.
The memory device of claim 2, wherein the selection circuit is further configured to output a fault address of the first faulty cell to the replacement circuit to perform the replacing operation.
The memory device of claim 1, further comprising: a spare circuit comprising a plurality of spare cells, wherein one of the plurality of spare cells is configured to store an accurate value corresponding to the at least one first faulty cell, wherein the spare circuit is further configured to replace a faulty bit corresponding to the at least one first faulty cell with the accurate value.
The memory device of claim 4, wherein the selection circuit is further configured to determine that an address received from a test circuit matches one of a plurality of addresses of a group of memory cells to output the address as the fault address, wherein the group of memory cells store data corresponding to the exponent field.
The memory device of claim 1, wherein the clipping circuit is further configured to compare the floating-point number that is read out from the memory array with the first threshold value, and configured to output the first threshold value as the read data when the floating-point number is greater than the first threshold value.
The memory device of claim 1, wherein the spare circuit comprises a plurality of spare cells, wherein one of the plurality of spare cells is configured to store the accurate value corresponding to the first faulty cell, wherein the spare circuit is further configured to replace a faulty bit corresponding to the first faulty cell with the accurate value.
The memory device of claim 5, wherein when the floating-point number is smaller than the second threshold value, the clipping circuit is further configured to output the second threshold value as the read data.
The memory device of claim 1, further comprising: a clipping circuit configured to compare the floating-point number that is read out from the memory array with a first threshold value, and configured to output the first threshold value as a read data when the floating-point number is greater than the first threshold value.
The memory device of claim 5, wherein the floating-point number corresponds to an input activation used in a neural network model, and the clipping circuit is further configured to compare the floating-point number with the second threshold value, and to output the floating-point number, the first threshold value, or the second threshold value, wherein the first threshold value corresponds to a maximum of data used in the neural network model, and the second threshold value equals to 0.
The memory device of claim 7, wherein when the floating-point number is smaller than a second threshold value smaller than the first threshold value, the clipping circuit is further configured to output the second threshold value as the read data.
The memory device of claim 1, wherein the clipping circuit is further configured to output the second threshold value when the floating-point number is smaller than the second threshold value, wherein the second threshold value is unequal to zero.
The memory device of claim 7, wherein the floating-point number corresponds to an input activation used in a neural network model, and the clipping circuit is further configured to compare the floating-point number with a second threshold value, and to output the floating-point number, the first threshold value, or the second threshold value, wherein the first threshold value corresponds to a maximum of data used in the neural network model, and the second threshold value equals to zero.
A method, comprising: testing a memory array to identify a plurality of faulty cells in the memory array; identifying in the plurality of faulty cells an excluded cell that meets at least one of a plurality of conditions, wherein the plurality of conditions are associated with a value of a first binary number corresponding to the excluded cell, wherein a first condition of the plurality of conditions indicates that a value of an exponent in the first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell; replacing at least one cell of remaining cells in the plurality of faulty cells with a redundant cell; and outputting a second binary number corresponding to the redundant cell as a read data to a neural network processor when the second binary number is between a first threshold value and a second threshold value.
A method, comprising: storing data transmitted from/to a neural network processor through a memory array; identifying in a plurality of faulty cells in the memory array an excluded cell that meets at least one of a plurality of conditions, wherein a first condition of the plurality of conditions indicates that a first value of an exponent in a first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell; and outputting a fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell according to a value stored in a spare circuit.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the value of the first binary number corresponding to the excluded cell is smaller than an accurate value of the first binary number corresponding to the excluded cell.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a mantissa field of the first binary number.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a mantissa field of the first binary number, or that the excluded cell is configured to store a bit in a sign field of the first binary number, and the first binary number is used as an activation in a neural network model.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a sign field of the first binary number, and the first binary number is used as an activation in a neural network model.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell stores a low logic value in response to a write operation performed to write a high logic value in the excluded cell.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell stores a low logic value in response to a write operation performed to write a high logic value in the excluded cell.
The method of claim 9, wherein the first threshold value and the second threshold value are associated with, respectively, a maximum and a minimum of data used in the neural network processor.
The method of claim 10, further comprising: outputting the fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell with a redundant cell; comparing a second value of a second binary number corresponding to the redundant cell with a first threshold value and a second threshold value that are associated with, respectively, a maximum and a minimum of data used in a neural network processor; and outputting, in response to the comparison, the second binary number, the first threshold value, or the second threshold value as a read data to the neural network processor.
The method of claim 9, wherein the at least one cell of the remaining cells in the plurality of faulty cells has a stuck-at-1 fault.
The method of claim 10, wherein the at least one cell of the remaining cells in the plurality of faulty cells has a stuck-at-1 fault.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a mantissa field of the first binary number.
A system, comprising: a memory device; and a neural network processor configured to access the memory device; wherein the memory device comprises: a plurality of memory cells configured to store data transmitted from/to the neural network processor; and a selection circuit configured to determine a fault address from a plurality of addresses, wherein the fault address is of a faulty cell in the plurality of memory cells, wherein the selection circuit identifies that the faulty cell has a lowest priority in a cell replacement operation according to the faulty cell having a stuck-at-0 fault.
A system, comprising: a memory device; and a neural network processor configured to access the memory device; wherein the memory device comprises: a plurality of memory cells configured to store a plurality of binary numbers corresponding to data transmitted from/to the neural network processor; a selection circuit configured to determine that a first address of a plurality of addresses received from a test circuit matches one of addresses of first memory cells in the plurality of memory cells to output the first address as a fault address, wherein the first memory cells store data corresponding to exponent fields of the plurality of binary numbers, and the plurality of addresses correspond to a plurality of faulty cells, wherein the selection circuit is further configured to output the fault address of a first faulty cell in a plurality of faulty cell, wherein the first faulty cell has a first priority in a cell replacement operation and has a stuck-at-1 fault in a bit in the exponent field of a first binary number of the plurality of binary numbers; a replacement circuit configured to replace, according to the fault address, the first faulty cell with a redundant cell of a plurality of redundant cells; and a clipping circuit configured to output to the neural network processor a first threshold value when the first binary number is greater than the first threshold value.
The system of claim 16, wherein the selection circuit identifies that the faulty cell has a highest priority in a cell replacement operation when the faulty cell has a stuck-at-1 fault and stores an exponent field of a binary number.
The system of claim 16, wherein the clipping circuit is further configured to output a second threshold value smaller than the first threshold value when the first binary number is smaller than the second threshold value, or the first binary number when the first binary number ranges between the first and second threshold values.
The system of claim 17, wherein the memory device further comprises: a clipping circuit configured to output to the neural network processor a first threshold value when the binary number is greater than the first threshold value, a second threshold value when the binary number is smaller than the second threshold value.
The system of claim 17, wherein the first and second threshold values are associated with distribution of input activations used in a neural network model executed in the neural network processor, and the second threshold value equals to 0.
The system of claim 16, wherein the memory device further comprises: a test circuit configured to compare a plurality of binary numbers, that are inputted to the memory device, with the plurality of binary numbers that are read from the memory device, and further configured to output, in response to the comparison, a plurality of addresses, corresponding to a plurality of faulty cells including the faulty cell, to the selection circuit.
The system of claim 16, wherein the test circuit is configured to compare the plurality of binary numbers, that are inputted to the memory device, with the plurality of binary numbers that are read from the memory device, and further configured to output, in response to the comparison, the plurality of addresses to the selection circuit.
The system of claim 16, wherein an excluded cell, different from the first faulty cell, in the plurality of memory cells has a second priority lower than the first priority in the cell replacement operation and has a stuck-at-0 fault, wherein a bit data that corresponds to the excluded cell keeps the same value during the cell replacement operation.
Regarding claim 1, the claim of the instant application is substantially similar to that of Claim 1 and Claim 4 of the Patent as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent notes the differences and the US Patent thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application.
Regarding claim 2 of the instant application, the limitations are substantially identical to claim 1 of the Patent.
Regarding claim 3 of the instant application, the limitations are substantially identical to limitations of claim 2 of the Patent.
Regarding claim 4 of the instant application, the limitations are substantially identical to limitations of claim 1 of the Patent.
Regarding claim 5 of the instant application, the limitations are substantially identical to claim 1 and claim 16 of the Patent. The system claim 16 of the Patent recites the element of the test circuit and one of ordinary skill in the art may recognize the inclusion of a test circuit which may provide an input to the memory device of claim 5 to perform the corresponding address matching as done by the selection circuit.
Regarding claim 6 of the instant application, the limitations are substantially identical to limitations of claim 4 of the Patent.
Regarding claim 7 of the instant application, the limitations are substantially identical to claim 5 of the Patent.
Regarding claim 8 of the instant application, the limitations are substantially identical to claim 6 of the Patent.
Regarding claim 9 of the instant application, the limitations are substantially identical to claim 7 of the Patent.
Regarding claim 10 of the instant application, the limitations are substantially identical to limitations of claim 9 and claim 11 of the Patent for similar reasons as presented above for claim 1.
Regarding claim 11 of the instant application, the limitations are substantially identical to limitations of claim 15 of the Patent
Regarding claim 12 of the instant application, the limitations are substantially identical to claim 11 of the Patent.
Regarding claim 13 of the instant application, the limitations are substantially identical to limitations of claim 12 of the Patent.
Regarding claim 14 of the instant application, the limitations are substantially identical to claim 9 and claim 13 of the Patent.
Regarding claim 15 of the instant application, the limitations are substantially identical to claim 14 of the Patent.
Regarding claim 16 of the instant application, the limitations are substantially identical to limitations of claim 16 and claim 20 of the Patent for similar reasons as presented above for claim 1.
Regarding claim 17 of the instant application, the limitations are substantially identical to claim 16 of the Patent.
Regarding claim 18 of the instant application, the limitations are substantially identical to claim 16 and claim 17 of the Patent.
Regarding claim 19 of the instant application, the limitations are substantially identical to claim 16 and claim 19 of the Patent.
This is a nonstatutory double patenting rejection.
The Examiner notes MPEP Section 804.02 (IV) cited below:
If multiple conflicting patents and/or pending applications are applied in nonstatutory double patenting rejections made in a single application, then prior to issuance of that application, it is necessary to disclaim the terminal part of any patent granted on the application which would extend beyond the expiration date of each one of the conflicting patents and/or applications. A terminal disclaimer fee is required for each terminal disclaimer filed. To avoid paying multiple terminal disclaimer fees, a single terminal disclaimer based on common ownership may be filed, for example, in which the term disclaimed is based on all the conflicting, commonly owned nonstatutory double patenting references. Similarly, a single terminal disclaimer based on a joint research agreement may be filed, in which the term disclaimed is based on all the conflicting nonstatutory double patenting references.
Each one of the commonly owned conflicting nonstatutory double patenting references must be included in the terminal disclaimer to avoid the problem of dual ownership of patents to patentably indistinct inventions in the event that the patent issuing from the application being examined ceases to be commonly owned with any one of the double patenting references that have issued or may issue as a patent. Note that 37 CFR 1.321(c)(3) requires that a terminal disclaimer for commonly owned conflicting claims "[i]nclude a provision that any patent granted on that application or any patent subject to the reexamination proceeding shall be enforceable only for and during such period that said patent is commonly owned with the application or patent which formed the basis for the judicially created double patenting."
Filing a terminal disclaimer including each one of the conflicting nonstatutory double patenting references is also necessary to avoid the problem of separate enforcement of patents to patentably indistinct inventions by parties to a joint research agreement. 37 CFR 1.321(d) sets forth the requirements for a terminal disclaimer where the claimed invention resulted from activities undertaken within the scope of a joint research agreement.
Claims 1-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,399,644, hereinafter referred to as “Patent II”. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are of a broader recitation of those in the US Patent as demonstrated by the comparison below. In this manner, it may be considered that the claims of the US Patent may anticipate the claims of the instant application as they are of narrower scope.
Instant Application
US Patent 12,399,644
A memory device, comprising: a memory array comprising a plurality of memory cells; a selection circuit configured to determine a first faulty cell in the plurality of memory cells to have a highest priority for a replacing operation according to the first faulty cell storing an exponent field of a floating-point number; and a spare circuit configured to store an accurate value corresponding to the first faulty cell for the replacing operation to replace the first faulty cells with the accurate value.
A memory device, comprising: a memory array comprising a plurality of memory cells; a selection circuit configured to identify a first faulty cell and a second faulty cell that are in the plurality of memory cells, wherein a first priority of the first faulty cell is higher than a second priority of the second faulty cell according to the first faulty cell storing an exponent field of a floating-point number; and a replacement circuit configured to perform a replacing operation to replace the first and second faulty cells according to the first priority and the second priority.
The memory device of claim 1, wherein the selection circuit is further configured to identify a second faulty cell in the plurality of memory cells, wherein a first priority of the first faulty cell is higher than a second priority of the second faulty cell, wherein the memory device further comprises: a replacement circuit configured to perform the replacing operation to replace the first and second faulty cells according to the first priority and the second priority.
The memory device of claim 1, wherein the first faulty cell has a stuck-at-1 fault, and the second faulty cell has a stuck-at-0 fault.
The memory device of claim 2, wherein the first faulty cell has a stuck-at-1 fault, and the second faulty cell has a stuck-at-0 fault.
The memory device of claim 1, wherein the selection circuit is further configured to output a fault address of the first faulty cell to the replacement circuit to perform the replacing operation.
The memory device of claim 2, wherein the selection circuit is further configured to output a fault address of the first faulty cell to the replacement circuit to perform the replacing operation.
The memory device of claim 3, wherein the selection circuit is further configured to determine that an address received from a test circuit matches one of a plurality of addresses of a group of memory cells to output the address as the fault address, wherein the group of memory cells store data corresponding to the exponent field.
The memory device of claim 4, wherein the selection circuit is further configured to determine that an address received from a test circuit matches one of a plurality of addresses of a group of memory cells to output the address as the fault address, wherein the group of memory cells store data corresponding to the exponent field.
The memory device of claim 1, further comprising: a spare circuit comprising a plurality of spare cells, wherein one of the plurality of spare cells is configured to store an accurate value corresponding to the first faulty cell, wherein the spare circuit is further configured to replace a faulty bit corresponding to the first faulty cell with the accurate value.
The memory device of claim 1, wherein the spare circuit comprises a plurality of spare cells, wherein one of the plurality of spare cells is configured to store the accurate value corresponding to the first faulty cell, wherein the spare circuit is further configured to replace a faulty bit corresponding to the first faulty cell with the accurate value.
The memory device of claim 1, further comprising: a clipping circuit configured to compare the floating-point number that is read out from the memory array with a first threshold value, and configured to output the first threshold value as a read data when the floating-point number is greater than the first threshold value.
The memory device of claim 1, further comprising: a clipping circuit configured to compare the floating-point number that is read out from the memory array with a first threshold value, and configured to output the first threshold value as a read data when the floating-point number is greater than the first threshold value.
The memory device of claim 6, wherein when the floating-point number is smaller than a second threshold value smaller than the first threshold value, the clipping circuit is further configured to output the second threshold value as the read data.
The memory device of claim 7, wherein when the floating-point number is smaller than a second threshold value smaller than the first threshold value, the clipping circuit is further configured to output the second threshold value as the read data.
The memory device of claim 6, wherein the floating-point number corresponds to an input activation used in a neural network model, and the clipping circuit is further configured to compare the floating-point number with a second threshold value, and to output the floating-point number, the first threshold value, or the second threshold value, wherein the first threshold value corresponds to a maximum of data used in the neural network model, and the second threshold value equals to zero.
The memory device of claim 7, wherein the floating-point number corresponds to an input activation used in a neural network model, and the clipping circuit is further configured to compare the floating-point number with a second threshold value, and to output the floating-point number, the first threshold value, or the second threshold value, wherein the first threshold value corresponds to a maximum of data used in the neural network model, and the second threshold value equals to zero.
A method, comprising: testing a memory array to identify a plurality of faulty cells in the memory array; identifying in the plurality of faulty cells an excluded cell that meets at least one of a plurality of conditions, wherein a first condition of the plurality of conditions indicates that a first value of an exponent in a first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell; and outputting a fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell with a redundant cell.
A method, comprising: storing data transmitted from/to a neural network processor through a memory array; identifying in a plurality of faulty cells in the memory array an excluded cell that meets at least one of a plurality of conditions, wherein a first condition of the plurality of conditions indicates that a first value of an exponent in a first binary number corresponding to the excluded cell is smaller than an accurate value of the exponent in the first binary number corresponding to the excluded cell; and outputting a fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell according to a value stored in a spare circuit.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a mantissa field of the first binary number.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a mantissa field of the first binary number.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a sign field of the first binary number, and the first binary number is used as an activation in a neural network model.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell is configured to store a bit in a sign field of the first binary number, and the first binary number is used as an activation in a neural network model.
The method of claim 9, wherein a second condition of the plurality of conditions indicates that the excluded cell stores a low logic value in response to a write operation performed to write a high logic value in the excluded cell.
The method of claim 10, wherein a second condition of the plurality of conditions indicates that the excluded cell stores a low logic value in response to a write operation performed to write a high logic value in the excluded cell.
The method of claim 9, further comprising: comparing a second value of a second binary number corresponding to the redundant cell with a first threshold value and a second threshold value that are associated with, respectively, a maximum and a minimum of data used in a neural network processor; and outputting, in response to the comparison, the second binary number, the first threshold value, or the second threshold value as a read data to the neural network processor.
The method of claim 10, further comprising: outputting the fault address of at least one cell of remaining cells in the plurality of faulty cells for replacing the at least one cell with a redundant cell; comparing a second value of a second binary number corresponding to the redundant cell with a first threshold value and a second threshold value that are associated with, respectively, a maximum and a minimum of data used in a neural network processor; and outputting, in response to the comparison, the second binary number, the first threshold value, or the second threshold value as a read data to the neural network processor.
The method of claim 9, wherein the at least one cell of the remaining cells in the plurality of faulty cells has a stuck-at-1 fault.
The method of claim 10, wherein the at least one cell of the remaining cells in the plurality of faulty cells has a stuck-at-1 fault.
A system, comprising: a memory device; and a neural network processor configured to access the memory device; wherein the memory device comprises: a plurality of memory cells configured to store data transmitted from/to the neural network processor; and a selection circuit configured to determine a fault address from a plurality of addresses received from a test circuit, wherein the fault address is of a faulty cell in the plurality of memory cells, wherein the selection circuit identifies that the faulty cell has a highest priority in a cell replacement operation when the faulty cell has a stuck-at-1 fault and stores an exponent field of a binary number.
A system, comprising: a memory device; and a neural network processor configured to access the memory device; wherein the memory device comprises: a plurality of memory cells configured to store data transmitted from/to the neural network processor; and a selection circuit configured to determine a fault address from a plurality of addresses, wherein the fault address is of a faulty cell in the plurality of memory cells, wherein the selection circuit identifies that the faulty cell has a lowest priority in a cell replacement operation according to the faulty cell having a stuck-at-0 fault.
The system of claim 15, wherein the memory device further comprises: a clipping circuit configured to output to the neural network processor a first threshold value when the binary number is greater than the first threshold value, a second threshold value when the binary number is smaller than the second threshold value.
The system of claim 16, wherein the selection circuit identifies that the faulty cell has a highest priority in a cell replacement operation when the faulty cell has a stuck-at-1 fault and stores an exponent field of a binary number.
The system of claim 16, wherein the clipping circuit is further configured to output to the neural network processor the binary number when the binary number ranges between the first and second threshold values.
The system of claim 17, wherein the memory device further comprises: a clipping circuit configured to output to the neural network processor a first threshold value when the binary number is greater than the first threshold value, a second threshold value when the binary number is smaller than the second threshold value.
The system of claim 17, wherein the first and second threshold values are associated with distribution of input activations used in a neural network model executed in the neural network processor, and the second threshold value equals to zero.
The system of claim 16, wherein the memory device further comprises: a test circuit configured to compare a plurality of binary numbers, that are inputted to the memory device, with the plurality of binary numbers that are read from the memory device, and further configured to output, in response to the comparison, a plurality of addresses, corresponding to a plurality of faulty cells including the faulty cell, to the selection circuit.
The system of claim 15, wherein the memory device further comprises: a test circuit configured to compare a plurality of binary numbers, that are inputted to the memory device, with the plurality of binary numbers that are read from the memory device, and further configured to output, in response to the comparison, a plurality of addresses, corresponding to a plurality of faulty cells including the faulty cell, to the selection circuit.
The system of claim 15, wherein an excluded cell in the plurality of memory cells has a second priority lower than the highest priority in the cell replacement operation and has a stuck-at-0 fault, wherein a bit data that corresponds to the excluded cell keeps the same value in the cell replacement operation.
Regarding claim 1, the claim of the instant application is substantially similar to that of Claim 1 and Claim 5 of the Patent II as noted by the unbolded portions of each claim in the table above. The bolded portions of claim 1 of the instant application and US Patent II notes the differences and the US Patent II thereby presenting a narrower scope establishes that the US Patent would otherwise anticipate the limitations of the instant application.
Regarding claim 2 of the instant application, the limitations are substantially identical to claim 1 of the Patent II.
Regarding claim 3 of the instant application, the limitations are substantially identical to limitations of claim 2 of the Patent II.
Regarding claim 4 of the instant application, the limitations are substantially identical to limitations of claim 3 of the Patent II.
Regarding claim 5 of the instant application, the limitations are substantially identical to claim 4 of the Patent II.
Regarding claim 6 of the instant application, the limitations are substantially identical to limitations of claim 5 of the Patent II.
Regarding claim 7 of the instant application, the limitations are substantially identical to claim 6 of the Patent II.
Regarding claim 8 of the instant application, the limitations are substantially identical to claim 7 of the Patent II.
Regarding claim 9 of the instant application, the limitations are substantially identical to claim 8 of the Patent II.
Regarding claim 10 of the instant application, the limitations are substantially identical to limitations of claim 9 of the Patent for similar reasons as presented above for claim 1.
Regarding claim 11 of the instant application, the limitations are substantially identical to limitations of claim 10 of the Patent II.
Regarding claim 12 of the instant application, the limitations are substantially identical to claim 11 of the Patent II.
Regarding claim 13 of the instant application, the limitations are substantially identical to limitations of claim 12 of the Patent II.
Regarding claim 14 of the instant application, the limitations are substantially identical to claim 19 and 13 of the Patent II.
Regarding claim 15 of the instant application, the limitations are substantially identical to claim 14 of the Patent II.
Regarding claim 16 of the instant application, the limitations are substantially identical to limitations of claim 15 of the Patent II for similar reasons as presented above for claim 1.
Regarding claim 17 of the instant application, the limitations are substantially identical to claim 15 of the Patent II.
Regarding claim 18 of the instant application, the limitations are substantially identical to claim 16 of the Patent II.
Regarding claim 19 of the instant application, the limitations are substantially identical to claim 19 of the Patent II.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Davis et al. (US 2015/0033064) wherein identifying fault memory cells and replacement cells via encoding techniques is discussed.
Strauss et al. (US 2014/0258593) wherein storing floating-point number components according to priorities is discussed.
Chen et al. (US 2019/0079727) wherein pruning floating point numbers is discussed.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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