Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Interpretation — 35 USC § 112
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. — An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word
“means” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AlA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “an external memory unit”; “a descriptor loading block"; “a remap table database” in claims 1, 3.
Claims 17-20 using of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AlA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AlIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention are directed to non-statutory subject matter.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention are directed to an abstract idea without significantly more.
Claim 8 recites a process for updating metadata, the method comprising: fetching an original descriptor tag from an external memory…; storing the original descriptor tag in an internal cache memory of a processing engine…; comparing the original descriptor tag to a plurality of descriptor update tags, wherein the original descriptor tag and the plurality of descriptor update tags are stored in the internal cache memory; and replacing an original base value…”.
These limitations are processes that, under their broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting "an external memory", "an internal memory", “processing engine” nothing in the claim element precludes the step from practically being performed in a human mind or with the aid of pen and paper. For example, but for the "an external memory", "an internal memory", “processing engine” language, “fetching an original descriptor tag…; storing the original descriptor tag…; comparing the original descriptor tag…; and replacing an original base value…” in the context of this claim encompasses a user mentally, and with the aid of pen and paper finding changes between an original and updated descriptor tags on a sheet of paper and evaluate to identify a result.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind, then it falls within the “Mental Processes” grouping of abstract ideas (concepts performed in the human mind including an observation, evaluation, judgment, and opinion).
This judicial exception is not integrated into a practical application. In particular, the claims recite additional element – using reciting "an external memory", "an internal memory", “processing engine”, however, these limitations “fetching an original descriptor tag…; storing the original descriptor tag…; comparing the original descriptor tag…; and replacing an original base value…” amount to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g).
These limitations “storing the original descriptor tag in an internal cache memory”; these limitations are a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g).
The " external memory", " internal memory", “processing engine”, non-transitory computer-readable medium are recited at a high-level of generality (i.e., as a generic processor performing a generic computer function of fetching an original descriptor tag…; storing the original descriptor tag…; comparing the original descriptor tag to identify a difference and replacing the original with the updated base value…) such that they amount no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. (see MPEP 2106.05(f)). The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because, when considered separately and in combination, they do not add significantly more to the exception. Considered separately and as an ordered combination, the claim elements do not provide an improvement to another technology or technical field; do not provide an improvement to the functioning of the computer itself.
The limitations “fetching an original descriptor tag…; storing the original descriptor tag…; comparing the original descriptor tag…; and replacing an original base value…” amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Claims 1 and claim 17 are the apparatuses claims to perform the method of claim 10; are similar in scope to claim 10; and therefore, are rejected under similar rationale.
Claims 2-9, 11-16, 18-20 are dependent on claims 1, 10, 17, they merely add further details of the abstract steps recited in their respective independent claims 1, 10, 17, without including an improvement to another technology or technical field, an improvement to the functioning of the abstract idea to a particular technological environment. Therefore, dependent claims 2-9, 11-16, 18-20 are also directed to non-statutory subject matter.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7, 10-16, 19-24, 27-29 of copending Application No. 17/177,390. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are drawn to the same subject.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the instant application are claiming common subject matter and they are substantially similar in scope and they use the same limitations, using varying terminology. They are not patentably distinct from each other because claims 1-7, 10-16, 19-24, 27-29 of copending Application No. 17/177,390 contain almost every element of claims 1-20 of the instant application, and as such anticipate/obvious claims 1-20 of the instant application.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). “ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30,
2001).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over GRAJEWSKI et al (US Pub No. 2020/0151845), in view of Uhrenholt et al (US Pub No. 2023/0195631).
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over GRAJEWSKI et al (US Pub No. 2020/0151845), in view of Uhrenholt et al (US Pub No. 2023/0195631).
A per claim 1, GRAJEWSKI teaches an apparatus comprising (i.e. An apparatus comprising: a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated, [0248]):
a non-transitory external memory unit configured for storing an original descriptor tag, wherein the original descriptor tag includes information of an object which is rendered and a value related to a graphical surface location (i.e. the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]; FIG. 15 ... a graphics application 1506 and graphics processor 1501. A physical configuration memory 1514 stores current configuration data for the graphics processor 1501 using a physical layout which is different from the logical view of the configuration memory 1512 provided to the graphics processor 1501 and graphics device driver 1510 ... a configuration mapper 1530 maps the logical view of configuration memory 1512 to the physical view of configuration memory 1514 to facilitate configuration updates and configuration queries performed by the graphics device driver 1510 ... the configuration mapper 1530 comprises a mapping table, [0155]; The graphics processor 1501 then uses the remap table 1630 to identify the location of the update in physical configuration memory 1514, [0169]; Internally, the physical configuration memory 1514 can be partitioned into areas, which collect configuration data related to a given GPU stage (e.g., Stages A-D, N are used as an example in FIG. 16). After all updates are processed, the graphics processor 1501 may keep track of which states were modified. For a draw/dispatch request, it can then push these configuration changes down the state pipeline to take effect for a particular draw/dispatch operation, [0170]; within the shader processor 602 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.), [0077]);
a remap table database coupled to the non-transitory external memory unit,
the remap table database to store a plurality of original base values, a plurality of updated base values, and a plurality of updated miscellaneous base values, wherein each of the plurality of original base values represents a starting surface location in the non-transitory external memory unit (i.e. the graphic device driver 1510 updates the graphics processor 1501 by submitting configuration update pointers (e.g., address offsets) and associated data 1550-1553 via the command buffer 1515. The pointers identify regions of the logical view of configuration memory 1512 which are then mapped by the configuration mapper 1530 to perform the updates to the physical configuration memory 1514. The combined command buffer entries 1550-1553, logical view of configuration memory 1512 and configuration mapper 1530, [0156]; A remapping table 1630 them maps the logical view 1512 to the configuration layout in physical configuration memory 1514, [0159]; At 2004, the graphics processor configuration is updated using the physical configuration addresses. For example, the graphics configuration may be updated in a physical configuration memory with address ranges corresponding to different stages and/or functional units within the graphics processor, [0246]); and
a descriptor loading block coupled to the non-transitory external memory, the descriptor loading block to fetch the original descriptor tag from the non-transitory external memory for storage in an internal cache memory and to compare an original base value of the original descriptor tag stored in the internal cache memory to each of the plurality of original base values in the remap table database, and to replace the original base value of the original descriptor tag with an updated base value of the plurality of updated base values in the remap table database, wherein the original base value is not equal to the updated base value (i.e. At 2002, a lookup is performed in a mapping data structure using the logical configuration addresses to identify corresponding physical configuration addresses. For example, a lookup table may be used with a plurality of entries, where each entry includes a logical address and a corresponding physical address for the physical configuration memory, [0244]; Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830, [0095]; Thus, the graphics processor physical configuration memory 1514 is perceived from the perspective of the graphics driver 1510 as a specified memory region, referred to herein as the physical GPU configuration space 1514 ... processing a draw/dispatch request the graphics driver 1510 programs the state by providing updates 1550-1553 to specified portions of the configuration image ... the graphics device driver 1510 generates the updates 1550-1553, including offsets into the logical view 1512 and corresponding configuration data, and submits the updates via the command buffer 1515, [0157]; command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803, [0096]).
GRAJEWSKI implicitly teaches the term "tag" (an original descriptor tag) (i.e. A remapping table 1630 them maps the logical view 1512 to the configuration layout in physical configuration memory 1514 ... the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses
of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]).
GRAJEWSKI does not clearly state this term.
Uhrenholt teaches the term (an original descriptor tag) (i.e. A cache entry (e.g. cache line) should ... include respective data that the cache entry caches, and in an embodiment an identifier (e.g. tag) for the data, that in an embodiment indicates a location (address) in the memory system where corresponding data is stored, [0033]).
It would have been obvious to one of ordinary skill of the art having the teaching of GRAJEWSKI, Uhrenholt before the effective filing date of the claimed invention to modify the system of GRAJEWSKI to include the limitations as taught by Uhrenholt. One of ordinary skill in the art would be motivated to make this combination in order to keep track of which cache is caching what data in view of Uhrenholt ([0036]), as doing so would give the added benefit of updating the data of the corresponding entry in the second cache so that both entries validly cache the same updated data, as taught by Uhrenholt ([0034]).
As to claims 10, 17,GRAJEWSKI teaches a method for updating metadata, the method comprising (i.e. A method comprising: submitting a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of a configuration memory and configuration data to be used to modify at least one configuration region of the configuration memory associated with the at least one logical memory address; performing a lookup to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units; and responsively updating the at least one configuration region, [0256]):
fetching an original descriptor tag from a non-transitory external memory, wherein the non-transitory external memory stores a plurality of original base values, a plurality of updated base values, a plurality of miscellaneous base values, and a plurality of updated miscellaneous base values, and wherein each of the plurality of original base values represents a starting surface location in the non-transitory external memory unit (i.e. the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]; the physical configuration memory 1514 can be partitioned into areas, which collect configuration data related to a given GPU stage (e.g., Stages A-D, N are used as an example in FIG. 16). After all updates are processed, the graphics processor 1501 may keep track of which states were modified. For a draw/dispatch request, it can then push these configuration changes down the state pipeline to take effect for a particular draw/dispatch operation, [0170]; within the shader processor 602 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.), [0077]);
storing the original descriptor tag in an internal cache memory of a processing engine, and wherein the original descriptor tag includes information of an object which is rendered and a value related to a graphical surface location (i.e. FIG. 15 ... a graphics application 1506 and graphics processor 1501. A physical configuration memory 1514 stores current configuration data for the graphics processor 1501 using a physical layout which is different from the logical view of the configuration memory 1512 provided to the graphics processor 1501 and graphics device driver 1510 ... a configuration mapper 1530 maps the logical view of configuration memory 1512 to the physical view of configuration memory 1514 to facilitate configuration updates and configuration queries performed by the graphics device driver 1510 ... the configuration mapper 1530 comprises a mapping table, [0155]);
comparing the original descriptor tag to a plurality of descriptor update tags, wherein the original descriptor tag and the plurality of descriptor update tags are stored in the internal cache memory (i.e. Thus, the updates can be either placed directly in the command buffer 1515 (e.g., for small updates) or placed in graphics memory and referenced from the command buffer 1515 using indirect update fields with pointers to memory (e.g., for more complex data updates). All these are addressed to the logical view. The graphics processor 1501 then uses the remap table 1630 to identify the location of the update in physical configuration memory 1514, [0169]); the graphic device driver 1510 updates the graphics processor 1501 by submitting configuration update pointers (e.g., address offsets) and associated data 1550-1553 via the command buffer 1515. The pointers identify regions of the logical view of configuration memory 1512 which are then mapped by the configuration mapper 1530 to perform the updates to the physical configuration memory 1514. The combined command buffer entries 1550-1553, logical view of configuration memory 1512 and configuration mapper 1530, [0156]; A remapping table 1630 them maps the logical view 1512 to the configuration layout in physical configuration memory 1514, [0159]; At 2004, the graphics processor configuration is updated using the physical configuration addresses. For example, the graphics configuration may be updated in a physical configuration memory with address ranges corresponding to different stages and/or functional units within the graphics processor, [0246]); and
replacing an original base value of the original descriptor tag with an updated base value of the plurality of updated base values, wherein the original base value is not equal to the updated base value (i.e. At 2002, a lookup is performed in a mapping data structure using the logical configuration addresses to identify corresponding physical configuration addresses. For example, a lookup table may be used with a plurality of entries, where each entry includes a logical address and a corresponding physical address for the physical configuration memory, [0244]; Commands from ring interconnect 802 are interpreted by a command streamer 803, which supplies instructions to individual components of the geometry pipeline 820 or the media pipeline 830, [0095]; Thus, the graphics processor physical configuration memory 1514 is perceived from the perspective of the graphics driver 1510 as a specified memory region, referred to herein as the physical GPU configuration space 1514 ... processing a draw/dispatch request the graphics driver 1510 programs the state by providing updates 1550-1553 to specified portions of the configuration image ... the graphics device driver 1510 generates the updates 1550-1553, including offsets into the logical view 1512 and corresponding configuration data, and submits the updates via the command buffer 1515, [0157]; command streamer 803 directs the operation of a vertex fetcher 805 that reads vertex data from memory and executes vertex-processing commands provided by command streamer 803, [0096]).
GRAJEWSKI implicitly teaches the term "tag" (an original descriptor tag) (i.e. A remapping table 1630 them maps the logical view 1512 to the configuration layout in physical configuration memory 1514 ... the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]).
GRAJEWSKI does not clearly state this term.
Uhrenholt teaches the term (an original descriptor tag) (i.e. A cache entry (e.g. cache line) should ... include respective data that the cache entry caches, and in an embodiment an identifier (e.g. tag) for the data, that in an embodiment indicates a location (address) in the memory system where corresponding data is stored, [0033]).
It would have been obvious to one of ordinary skill of the art having the teaching of GRAJEWSKI, Uhrenholt before the effective filing date of the claimed invention to modify the system of GRAJEWSKI to include the limitations as taught by Uhrenholt. One of ordinary skill in the art would be motivated to make this combination in order to keep track of which cache is caching what data in view of Uhrenholt ([0036]), as doing so would give the added benefit of updating the data of the corresponding entry in the second cache so that both entries validly cache the same updated data as taught by Uhrenholt ([0034]).
As to claims 2, 11, 19, Uhrenholt teaches the object is in a graphical product (i.e. The processor may also comprise, and/or be in communication with, one or more memories and/or memory devices that store the data described herein, and/or store software (e.g. (shader) program) for performing the processes described herein. The processor may also be in communication with a host microprocessor, and/or with a display for displaying images based on data generated by the processor, [0096]).
As per claim 3, Uhrenholt teaches the descriptor loading block is further to replace an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of the plurality of updated miscellaneous base values (i.e. In this example, where data corresponding to one of the decompressed L1 cache lines 562-565 has been updated, eviction of one of the decompressed L1 cache lines 562-565 from the Load/Store (L1) cache 25 to the L2 cache 21 will involve compressing the data corresponding to all four decompressed L1 cache lines 562-565 to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As per claim 4, Uhrenholt teaches the descriptor loading block is to store an updated descriptor tag in the internal cache memory unit within the descriptor loading block (i.e. In this example, where data corresponding to one of the decompressed L1 cache lines 562-565 has been updated, eviction of one of the decompressed L1 cache lines 562-565 from the Load/Store (L1) cache 25 to the L2 cache 21 will involve compressing the data corresponding to all four decompressed L1 cache lines 562-565 to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As per claim 5, Uhrenholt teaches the updated descriptor tag includes the updated base value and the updated miscellaneous base value (i.e. Where the cache system comprises first, second and higher level caches, an (the) update to an (the) entry in the first cache in an embodiment triggers updates to one or more cache entries in the higher level cache, as well as to (the) plural entries in the second cache, [0049]; In this example, where data corresponding to one of the decompressed L1 cache lines 562-565 has been updated, eviction of one of the decompressed L1 cache lines 562-565 from the Load/Store (L1) cache 25 to the L2 cache 21 will involve compressing the data corresponding to all four decompressed L1 cache lines 562-565 to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As per claim 6, Uhrenholt teaches a first auxiliary processing engine to utilize the updated descriptor tag (i.e. In this example, where data corresponding to one of the decompressed L1 cache lines 562-565 has been updated, eviction of one of the decompressed L1 cache lines 562-565 from the Load/Store (L1) cache 25 to the L2 cache 21 will involve compressing the data corresponding to all four decompressed L1 cache lines 562-565 to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As per claim 7, Uhrenholt teaches a second auxiliary processing engine to utilize the updated descriptor tag (i.e. In this example, where data corresponding to one of the decompressed L1 cache lines 562-565 has been updated, eviction of one of the decompressed L1 cache lines 562-565 from the Load/Store (L1) cache 25 to the L2 cache 21 will involve compressing the data corresponding to all four decompressed L1 cache lines 562-565 to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As to claims 8, 15, GRAJEWSKI teaches the remap table database is part of the descriptor loading block (i.e. the remapping table 1630 comprises a plurality of entries with each entry comprising a logical address of an offset value and a corresponding physical address to identify the region of physical configuration memory 1514. In one embodiment, the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]).
As to claims 9, 16, GRAJEWSKI teaches the internal cache memory is dedicated to the descriptor loading block (i.e. In some embodiments, the processor 102 includes cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache, [0031]).
As to claims 12, 18, Uhrenholt teaches generating an updated descriptor tag if the original descriptor tag matches one or more of the plurality of descriptor update tags (i.e. Thus, in an embodiment, it is determined whether the first cache (and/or associated execution unit) satisfies a condition, the condition being such that it can only be satisfied by one of the plural first caches (and/or execution units) at any one time, [0088]; to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223]).
As to claims 13, 20, Uhrenholt teaches replacing an original miscellaneous base value of the original descriptor tag with an updated miscellaneous base value of the plurality of updated miscellaneous base values (i.e. to generate updated compressed payload data and updated header data for the compression block 201, writing the updated compressed payload data to the corresponding L2 cache line 512, and writing the updated header data to the corresponding L2 cache line 511, [0223].
As per claim 14, GRAJEWSKI teaches the plurality of updated base values and the plurality of updated miscellaneous base values are stored in a remap table database within the processing engine (i.e. the remapping table 1630 comprises a plurality of entries with each entry comprising a logical address of an offset value and a corresponding physical address to identify the region of physical configuration memory 1514. In one embodiment, the entries in the remapping table 1630 can be defined in Bytes, Words, DWords, etc, depending on the resolution required for a given implementation. Using these values, the remapping table 1630 maps addresses of each logical unit (e.g., Byte, Word, DWord, etc) into a physical unit, [0159]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
BARCZAK et al. (US Pub. 2020/0211272) – discloses technique of ray tracing shading in which a light transport is simulated through physically-based rendering.
Parke et al. (US Pub. 2006/0164425) discloses updating a memory address remapping table using a graphics processing circuitry.
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/MIRANDA LE/ Primary Examiner, Art Unit 2153
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