DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-11 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-11 of prior U.S. Patent No. 12,373,362. This is a statutory double patenting rejection.
Current Application 19/256,297
US Patent – 12,373,362
1. A semiconductor device comprising: a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip, wherein the first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.
1. A semiconductor device comprising: a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip, wherein the first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.
2. The semiconductor device of claim 1, wherein the first system-on-chip includes: a first memory management unit (MMU) configured to convert the first memory physical address into the first device address; and a router configured to determine whether the first device address corresponds to the first memory and configured to forward the first memory request to one of the first memory and the second system-on-chip.
2. The semiconductor device of claim 1, wherein the first system-on-chip includes: a first memory management unit (MMU) configured to convert the first memory physical address into the first device address; and a router configured to determine whether the first device address corresponds to the first memory and configured to forward the first memory request to one of the first memory and the second system-on-chip.
3. The semiconductor device of claim 2, wherein the first system-on-chip and the second system-on-chip control the plurality of memories according to a compute express link (CXL) protocol.
3. The semiconductor device of claim 2, wherein the first system-on-chip and the second system-on-chip control the plurality of memories according to a compute express link (CXL) protocol.
4. The semiconductor device of claim 2, wherein the first memory has a device address in a first range, the second memory has a device address in a second range that is greater than the first range, and the router compares the first device address with the first range and forwards the first memory request.
4. The semiconductor device of claim 2, wherein the first memory has a device address in a first range, the second memory has a device address in a second range that is greater than the first range, and the router compares the first device address with the first range and forwards the first memory request.
5. The semiconductor device of claim 4, wherein the first range is defined from a start address to an end address, and the router forwards the first memory request to the second system-on-chip when the first device address is greater than the end address.
5. The semiconductor device of claim 4, wherein the first range is defined from a start address to an end address, and the router forwards the first memory request to the second system-on-chip when the first device address is greater than the end address.
6. The semiconductor device of claim 2, further comprising: a third processor configured to generate a third memory physical address and a third memory request; and a third system-on-chip physically connected to the third processor, the first system-on-chip, and the second system-on-chip and configured to convert the third memory physical address into a third device address.
6. The semiconductor device of claim 2, further comprising: a third processor configured to generate a third memory physical address and a third memory request; and a third system-on-chip physically connected to the third processor, the first system-on-chip, and the second system-on-chip and configured to convert the third memory physical address into a third device address.
7. The semiconductor device of claim 6, wherein the router forwards the first memory request to an optimal path on which contour numbers are defied in order of proximity to a current system-on-chip.
7. The semiconductor device of claim 6, wherein the router forwards the first memory request to an optimal path on which contour numbers are defied in order of proximity to a current system-on-chip.
8. The semiconductor device of claim 1, wherein the first and second system-on-chip connect through die-to-die interfaces or chip-to-chip interfaces.
8. The semiconductor device of claim 1, wherein the first and second system-on-chip connect through die-to-die interfaces or chip-to-chip interfaces.
9. A method of forwarding a memory request of a semiconductor device, the method comprising: receiving, by a first processor, a first memory request and a first physical address to which the first memory request has to be forwarded; converting the first physical address into a first device address by a first system-on-chip physically connected to the first processor; comparing, by the first system-on-chip, the first device address with a device address of a first memory connected to the first system-on-chip; forwarding the first memory request to the first memory when the first system-on-chip corresponds to the device address of the first memory; forwarding the first memory request to a second system-on-chip connected to the first system-on-chip when the first system-on-chip does not correspond to the device address of the first memory; comparing, by the second system-on-chip, the first device address with a device address of a second memory connected to the second system-on-chip; forwarding the first memory request to the second memory when the second system-on-chip corresponds to the device address of the second memory; and forwarding the first memory request to a third system-on-chip connected to the second system-on-chip when the second system-on-chip does not correspond to the device address of the second memory.
9. A method of forwarding a memory request of a semiconductor device, the method comprising: receiving, by a first processor, a first memory request and a first physical address to which the first memory request has to be forwarded; converting the first physical address into a first device address by a first system-on-chip physically connected to the first processor; comparing, by the first system-on-chip, the first device address with a device address of a first memory connected to the first system-on-chip;
forwarding the first memory request to the first memory when the first system-on-chip corresponds to the device address of the first memory; forwarding the first memory request to a second system-on-chip connected to the first system-on-chip when the first system-on-chip does not correspond to the device address of the first memory; comparing, by the second system-on-chip, the first device address with a device address of a second memory connected to the second system-on-chip; forwarding the first memory request to the second memory when the second system-on-chip corresponds to the device address of the second memory; and forwarding the first memory request to a third system-on-chip connected to the second system-on-chip when the second system-on-chip does not correspond to the device address of the second memory.
10. The method of claim 9, wherein the device address of the first memory is defined as a first range, and the comparing of the first device address with the device address of the first memory includes comparing a smallest value of the first range with the first device address, and comparing a greatest value of the first range with the first device address.
10. The method of claim 9, wherein the device address of the first memory is defined as a first range, and the comparing of the first device address with the device address of the first memory includes comparing a smallest value of the first range with the first device address, and comparing a greatest value of the first range with the first device address.
11. The method of claim 9, wherein a path between the first system-on-chip and the third system-on-chip is an optimal path.
11. The method of claim 9, wherein a
path between the first system-on-chip and the third system-on-chip is an optimal path.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Krithivas et al. (US 2014/0189197), Mayer et al. (US 9,946,674), Stoler (US 10,019,546), Sehgal et al. (US 2023/0236742) and De et al. (US 2017/0162235) do teach a memory system and a memory operation method over compute express link.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184
