DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 19 is objected to because “the initialization module is configured to provide an initialization signal for the light-emitting element of the display panel. the compensation module“ should be changed to --the initialization module is configured to provide an initialization signal for the light-emitting element of the display panel[[.]]; and the compensation module--. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7-16, 20, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 4, 7-9, 12, 13, 15, and 17 of U.S. Patent No. 11,663,957 (resulting from parent application 17/646,610). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of U.S. Patent No. 11,663,957, in view of Lin et al (US 2021/0012712; hereinafter Lin).
• Regarding claim 17, US 11,663,957 claims everything in claims 1 and 15 except the additional details of the additional details of the display panel.
In the same field of endeavor, Lin discloses the additional details of the display panel, as shown in the following table.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 11,663,957 according to the teachings of Lin, for the purpose of reducing leakage and power consumption in a pixel circuit (¶ 53).
Claims 18 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of U.S. Patent No. 11,663,957, in view of Park et al (US 2019/0340977; hereinafter Park).
• Regarding claims 18 and 19, US 11,663,957 claims everything in claims 1 and 15 except the additional details of the additional details of the display panel.
In the same field of endeavor, Park discloses the additional details of the display panel, as shown in the following table.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the claimed invention of US 11,663,957 according to the teachings of Park, for the purpose of enhancing the display quality of a display apparatus (¶ 11).
US 19/256,495
US 11,663,957
1. A display panel, comprising:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
1. A display panel, comprising:
a driving circuit and a pixel circuit,
wherein the driving circuit is configured to provide a control signal for the pixel circuit and the pixel circuit includes a driving transistor; and
a clock signal line, configured to provide a clock signal for the driving circuit,
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage;
the holding stage includes N stages arranged in sequence; N≥1;
when the pixel circuit is operated in the data writing stage, the clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one of the N stages, the clock pulse frequency of the clock signal is a second frequency F2; and F1>F2>0; and
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L1;
when the pixel circuit is operated at the second data refresh frequency F22, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L2; and L1<L2.
15. The display panel according to claim 1, wherein:
the pixel circuit includes a first transistor and a second transistor;
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is configured to provide a control signal for the first transistor; the second driving circuit is configured to provide a control signal for the second transistor;
the clock signal line includes a first clock signal line and a second clock signal line; the first clock signal line provides a first clock signal for the first driving circuit; the second clock signal line provides a second clock signal for the second driving circuit; and
See claim 1.
See claim 1.
See claim 1.
when the pixel circuit is operated in the holding stage, a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is longer than a time length when the clock pulse frequency of the second clock signal is the second frequency F2.
See claim 1.
7. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
when F3>0, F1/F2≤F2/F3.
3. The display panel according to claim 1, wherein:
the N stages also include at least a stage when a clock pulse frequency of the clock signal is a third frequency F3, and F2>F3>0.
7. The display panel according to claim 3, wherein:
when F3>0, F1/F2≤F2/F3.
8. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
when F3=0, the second clock signal is a constant voltage signal.
3. The display panel according to claim 1, wherein:
the N stages also include at least a stage when a clock pulse frequency of the clock signal is a third frequency F3, and F2>F3>0.
8. The display panel according to claim 3, wherein:
when F3=0, the clock signal is a constant voltage signal.
9. The display panel according to claim 8, wherein:
the driving circuit includes at least one transistor controlled by the second clock signal; and
the constant voltage signal controls the at least one transistor to be at an on state.
9. The display panel according to claim 8, wherein:
the driving circuit includes at least one transistor controlled by the clock signal; and
the constant voltage signal controls the at least one transistor to be at an on state.
10. The display panel according to claim 1, wherein
when the pixel circuit is operated in the holding stage:
in an i-th stage of the N stages, the clock pulse frequency of the first clock signal is the second frequency F2;
in a j-th stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
1⩽i⩽N and 1⩽j⩽N.
4. The display panel according to claim 3, wherein:
when the pixel circuit is operated in the holding stage,
in the i-th stage of the N stages, the clock pulse frequency of the clock signal is the second frequency F2, and
in the j-th stage of the N stages, the clock signal is the third frequency F3; and
1≤i≤j≤N.
11. The display panel according to claim 10, wherein:
i<j.
4. The display panel according to claim 3, wherein: …
1≤i≤j≤N.
12. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, in the holding stage, a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is L1;
when the pixel circuit is operated at the second data refresh frequency F22, in the holding stage, the time length when the clock pulse frequency of the first clock signal is the second frequency F2 is L2; and
L1<L2.
1. A display panel, comprising: …
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22; when
the pixel circuit is operated at the first data refresh frequency F11, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L1;
when the pixel circuit is operated at the second data refresh frequency F22, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L2; and
L1<L2.
13. The display panel according to claim 12, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3;
when the pixel circuit is operated at the first data refresh frequency F11, in the holding stage, a time length when the clock pulse frequency of the second clock signal is the third frequency F3 is L3; and
when the pixel circuit is operated at the second data refresh frequency F22, in the holding stage, the time length when the clock pulse frequency of the second clock signal is the third frequency F3 is L4.
13. The display panel according to claim 1, wherein:
when the pixel circuit is operated at the first data refresh frequency F11, in one holding stage, a time length when the clock pulse frequency of the clock signal is the third frequency F3 is L3;
when the pixel circuit is operated at the second data refresh frequency F22, in one holding stage, a time length when the clock pulse frequency of the clock signal is the third frequency F3 is L4; and
|L1−L3|>|L2−L4|.
14. The display panel according to claim 13, wherein:
|L1-L3|>|L2-L4|.
13. The display panel according to claim 1, wherein: …
|L1−L3|>|L2−L4|.
15. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 stages when the clock pulse frequency of the first clock signal is the second frequency F2;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 stages when the clock pulse frequency of the first clock signal is the second frequency F2; and
X1 < X2.
12. The display panel according to claim 1, wherein:
See claim 1.
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 second frequency stages and Y1 third frequency stages; and
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 second frequency stages and Y2 third frequency stages, wherein:
X1<X2, and/or, Y1<Y2; and
in the second frequency stage, the clock pulse frequency of the clock signal is the second frequency F2, and in the third frequency stage, the clock pulse frequency of the clock signal is the third frequency F3.
16. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes Y1 stages when the clock pulse frequency of the second clock signal is a third frequency F3;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes Y2 stages when the clock pulse frequency of the second clock signal is the third frequency F3; and
Y1 < Y2.
12. The display panel according to claim 1, wherein:
See claim 1.
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 second frequency stages and Y1 third frequency stages; and
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 second frequency stages and Y2 third frequency stages, wherein:
X1<X2, and/or, Y1<Y2; and …
17. The display panel according to claim 1, wherein:
the driving transistor includes an oxide semiconductor transistor.
Lin: ¶ 53
18. The display panel according to claim 1, wherein:
the driving transistor includes a silicon transistor.
Park: ¶ 64
19. The display panel according to claim 1, wherein:
the pixel circuit further include a data writing module, a light-emitting control module, a reset module, an initialization module, and a compensation module;
the data writing module is configured to provide a data signal to the driving transistor;
the light-emitting control module is configured to selectively allow a light-emitting element of the display panel to enter a light-emitting stage;
the reset module is configured to provide a reset signal for the gate electrode of the driving transistor; and
the initialization module is configured to provide an initialization signal for the light-emitting element of the display panel[[.]]; and
the compensation module is connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor.
See below.
Park: element T2 in figure 16 and ¶s 65 and 66
Park: elements T5 and T6 in figure 16 and ¶s 71-74
Park: element T4 in figure 16 and ¶s 69 and 70
Park: element T7 in figure 16 and ¶s 75 and 76
Park: element T3 in figure 16 and ¶s 67 and 68
20. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3, and
F3=0.
3. The display panel according to claim 1, wherein:
the N stages also include at least a stage when a clock pulse frequency of the clock signal is a third frequency F3, and F2>F3>0.
8. The display panel according to claim 3, wherein:
when F3=0, the clock signal is a constant voltage signal.
21. A display device comprising:
a display panel including:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
17. A display device, comprising:
a display panel, including:
a driving circuit and a pixel circuit,
wherein the driving circuit is configured to provide a control signal for the pixel circuit and the pixel circuit includes a driving transistor; and
a clock signal line, configured to provide a clock signal for the driving circuit,
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage;
the holding stage includes N stage arranged in sequence; N≥1;
when the pixel circuit is operated in the data writing stage, the clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one of the N stages, the clock pulse frequency of the clock signal is a second frequency F2; and F1>F2>0; and
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L1;
when the pixel circuit is operated at the second data refresh frequency F22, in one holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L2; and
L1<L2.
15. The display panel according to claim 1, wherein:
the pixel circuit includes a first transistor and a second transistor;
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is configured to provide a control signal for the first transistor; the second driving circuit is configured to provide a control signal for the second transistor;
the clock signal line includes a first clock signal line and a second clock signal line; the first clock signal line provides a first clock signal for the first driving circuit; the second clock signal line provides a second clock signal for the second driving circuit; and
See claim 17.
See claim 17.
See claim 17.
when the pixel circuit is operated in the holding stage, a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is longer than a time length when the clock pulse frequency of the second clock signal is the second frequency F2.
See claim 17.
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Claims 1, 7-11, 13-16, and 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 7-9, 12, 13, 15, and 17 of U.S. Patent No. 12,014,674 (resulting from parent application 18/129,373). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of U.S. Patent No. 12,014,674, in view of Lin.
• Regarding claim 17, US 12,014,674 claims everything in claims 1 and 15 except the additional details of the display device.
In the same field of endeavor, Lin discloses the additional details of the display device, as shown in the following table, and for the reasons previously indicated.
Claims 18 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of U.S. Patent No. 12,014,674, in view of Park.
• Regarding claims 18 and 19, US 12,014,674 claims everything in claims 1 and 15 except the additional details of the display device.
In the same field of endeavor, Park discloses the additional details of the display device, as shown in the following table, and for the reasons previously indicated.
US 19/256,495
US 12,014,674
1. A display panel, comprising:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
1. A display panel, comprising:
a pixel circuit;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, and the N stages further include at least one stage, in which the clock pulse frequency of the clock signal is a third frequency F3; and F1>F2>F3≥0.
15. The display panel according to claim 1, wherein:
the pixel circuit includes a driving transistor, a first transistor, and a second transistor;
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes:
a first driving circuit configured to provide a control signal to the first transistor; and
a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes:
a first clock signal line configured to provide a first clock signal to the first driving circuit; and
a second clock signal line configured to provide a second clock signal to the second driving circuit;
See claim 1.
See claim 1.
See claim 1.
when the pixel circuit is operated in the holding stage, a time length when a clock pulse frequency of the first clock signal is the second frequency F2 is greater than a time length when a clock pulse frequency of the second clock signal is the second frequency F2.
See claim 1.
7. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
when F3>0, F1/F2≤F2/F3.
7. The display panel according to claim 1, wherein:
See claim 1.
when F3>0, F1/F2≤F2/F3.
8. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
when F3=0, the second clock signal is a constant voltage signal.
8. The display panel according to claim 1, wherein:
See claim 1.
when F3=0, the clock signal is a constant voltage signal.
9. The display panel according to claim 8, wherein:
the driving circuit includes at least one transistor controlled by the second clock signal; and
the constant voltage signal controls the at least one transistor to be at an on state.
9. The display panel according to claim 8, wherein:
the driving circuit includes at least one transistor controlled by the clock signal; and
the constant voltage signal controls the at least one transistor to be at an on state.
10. The display panel according to claim 1, wherein
when the pixel circuit is operated in the holding stage:
in an i-th stage of the N stages, the clock pulse frequency of the first clock signal is the second frequency F2;
in a j-th stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3; and
1⩽i⩽N and 1⩽j⩽N.
2. The display panel according to claim 1, wherein
when the pixel circuit is operated in the holding stage:
in an i-th stage of the N stages, the clock pulse frequency of the clock signal is the second frequency F2;
in a j-th stage of the N stages, the clock pulse frequency of the clock signal is the third frequency F3; and
1≤i≤N and 1≤j≤N.
11. The display panel according to claim 10, wherein:
i<j.
3. The display panel according to claim 2, wherein:
1≤i<j≤N.
13. The display panel according to claim 12, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3;
when the pixel circuit is operated at the first data refresh frequency F11, in the holding stage, a time length when the clock pulse frequency of the second clock signal is the third frequency F3 is L3; and
when the pixel circuit is operated at the second data refresh frequency F22, in the holding stage, the time length when the clock pulse frequency of the second clock signal is the third frequency F3 is L4.
12. The display panel according to claim 1, wherein:
See claim 1.
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, in the holding stage, a time length when the clock pulse frequency of the clock signal is the second frequency F2 is L1;
when the pixel circuit is operated at the second data refresh frequency F22, in the holding stage, the time length when the clock pulse frequency of the clock signal is the second frequency F2 is L2;
when the pixel circuit is operated at the first data refresh frequency F11, in the holding stage, a time length when the clock pulse frequency of the clock signal is the third frequency F3 is L3;
when the pixel circuit is operated at the second data refresh frequency F22, in the holding stage, the time length when the clock pulse frequency of the clock signal is the third frequency F3 is L4; and
|L1−L3|>|L2−L4|.
14. The display panel according to claim 13, wherein:
|L1-L3| > |L2-L4|.
12. The display panel according to claim 1, wherein: …
|L1−L3|>|L2−L4|.
15. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 stages when the clock pulse frequency of the first clock signal is the second frequency F2;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 stages when the clock pulse frequency of the first clock signal is the second frequency F2; and
X1 < X2.
13. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 second frequency stages and Y1 third frequency stages;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 second frequency stages and Y2 third frequency stages;
X1<X2 and/or Y1<Y2;
in the second frequency stage, the clock pulse frequency of the clock signal is the second frequency F2; and
in the third frequency stage, the clock pulse frequency of the clock signal is the third frequency F3.
16. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes Y1 stages when the clock pulse frequency of the second clock signal is a third frequency F3;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes Y2 stages when the clock pulse frequency of the second clock signal is the third frequency F3; and
Y1 < Y2.
13. The display panel according to claim 1, wherein:
a data refresh frequency of the pixel circuit includes a first data refresh frequency F11 and a second data refresh frequency F22, and F11>F22;
when the pixel circuit is operated at the first data refresh frequency F11, the holding stage includes X1 second frequency stages and Y1 third frequency stages;
when the pixel circuit is operated at the second data refresh frequency F22, the holding stage includes X2 second frequency stages and Y2 third frequency stages;
X1<X2 and/or Y1<Y2; …
17. The display panel according to claim 1, wherein:
the driving transistor includes an oxide semiconductor transistor.
Lin: ¶ 53
18. The display panel according to claim 1, wherein:
the driving transistor includes a silicon transistor.
Park: ¶ 64
19. The display panel according to claim 1, wherein:
the pixel circuit further include a data writing module, a light-emitting control module, a reset module, an initialization module, and a compensation module;
the data writing module is configured to provide a data signal to the driving transistor;
the light-emitting control module is configured to selectively allow a light-emitting element of the display panel to enter a light-emitting stage;
the reset module is configured to provide a reset signal for the gate electrode of the driving transistor; and
the initialization module is configured to provide an initialization signal for the light-emitting element of the display panel[[.]]; and
the compensation module is connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor.
Park: element T2 in figure 16 and ¶s 65 and 66
Park: elements T5 and T6 in figure 16 and ¶s 71-74
Park: element T4 in figure 16 and ¶s 69 and 70
Park: element T7 in figure 16 and ¶s 75 and 76
Park: element T3 in figure 16 and ¶s 67 and 68
21. A display device comprising:
a display panel including:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
17. A display device, comprising
a display panel, including:
a pixel circuit;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, and the N stages further include at least one stage, in which the clock pulse frequency of the clock signal is a third frequency F3; and
F1>F2>F3≥0.
15. The display panel according to claim 1, wherein:
the pixel circuit includes a driving transistor, a first transistor, and a second transistor;
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes:
a first driving circuit configured to provide a control signal to the first transistor; and
a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes:
a first clock signal line configured to provide a first clock signal to the first driving circuit; and
a second clock signal line configured to provide a second clock signal to the second driving circuit;
See claim 17.
See claim 17.
See claim 17.
when the pixel circuit is operated in the holding stage, a time length when a clock pulse frequency of the first clock signal is the second frequency F2 is greater than a time length when a clock pulse frequency of the second clock signal is the second frequency F2.
See claim 17.
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Claims 1 and 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4, 8, and 15 of U.S. Patent No. 12,020,631 (resulting from related application 18/129,405). Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims, as a whole, include all of the limitations of the instant application claims, respectively. The patent claims, as a whole, also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims, as a whole. As such, the instant application claims are anticipated by the patent claims, as a whole, and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”). See the following table.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,020,631, in view of Lin.
• Regarding claim 17, US 12,020,631 claims everything in claim 2 except the additional details of the display device.
In the same field of endeavor, Lin discloses the additional details of the display device, as shown in the following table, and for the reasons previously indicated.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,020,631, in view of Park.
• Regarding claim 18, US 12,020,631 claims everything in claim 2 except the additional details of the display device.
In the same field of endeavor, Park discloses the additional details of the display device, as shown in the following table, and for the reasons previously indicated.
US 19/256,495
US 12,020,631
1. A display panel, comprising:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
1. A display panel, comprising:
a pixel circuit;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, F1>F2>0;
the pixel circuit includes a driving transistor, a first transistor, and a second transistor; …
2. The display panel according to claim 1, wherein:
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor.
1. …the driving circuit includes:
a first driving circuit configured to provide a control signal to the first transistor; and
a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes:
a first clock signal line configured to provide a first clock signal to the first driving circuit; and
a second clock signal line configured to provide a second clock signal to the second driving circuit;
See claim 1.
See claim 1.
See claim 1.
when the pixel circuit is operated in the holding stage, a time length when a clock pulse frequency of the first clock signal is the second frequency F2 is H1, a time length when a clock pulse frequency of the second clock signal is the second frequency F2 is H2, and H1>H2≥0.
See claim 1.
17. The display panel according to claim 1, wherein:
the driving transistor includes an oxide semiconductor transistor.
Lin: ¶ 53
18. The display panel according to claim 1, wherein:
the driving transistor includes a silicon transistor.
Park: ¶ 64
19. The display panel according to claim 1, wherein:
the pixel circuit further include a data writing module, a light-emitting control module, a reset module, an initialization module, and a compensation module;
the data writing module is configured to provide a data signal to the driving transistor;
the light-emitting control module is configured to selectively allow a light-emitting element of the display panel to enter a light-emitting stage;
the reset module is configured to provide a reset signal for the gate electrode of the driving transistor; and
the initialization module is configured to provide an initialization signal for the light-emitting element of the display panel[[.]]; and
the compensation module is connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor.
4. (rearranged) The display panel according to claim 2, wherein
the pixel circuit includes:
a data writing module connected between the data signal line and the source electrode of the driving transistor; and/or
a light-emitting control module configured to selectively allow a light-emitting element to enter a light-emitting stage.
a reset module connected between a reset signal terminal and the gate electrode of the driving transistor; and/or
an initialization module connected between an initialization signal terminal and a light-emitting element of the display panel; and/or
a compensation module connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor; and/or
20. The display panel according to claim 1, wherein:
in at least one stage of the N stages, the clock pulse frequency of the second clock signal is a third frequency F3, and
F3=0.
15. A display panel, comprising:
…
a data refresh period of the pixel circuit includes a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, a clock pulse frequency of the clock signal is a third frequency F3, F3=0; …
21. A display device comprising:
a display panel including:
a pixel circuit including a driving transistor;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: the pixel circuit further includes a first transistor and a second transistor,
a source electrode or a drain electrode of the first transistor being connected to a gate electrode of the driving transistor, and
a source electrode or a drain electrode of the second transistor being connected to a source electrode or a drain electrode of the driving transistor;
the driving circuit includes a first driving circuit configured to provide a control signal to the first transistor, and a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes a first clock signal line configured to provide a first clock signal to the first driving circuit, and a second clock signal line configured to provide a second clock signal to the second driving circuit;
a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the first clock signal and/or the second clock signal is a first frequency F1; and
when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2,
wherein, a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0.
8. A display device comprising the display panel of claim 1.
1. A display panel, comprising:
a pixel circuit;
a driving circuit configured to provide a control signal to the pixel circuit; and
a clock signal line configured to provide a clock signal for the driving circuit;
wherein: a data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N≥1;
when the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1;
when the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, F1>F2>0;
the pixel circuit includes a driving transistor, a first transistor, and a second transistor; …
2. The display panel according to claim 1, wherein:
a source electrode or a drain electrode of the first transistor is connected to a gate electrode of the driving transistor;
a source electrode or a drain electrode of the second transistor is connected to a source electrode or a drain electrode of the driving transistor.
1. …the driving circuit includes:
a first driving circuit configured to provide a control signal to the first transistor; and
a second driving circuit configured to provide a control signal to the second transistor;
the clock signal line includes:
a first clock signal line configured to provide a first clock signal to the first driving circuit; and
a second clock signal line configured to provide a second clock signal to the second driving circuit;
See claim 1.
See claim 1.
See claim 1.
when the pixel circuit is operated in the holding stage, a time length when a clock pulse frequency of the first clock signal is the second frequency F2 is H1, a time length when a clock pulse frequency of the second clock signal is the second frequency F2 is H2, and H1>H2≥0.
see claim 1 above
Allowable Subject Matter
Claims 1 and 7-21 would be allowable if rewritten or amended to overcome the Double Patenting rejections set forth in this Office action, or upon the filing of at least one proper Terminal Disclaimer cumulatively listing every US Patent and US Application forming the basis of the Double Patenting rejections set forth in this Office action. See MPEP §§ 804.02(II) and 804.02(IV).
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest:
a. In claims 1 and 21, where, “when the pixel circuit is operated in the holding phase, in at least one of the N stages, the clock pulse frequency of the first clock signal and/or the second clock signal is a second frequency F2” and “a time length of the clock pulse frequency of the first clock signal being the second frequency F2 is greater than a time length of the clock pulse frequency of the second clock signal being the second frequency F2, and F2 is not equal to 0”, in combination with all the remaining limitations in each claim. Note that these limitations are similar to those indicated as being allowable in section 8, subsection f, of the Office action mailed 27 October 2022 in parent application 17/646,610.
b. In claim 2, where “in the data refresh period, a time length when the clock pulse frequency of the first clock signal is the first frequency F1 is T11, a time length when the clock pulse frequency of the second clock signal is the first frequency F1 is T21, and T11=T21”, in combination with all the limitations in claim 1.
c. In claim 3, where “in the data refresh period, a time length when the clock pulse frequency of the first clock signal is the first frequency F1 is T11, a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is T12, and T11<T12”, in combination with all the limitations in claim 1.
d. In claim 4, where “in the data refresh period, a time length when the clock pulse frequency of the second clock signal is the first frequency F1 is T21, a time length when the clock pulse frequency of the second clock signal is the third frequency F3 is T23, and T21<T23”, in combination with all the remaining limitations in the claim and all the limitations in claim 1.
e. In claim 5, where “in the data refresh period, a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is T12, a time length when the clock pulse frequency of the second clock signal is the third frequency F3 is T23, and T12<T23”, in combination with all the remaining limitations in the claim and all the limitations in claim 1.
f. In claim 6, where “in the data refresh period, a difference between a time length when the clock pulse frequency of the first clock signal is the first frequency F1 and a time length when the clock pulse frequency of the first clock signal is the second frequency F2 is d1, a difference between a time length when the clock pulse frequency of the first clock signal is the second frequency F2 and a time length when the clock pulse frequency of the second clock signal is the third frequency F3 is d2, and d1<d2”, in combination with all the remaining limitations in the claim and all the limitations in claim 1.
g. Claims 7-20 would be allowable based on their dependence from claim 1.
Closing Remarks/Comments
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
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