DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The present application is being examined under the claims filed 08/03/2026.
Claims 1-18 are pending.
Response to Amendment
This Office Action is in response to Applicant’s communication filed 08/03/2026 in response to office action mailed 05/05/2026. The Applicant’s remarks and any amendments to the claims or specification have been considered with the results that follow.
Response to Arguments
In Remarks page 7, Argument 1
The Examiner points to a pre-synaptic spike time bit of Jin which is used to convert electronic timing to neural timing, which the Examiner argues is indicative of a time period (which appears to be a delay time period). The spike time bit of Jin is not a signal enabling an attention period, as recited in claim 1 as amended. The Examiner does not appear to rely on the other cited references for the missing features. Accordingly, independent claim 1, as amended, is allowable over the cited references, considered alone or in combination.
While the language and scope of independent claims 7 and 13, as amended, are not identical to the language and scope of independent claim 1, as amended, the allowability of independent claims 7 and 13 will be apparent in view of the discussion herein. The dependent claims are allowable at least by virtue of their dependencies.
Examiner’s response to Argument 1
The 35 U.S.C. 102 rejections are updated to reflect the new wording in the claims as amended. Particularly, Jin teaches that upon receiving a spike from a presynaptic neuron (a signal), spike timing data from the last 45 ms are stored (an attention period). Thus the presynaptic spike acts as a signal enabling an attention period. The details of the new mapping (necessitated by amendments) are provided in the 35 U.S.C. 102 rejections for claims 1, 7, and 13 below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. “Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware” herein referred to as Jin.
Regarding Claim 1
Jin teaches:
A method, comprising: generating a signal enabling an attention period;
(page 3 column 1 last paragraph) “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive[*Examiner notes: generating a signal].”; [*Examiner notes: The signal is generated by the presynaptic neurons which generate the spikes]
storing, on a set of storage neurons of a neural network,
(page 3 column 2 paragraph 1) “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive.”; [*Examiner notes: The broadest reasonable interpretation of “storage neurons” includes memory which stores data about neurons. Therefore, the “SDRAM” storing the timing data is mapped to the set of storage neurons.]
a set of spike pattern data, the storing the set of spike pattern data including: storing first parameters indicative of a presence of spikes on respective neurons of the set of storage neurons during the attention period; and storing, on the set of storage neurons of the neural network, second parameters indicative of a timing of spikes on the respective neurons of the set of storage neurons.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired[*Examiner notes: parameters indicative of presence of spikes] The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history[*Examiner notes: parameters indicative of timing of spikes] in the last 48 ms[*Examiner notes: during the attention period]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”; [*Examiner notes: Data in the “coarse time” portion indicates the presence of data in the “fine time” portion, which stores timing data on spikes within the attention period]
Regarding Claim 2:
Jin teaches:
The method of claim 1
(see rejection of claim 1)
comprising storing, by the neurons of the set of storage neurons: the first parameters as corresponding first reference parameters; and the second parameters as corresponding second reference parameters.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired[*Examiner notes: first parameters indicative of presence of spikes]. The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history in the last 48 ms[*Examiner notes: second reference parameters]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”
Regarding Claim 7
Jin teaches:
A neural network, comprising: a timing neuron, which, in operation, generates a signal enabling an attention period; and a set of storage neurons coupled to the timing neuron,
() “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron[*Examiner notes: timing neuron] is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive[*Examiner notes: signal enabling attention period].”
wherein the set of storage neurons, in operation, store
(page 3 column 2 paragraph 1) “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive.”; [*Examiner notes: The broadest reasonable interpretation of “storage neurons” includes memory which stores data about neurons. Therefore, the “SDRAM” storing the timing data is mapped to the set of storage neurons.]
a set of spike pattern data, based on the signal enabling the attention period, the set of spike pattern data including: first parameters indicative of a presence of spikes stored on respective neurons of the set of storage neurons during the attention period; and second parameters indicative of a timing of spikes stored on the respective neurons of the set of storage neurons.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired[*Examiner notes: parameters indicative of presence of spikes] The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history[*Examiner notes: parameters indicative of timing of spikes] in the last 48 ms[*Examiner notes: during the attention period]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”; [*Examiner notes: Data in the “coarse time” portion indicates the presence of data in the “fine time” portion, which stores timing data on spikes within the attention period]
Regarding Claim 8
Jin teaches:
The neural network of claim 7
(see rejection of claim 7)
wherein the neurons of the set of storage neurons, in operation, store: the first parameters as corresponding first reference parameters; and the second parameters as corresponding second reference parameters.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired[*Examiner notes: first parameters indicative of presence of spikes]. The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history in the last 48 ms[*Examiner notes: second reference parameters]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Julian et al. (PGPUB no. US20140351186A1) herein referred to as Julian.
Regarding Claim 3
Jin teaches:
The method of claim 2,
(see rejection of claim 2)
Jin does not explicitly teach:
wherein the first and second reference parameters are stored in a non-volatile memory.
However, Julian teaches:
wherein the first and second reference parameters are stored in a non-volatile memory.
(paragraph [0048]) “Functionality of a neural processor that emulates the neural system 100 may depend on weights of synaptic connections, which may control strengths of connections between neurons. The synaptic weights may be stored in a non-volatile memory in order to preserve functionality of the processor after being powered down.”; [*Examiner notes: Julian teaches storing parameters in non-volatile memory]
Jin, Julian, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin with the non-volatile memory of Julian because (Julian paragraph [0048]) “. The synaptic weights may be stored in a non-volatile memory in order to preserve functionality of the processor after being powered down.”
Regarding Claim 9
Jin teaches:
The neural network of claim 8
(see rejection of claim 8)
Jin does not explicitly teach:
comprising a non-volatile memory, wherein neurons of the set of storage neurons, in operation, store the first and second reference parameters in the non-volatile memory.
However, Julian teaches:
comprising a non-volatile memory, wherein neurons of the set of storage neurons, in operation, store the first and second reference parameters in the non-volatile memory.
(paragraph [0048]) “Functionality of a neural processor that emulates the neural system 100 may depend on weights of synaptic connections, which may control strengths of connections between neurons. The synaptic weights may be stored in a non-volatile memory in order to preserve functionality of the processor after being powered down.”; [*Examiner notes: Julian teaches storing parameters in non-volatile memory]
Jin, Julian, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin with the non-volatile memory of Julian because (Julian paragraph [0048]) “. The synaptic weights may be stored in a non-volatile memory in order to preserve functionality of the processor after being powered down.”
Claims 4, 6, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of NPL reference Dennis et al. “Combining robust spike coding with spiking neural networks for sound event classification” herein referred to as Dennis.
Regarding Claim 4
Jin teaches:
The method of claim 1
(see rejection of claim 1)
Jin does not explicitly teach:
comprising comparing the first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data
However, Dennis teaches:
comprising comparing the first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data
(page 177 column 2 last paragraph) “To produce a spike coding of this representation, a codebook dictionary is first generated that contains entries representing the variation of local feature information. Here we use k. means clustering to produce the codebook, C. However other approaches are possible, such as sparse coding [12]. For the each entry where z=1…Z in the codebook, Cz, the Euclidean distance is used as the similarity measure, with a local missing feature mask introduced to reduce the influence of the noise on the codebook matching. The distance[*Examiner notes: comparing] between the codebook[*Examiner notes: reference spike pattern data] and a local feature at position (f,t)[*Examiner notes: corresponding first and second parameters] is therefore calculated as follows:”
Jin, Dennis, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin by using reference neurons and comparing against them as taught by Dennis because (Dennis page 177 column 2 paragraph 2) “The proposed spike coding is generated by first detecting key-points in the spectrogram, which localise the sparse high-energy peaks in the spectrogram, and then extracting the local spectral information to find the best matching entries in a codebook. The idea is that such peaks will still be present under mismatched noise, and the discriminative local feature information should provide a robust foundation for further processing. The final output can be considered as a novel sparse representation of the spectrogram, since the spike coding preserves the frequency information while outputting a sparse spike coding of the detected local features.”
Regarding Claim 6
Jin in view of Dennis teaches:
The method of claim 4
(see rejection of claim 4)
Dennis further teaches:
wherein the comparing includes performing a distance calculation
(page 178 column 1 paragraph 1) “The distance between the codebook and a local feature at position (f,t) is therefore calculated as follows:”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to combine Jin with Dennis for the same reasons given in claim 4 above.
Regarding Claim 10
Jin teaches:
The neural network of claim 7
(see rejection of claim 7)
Jin does not explicitly teach:
wherein the neurons of the set of storage neurons, in operation, compare first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data
However, Dennis teaches:
wherein the neurons of the set of storage neurons, in operation, compare first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data
(page 177 column 2 last paragraph) “To produce a spike coding of this representation, a codebook dictionary is first generated that contains entries representing the variation of local feature information. Here we use k. means clustering to produce the codebook, C. However other approaches are possible, such as sparse coding [12]. For the each entry where z=1…Z in the codebook, Cz, the Euclidean distance is used as the similarity measure, with a local missing feature mask introduced to reduce the influence of the noise on the codebook matching. The distance[*Examiner notes: comparing] between the codebook[*Examiner notes: reference spike pattern data] and a local feature at position (f,t)[*Examiner notes: corresponding first and second parameters] is therefore calculated as follows:”
Jin, Dennis, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin by using reference neurons and comparing against them as taught by Dennis because (Dennis page 177 column 2 paragraph 2) “The proposed spike coding is generated by first detecting key-points in the spectrogram, which localise the sparse high-energy peaks in the spectrogram, and then extracting the local spectral information to find the best matching entries in a codebook. The idea is that such peaks will still be present under mismatched noise, and the discriminative local feature information should provide a robust foundation for further processing. The final output can be considered as a novel sparse representation of the spectrogram, since the spike coding preserves the frequency information while outputting a sparse spike coding of the detected local features.”
Regarding Claim 12
Jin in view of Dennis teaches:
The neural network of claim 10
(see rejection of claim 10)
And Dennis further teaches:
wherein the comparing includes performing a distance calculation
(page 178 column 1 paragraph 1) “The distance between the codebook and a local feature at position (f,t) is therefore calculated as follows:”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to combine Jin with Dennis for the same reasons given in claim 10 above.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jin in view of Dennis and Wu et al. (PGPUB no US20180082176A1) herein referred to as Wu.
Regarding Claim 5
Jin in view of Dennis teaches:
The method of claim 4
(see rejection of claim 4)
Jin in view of Dennis does not explicitly teach:
wherein the set of spike pattern data is stored in a volatile memory and the set of reference spike pattern data is stored in a non-volatile memory
However, Wu teaches:
wherein the set of spike pattern data is stored in a volatile memory and the set of reference spike pattern data is stored in a non-volatile memory
(paragraph [0019]) “In one embodiment, the memory 104 may comprise one or more SRAM memory devices or other non-volatile memory devices known in the art. In an alternative embodiment, the memory 104 may comprise a main memory, such as a DRAM, for storing programs[*Examiner notes: set of spike pattern data stored in volatile memory], e.g., 106 and 108, being executed, and a separate non-volatile memory, such as an SRAM or flash memory, storing the spike history array 200[*Examiner notes: set of reference spike pattern data stored in non-volatile memory], now pointer 300, synapse information 400, and neuron membrane potential information 500.”
Jin, Dennis, Wu, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin in view of Dennis by implementing the non-volatile and volatile memories taught by Wu because (Wu paragraph [0045]) “FIG. 8 illustrates an embodiment of a computer architecture 800, such as the components included in the computer system 100, including a processor 802 that communicates over a bus 804 with a volatile memory device 806 in which programs, operands and parameters being executed are cached, and a non-volatile storage device 804, such as target system memory 136.”. That is, the memory is useful for caching and storing data. Furthermore, volatile memory is useful for storing parameters being actively used because it is typically faster, and non-volatile memory is useful for long-term storage of parameters because non-volatile memory is retained even after the circuit powers off.
Regarding Claim 11
Jin in view of Dennis teaches:
The neural network of claim 10
(see rejection of claim 10)
Jin in view of Dennis does not explicitly teach:
comprising a non-volatile memory, which, in operation, stores the set of reference spike pattern data.
However, Wu teaches:
comprising a non-volatile memory, which, in operation, stores the set of reference spike pattern data
(paragraph [0019]) “In one embodiment, the memory 104 may comprise one or more SRAM memory devices or other non-volatile memory devices known in the art. In an alternative embodiment, the memory 104 may comprise a main memory, such as a DRAM, for storing programs, e.g., 106 and 108, being executed, and a separate non-volatile memory, such as an SRAM or flash memory, storing the spike history array 200[*Examiner notes: set of reference spike pattern data stored in non-volatile memory], now pointer 300, synapse information 400, and neuron membrane potential information 500.”
Jin, Dennis, Wu, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the storage neurons of Jin in view of Dennis by implementing the non-volatile memory taught by Wu because (Wu paragraph [0045]) “FIG. 8 illustrates an embodiment of a computer architecture 800, such as the components included in the computer system 100, including a processor 802 that communicates over a bus 804 with a volatile memory device 806 in which programs, operands and parameters being executed are cached, and a non-volatile storage device 804, such as target system memory 136.”. That is, the memory is useful for caching and storing data. Furthermore, volatile memory is useful for storing parameters being actively used because it is typically faster, and non-volatile memory is useful for long-term storage of parameters because non-volatile memory is retained even after the circuit powers off.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (PGPUB no. US 20150193680 A1) herein referred to as Chan in view of Jin.
Regarding Claim 13
Chan teaches:
A system, comprising: an encoder, which, in operation, generates encoded data based on a data flow, the encoder including a plurality of sets of pairs of spiking neurons, each pair including:
(paragraph [0088]) “A useful neural network model, such as one composed of the levels of neurons 102, 106 of FIG. 1, may encode information via any of various suitable neural coding schemes”
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a first spiking neuron, which, in operation, generates a spike indicating a time of detection of an event in the data flow; and
(paragraph [0105]) “In this example, a square current (indicating the duration and strength of the stimulus) is injected into the receptor neuron[*Examiner notes: first spiking neuron], which depolarizes and spikes immediately after stimulus onset[*Examiner notes: detection of event in data flow], and thereafter generates spikes periodically (as a result of intrinsic somatic noise).”
a second spiking neuron coupled to the first spiking neuron, wherein the second spiking neuron, in operation, generates a spike delayed, with respect to the time of detection of the event, according to an amplitude of the event; and
(paragraph [0097]) “Certain aspects of the present disclosure provide a detector neuron[*Examiner notes: second neuron circuit] postsynaptic to a receptor neuron[*Examiner notes: coupled to the first spiking neuron] (the artificial neuron receiving the stimulus, such as a sensory neuron). The detector neuron responds with a first spike to the onset of an effective stimulus (the primary response, based on a latency code) and with a second spike after an interval (the secondary response, based on a rate code).”; (paragraph [0108]) “Receptor neuron design (top left) is similar to the example in FIG. 11, but here, the magnitude of injected current and onset slope are varied together, resulting in stimuli in which the initial coincident spiking occurs at a characteristic latency as a function of input strength.”
a neural network coupled to the encoder, wherein the neural network, in operation, processes coded signals generated by the encoder,
(paragraph [0088]) “A useful neural network model[*Examiner notes: neural network coupled to the encoder], such as one composed of the levels of neurons 102, 106 of FIG. 1, may encode information via any of various suitable neural coding schemes, such as coincidence coding, temporal coding or rate coding.”
Chan does not explicitly teach:
and the neural network includes: a timing neuron, which, in operation, generates a signal indicative of an attention period; and a set of storage neurons coupled to the timing neuron, wherein the set of storage neurons, in operation, store a set of spike pattern data based on the encoded data.
However, Jin teaches:
and the neural network includes: a timing neuron, which, in operation, generates a signal enabling an attention period; and a set of storage neurons coupled to the timing neuron,
(page 3 column 1 last paragraph) “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron[*Examiner notes: timing neuron] is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive[*Examiner notes: signal enabling an attention period].”
wherein the set of storage neurons, in operation, store a set of spike pattern data based on the encoded data and on the signal enabling the attention period.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired. The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history in the last 48 ms[*Examiner notes: store a set of spike pattern data]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”; (page 3 column 1 last paragraph) “A pre-synaptic time stamp at 2ms resolution is kept in the SDRAM along with each synapse block as shown in Figure 4 (the global ID of the pre-synaptic neuron is added in front of the time stamp for debugging purposes), and is updated when pre-synaptic spikes arrive[*Examiner notes: based on signal enabling the attention period].”
Chan, Jin, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the neuron encoder taught by Chan by storing spike pattern data as taught by Jin because (Jin page 8 column 1 last paragraph) “In this paper we have presented a way to implement an efficient STDP algorithm on the SpiNNaker, a multi-chip neuromorphic parallel hardware with a distributed memory system, where synaptic data is stored on the post-synaptic end and is retrieved only upon the arrival of pre-synaptic spikes. The problem is solved by introducing a pre-synaptic scheme and an associated deferred event-driven model, which permits to update the weights only when a pre-synaptic spike arrives, hence reducing memory requests and indexing process operations. The methods shown in this paper validate the practicality of learning on multi-chip neuromorphic parallel hardware and illustrates ways to translate theoretical learning rules into actual implementation, leading to the further development of universal learning support for spiking neural networks on neuromorphic hardware.”
Regarding Claim 14
Chan in view of Jin teaches:
The system of claim 13
(see rejection of claim 13)
And Jin further teaches:
wherein the set of spike pattern data includes: first parameters indicative of a presence of spikes stored on respective neurons of the set of storage neurons during the attention period; and second parameters indicative of a timing of spikes stored on the respective neurons of the set of storage neurons.
(page 3 column 2 paragraph 1) “The time stamp comprises two parts, a coarse and a fine time. The coarse time is a 32-bit digital value representing the last time the neuron fired[*Examiner notes: first parameters indicative of presence of spikes]. The fine time is a bit-mapped field of 24 bits (bit [31:8]) representing spike history in the last 48 ms[*Examiner notes: second parameters indicative of a timing of spikes]. The coarse time always points to the least significant bit of the fine time (bit 8). As a result, the least significant bit (bit 8) of the fine time is always set.”
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to combine Chan with Jin for the same reasons given in claim 13 above.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chan in view of Jin, and further in view of Julian.
Regarding Claim 15
Chan in view of Jin teaches:
The system of claim 13
(See rejection of claim 13)
Chan in view of Jin does not explicitly teach:
wherein each storage neuron of the set of storage neurons of the neural network is coupled to the plurality of sets of pairs of spiking neurons of the encoder.
However, Julian teaches:
wherein each storage neuron of the set of storage neurons of the neural network is coupled to the plurality of sets of pairs of spiking neurons of the encoder.
(paragraph [0014]) “The apparatus generally includes a processing system and a memory coupled to the processing system[*Examiner notes: corresponds to each storage neuron of the set of storage neurons]. The processing system is typically configured to record spike times for a first artificial neuron, to record spike times for a second artificial neuron coupled to the first artificial neuron via a synapse, to process spikes for the second artificial neuron according to a window based at least in part on the spike times for the first artificial neuron, and to update a parameter of the synapse based on the processing.”
Chan, Jin, Julian, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the neuron encoder and storage neurons taught by Chan in view of Jin with the storage neurons coupled to the neurons as taught by Julian because (Julian paragraph [0014]) “The apparatus generally includes a processing system and a memory coupled to the processing system. The processing system is typically configured to record spike times for a first artificial neuron, to record spike times for a second artificial neuron coupled to the first artificial neuron via a synapse, to process spikes for the second artificial neuron according to a window based at least in part on the spike times for the first artificial neuron, and to update a parameter of the synapse based on the processing.”
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Chan in view of Jin, and further in view of Khellah et al. (PGPUB no. US20190115011A1).
Regarding Claim 16
Chan in view of Jin teaches:
The system according to claim 13
(see rejection of claim 13)
Chan in view of Jin does not explicitly teach:
wherein the encoder comprises a filter, which, in operation, filters the data flow.
However, Khellah teaches:
wherein the encoder comprises a filter, which, in operation, filters the data flow.
(Khellah paragraph [0021]) “In some examples, the front-end module 104 may receive the audio input for preprocessing[*Examiner notes: corresponds to data flow]. The feature generator 106 can generate features including audio parameters. For example, the feature generator 106 can generate a mel-frequency cepstrum (MFC) representation of the received audio input[*Examiner notes: mapped to filter]. As used here, an MFC is a representation of the short-term power spectrum of a sound, based on a linear cosine transform of a log power spectrum on a nonlinear mel scale of frequency. A mel scale is a perceptual scale of pitches judged by listeners to be equal in distance from one another. The MFC may be made up of mel-frequency cepstral coefficients (MFCCs) derived from a type of cepstral representation of the audio”
Chan, Jin, Khellah, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the neuron encoder and storage neurons of Chan in view of Jin with the filter as taught by Khellah because (Khellah paragraph [0017]) “The techniques described herein thus enable a low-power solution for keyword spotting using a sparsely active network based on spikes. The techniques described herein can be used to improve the ability of an always-on keyword spotting system with the ability to recognize more keywords. In particular, the spiking neural network may be a type of sparsely active neural (SAN) network that only processes data as needed. Such an event-driven approach may keep the system inactive unless there is a speech stimulus, thus reducing the power consumption during inactivity.”
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Chan in view of Jin, and further in view of Dennis.
Regarding Claim 17
Chan in view of Jin teaches:
The system of claim 13
(see rejection of claim 13)
Chan in view of Jin does not explicitly teach:
wherein the neurons of the set of storage neurons, in operation, compare first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data.
However, Dennis teaches:
wherein the neurons of the set of storage neurons, in operation, compare first and second parameters of the set of spike pattern data with corresponding first and second parameters of a set of reference spike pattern data.
(page 177 column 2 last paragraph) “To produce a spike coding of this representation, a codebook dictionary is first generated that contains entries representing the variation of local feature information. Here we use k. means clustering to produce the codebook, C. However other approaches are possible, such as sparse coding [12]. For the each entry where z=1…Z in the codebook, Cz, the Euclidean distance is used as the similarity measure, with a local missing feature mask introduced to reduce the influence of the noise on the codebook matching. The distance[*Examiner notes: comparing] between the codebook[*Examiner notes: reference spike pattern data] and a local feature at position (f,t)[*Examiner notes: corresponding first and second parameters] is therefore calculated as follows:”
Chan, Jin, Dennis, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the neuron encoder and storage neurons of Chan in view of Jin by using reference neurons and comparing against them as taught by Dennis because (Dennis page 177 column 2 paragraph 2) “The proposed spike coding is generated by first detecting key-points in the spectrogram, which localise the sparse high-energy peaks in the spectrogram, and then extracting the local spectral information to find the best matching entries in a codebook. The idea is that such peaks will still be present under mismatched noise, and the discriminative local feature information should provide a robust foundation for further processing. The final output can be considered as a novel sparse representation of the spectrogram, since the spike coding preserves the frequency information while outputting a sparse spike coding of the detected local features.”
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Chan in view of Jin, and further in view of Natroshvili et al. (PGPUB no. US20190042942A1) herein referred to as Natroshvili.
Regarding Claim 18:
Chan in view of Jin teaches:
The system of claim 13
(see rejection of claim 13)
Chan in view of Jin does not explicitly teach:
comprising a support vector machine coupled to the neural network, wherein the support vector machine, in operation, generates a recognition signal based on a score signal generated by the neural network.
However, Natroshvili:
comprising a support vector machine coupled to the neural network, wherein the support vector machine, in operation, generates a recognition signal based on a score signal generated by the neural network.
(paragraph [0091]) “At operation 1210, a feature set[*Examiner notes: score signal] is extracted from the sensor data using a SNN.”; (paragraph [0092]) “At operation 1215, an SVM is created for the sensor data using the feature set.”; (paragraph [0097]) “At operation 1220, a second set of sensor data is classified using the SVM.”; (Figure 12)
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Chan, Jin, Natrosshvili, and the instant application are analogous because they are all directed to spiking neural networks.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the present invention to modify the neuron encoder and storage neurons of Chan in view of Jin by coupling a support vector machine to the spiking neural network as taught by Natrosshvili because (Natrosshvili paragraph [0027]) “The computing hardware 105 is arranged to create the SVM 130 for the sensor data 120 using the feature set. Here, the feature set provides the classification (e.g., categorization) of the sensor data 120 that allows a hyperplane to be devised to separate features from different classes. In an example, the SVM 130 is a reduced set vector SVM. A reduced set SVM uses eigenvectors, derived from support vectors, in place of the support vectors. The advantage is a reduction in a number of features to test to classify new data. That is, in a traditional SVM, support vectors provide boundaries for class features. Features of new data is mapping into the SVM feature space and compared to the boundary features. A reduced set SVM replaces the support vectors with eigenvectors that have fewer points to define the same feature boundary. Thus, classification using a reduced set SVM is more efficient.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.J.B./Examiner, Art Unit 2126
/DAVID YI/Supervisory Patent Examiner, Art Unit 2126
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