Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant office action having application number 19/257431, filed on July 1, 2025, has claims 1-20 pending in this application.
Information Disclosure Statemen
The information disclosure statement (IDS) submitted on 07/01/2025 and 02/26/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No.12346343. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 under examination are obvious, respectively, by claims 1-19 of the reference Patent. Every limitations in the instant application under examination claims are recited in the conflicting reference patent claims, and the differences or additional limitations between the claims are highlighted below by underlining and bolding all limitations.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the independent claim 1, of the instant application to obtaining, by the data transform accelerator, metadata based on information in the data transform command, the metadata in the data transform accelerator or spread out in the memory of host computing unit and in the memory of data transform accelerator, wherein obtaining the metadata based on the information in the data transform command includes obtaining command metadata from a first input buffer in the data transform accelerator; and configuring, by the data transform accelerator, a data transform pipeline based on the metadata.
Please, see the comparison table below:
Instant Application 19257431
Patent No. 12346343
1. A method, comprising: determining, by a data transform accelerator, an address associated with a data transform command in a container data structure, the data transform accelerator in communication with a host computing unit; in response to a determination that the address is in the container data structure, accessing, by the data transform accelerator, the data transform command based on the address; obtaining, by the data transform accelerator, metadata based on information in the data transform command; and configuring, by the data transform accelerator, one or more data transform engines based on the metadata.
11. A host device, comprising: data processing hardware; and memory hardware in communication with the data processing hardware, the memory hardware storing instructions that when executed on the data processing hardware cause the data processing hardware to perform operations comprising: generating a container data structure for use by a data transform accelerator that is in data communication with the host device; generating input data in the memory hardware; generating metadata operable to configure one or more data transform engines in a data transform accelerator; reserving an output buffer in the memory hardware; generating a first data transform command in the memory hardware, the first data transform command associated with the input data and the metadata; updating the container data structure with an address of the first data transform command; and in response to the data transform accelerator performing one or more data transform operations, obtaining transformed data from the data transform engines in the data transform accelerator.
1. A method, comprising: determining, by a data transform accelerator, an address associated with a data transform command in a container data structure which is in the data transform accelerator, the data transform accelerator in communication with a host computing unit; in response to a determination that the address is in the container data structure, accessing, by the data transform accelerator, the data transform command based on the address, the data transform command in the host computing unit; obtaining, by the data transform accelerator, metadata based on information in the data transform command, the metadata in the data transform accelerator or spread out in the memory of host computing unit and in the memory of data transform accelerator, wherein obtaining the metadata based on the information in the data transform command includes obtaining command metadata from a first input buffer in the data transform accelerator; and configuring, by the data transform accelerator, a data transform pipeline based on the metadata.
10. A host comprising: data processing hardware; and memory hardware in communication with the data processing hardware, the memory hardware storing instructions that when executed on the data processing hardware cause the data processing hardware to perform operations comprising: generating a container data structure in a data transform accelerator, the data transform accelerator in data communication with the host; generating input data in the memory hardware; generating metadata in the data transform accelerator or spread out in the memory of data transform accelerator and host memory hardware; reserving output buffer in the memory hardware; generating a first data transform command in the memory hardware, the first data transform command associated with the input data and the metadata; and updating the container data structure with an address of the first data transform command, wherein the address of the first data transform command is accessible by a data transform accelerator, wherein accessing the address of the first data transform command by the data transform accelerator causes the data transform accelerator to obtain the input data, to perform one or more data transform operations on the input data based on the metadata, and to transmit output data to the output buffer, the metadata including command metadata being accessible in an input buffer in the data transform accelerator, and wherein the output data is the input data after being transformed by the one or more data transform operations.
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
The application claim 1 does not contain specific limitations as shown in the patent claim 1; however, according to In re Goodman, the application claim 1 is generic to the species of information covered by claim 1 of the patent. Thus, the generic invention is anticipated by the species of the patented invention.
The application claim 11 does not contain specific limitations as shown in the patent claim 10; however, according to In re Goodman, the application claim 11 is generic to the species of information covered by claim 10 of the patent. Thus, the generic invention is anticipated by the species of the patented invention.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 USC 101 because the claimed invention is directed to a judicial exception, namely an abstract idea, without reciting significantly more than the judicial exception.
Step 1 – Statutory Category
Claim 1 is directed to a process and therefore falls within a statutory category of invention.
Step 2A, Prong One – Whether the Claim Recites a Judicial Exception
Claim 1 recites: A method, comprising: determining, by a data transform accelerator, an address associated with a data transform command in a container data structure, the data transform accelerator in communication with a host computing unit; in response to a determination that the address is in the container data structure, accessing, by the data transform accelerator, the data transform command based on the address; obtaining, by the data transform accelerator, metadata based on information in the data transform command; and configuring, by the data transform accelerator, one or more data transform engines based on the metadata.Under the broadest reasonable interpretation, these limitations amount to collecting information, evaluating information, and using the evaluation to make a configuration decision. Such activities constitute mental processes because they can be performed conceptually by a person reviewing information and deciding how resources should be configured. Accordingly, the claim recites an abstract idea in the mental-process category of abstract ideas identified by the USPTO eligibility guidance.
Step 2A, Prong Two – Integration Into a Practical Application
The additional elements include a data transform accelerator, a host computing unit, one or more data transform engines, and a container data structure.These elements are recited at a high level of generality and merely provide an environment in which the abstract idea is performed. The claim does not recite:• a specific accelerator architecture;• a particular improvement to processor operation;• a specialized memory structure;• a technological solution to a technological problem; or• a particular machine implementation that meaningfully limits the claim.The claim merely uses generic computer components to perform the abstract idea. Therefore, the judicial exception is not integrated into a practical application.
Step 2B – Inventive Concept Analysis
The claim does not recite additional elements that amount to significantly more than the abstract idea.The recited accelerator, computing unit, engines, and data structure perform their ordinary and expected functions of storing, accessing, processing, and configuring information. Viewed individually and as an ordered combination, these elements merely implement the abstract idea on generic computer technology.
Claim 1 is directed to an abstract idea and does not integrate the abstract idea into a practical application. Furthermore, the claim does not recite significantly more than the abstract idea. Accordingly, Claim 1 is rejected under 35 U.S.C. § 101.
Claims 2-10 are depending on independent claim 1 and therefore rejected under the same rationale as claim 1 above.
Claim 11 is rejected under 35 U.S.C. § 101 because the claimed invention is directed to a judicial exception, namely an abstract idea, without reciting significantly more than the judicial exception.
Step 1 – Statutory Category
Claim 11 is directed to a machine comprising hardware components and therefore falls within a statutory category of invention.
Step 2A, Prong One – Whether the Claim Recites a Judicial Exception
Claim 11 recites A host device, comprising: data processing hardware; and memory hardware in communication with the data processing hardware, the memory hardware storing instructions that when executed on the data processing hardware cause the data processing hardware to perform operations comprising: generating a container data structure for use by a data transform accelerator that is in data communication with the host device; generating input data in the memory hardware; generating metadata operable to configure one or more data transform engines in a data transform accelerator; reserving an output buffer in the memory hardware; generating a first data transform command in the memory hardware, the first data transform command associated with the input data and the metadata; updating the container data structure with an address of the first data transform command; and in response to the data transform accelerator performing one or more data transform operations, obtaining transformed data from the data transform engines in the data transform accelerator.
Under the broadest reasonable interpretation, these limitations amount to collecting, organizing, storing, and processing information according to rules. The claim further includes creating metadata and command information and using such information to facilitate subsequent processing.These activities constitute mental processes because they involve observation, evaluation, organization, and management of information that can be performed conceptually or with pen and paper. Accordingly, the claim recites an abstract idea within the mental-process category identified in the USPTO's 2019 Revised Patent Subject Matter Eligibility Guidance.
Step 2A, Prong Two – Integration Into a Practical Application
The claim additionally recites data processing hardware, memory hardware, a host device, a data transform accelerator, one or more data transform engines, a container data structure, and an output buffer.These elements are recited at a high level of generality and merely provide a generic computer environment in which the abstract idea is performed.The claim does not recite:• a specific architecture for the data transform accelerator;• a particular improvement to computer functionality;• a specialized memory-management technique;• a technological improvement in data transformation operations;• a particular machine implementation imposing meaningful limits on the claim scope; or• any improvement to the operation of the host device itself.Instead, the additional elements merely use generic computing components as tools to carry out the abstract information-management operations. Therefore, the judicial exception is not integrated into a practical application.
Step 2B – Inventive Concept Analysis
The claim does not recite additional elements that amount to significantly more than the abstract idea.The recited hardware components perform their ordinary and expected functions, including storing information, generating data structures, maintaining memory buffers, processing commands, and receiving results.Rather, the claim is directed to generating, organizing, storing, and using information to facilitate processing operations, which is similar to concepts held ineligible in Alice, Electric Power Group, and Content Extraction.
Claim 11 is directed to an abstract idea and does not integrate the abstract idea into a practical application. Furthermore, the claim does not recite significantly more than the abstract idea. Accordingly, Claim 11 is rejected under 35 U.S.C. § 101.
Claims 12-20 are depending on claim 11 and therefore rejected under the same rationale as claim 11 above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-17 and 19-20 are rejected under 35 USC 102(a)(1) as being anticipated by Kazakov et al. (US 20210374607 A1) (hereinafter Kazakov).
As per claims 1 and 11, determining, by a data transform accelerator, an address associated with a data transform command in a container data structure, the data transform accelerator in communication with a host computing unit [FIG. 2A illustrates details of the APD 116, according to an example. The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands., paragraph 18]; in response to a determination that the address is in the container data structure, accessing, by the data transform accelerator, the data transform command based on the address [The inter-die interconnects 408 communicate data and commands between the memory and machine learning accelerator die 260 and the APD core die 115, as well as the processor 102. In some examples, the inter-die interconnects 408 are coupled directly to compute units 132 of the APD core die 115. The controllers 410 control operations on the memory and machine learning accelerator die 260, such as data transfer and machine learning operations on the machine learning accelerators, paragraph 39]; obtaining, by the data transform accelerator, metadata based on information in the data transform command [The dies are operationally coupled via interconnects that allow transfer of data and commands. The memory and machine learning accelerator die 260 includes memory such as static random access memory and well as machine learning accelerators such as matrix multiplication arithmetic logic units (“ALUs”) that are configured to perform matrix multiplication operations that may be useful for machine learning operations, paragraph 18]; and configuring, by the data transform accelerator, one or more data transform engines based on the metadata [FIG. 3 is a block diagram showing additional details of the graphics processing pipeline 134 illustrated in FIG. 2B, according to an example. The graphics processing pipeline 134 includes stages that each performs specific functionality of the graphics processing pipeline 134. Each stage is implemented partially or fully as shader programs executing in the programmable compute units 132, or partially or fully as fixed-function, non-programmable hardware external to the compute units, paragraph 27].
As per claim 2, Kazakov discloses wherein the container data structure is disposed in the data transform accelerator [The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands, paragraph 18].
As per claim 3, Kazakov discloses wherein the data transform command is disposed in the host computing unit.
As per claim 4, Kazakov discloses wherein the metadata is disposed in the data transform accelerator or is distributed in memory of the host computing unit and memory of the data transform accelerator [The input assembler stage 302 reads primitive data from user-filled buffers (e.g., buffers filled at the request of software executed by the processor 102, such as an application 126) and assembles the data into primitives for use by the remainder of the pipeline. The input assembler stage 302 can generate different types of primitives based on the primitive data included in the user-filled buffers, paragraph 28].
As per claim 5, Kazakov discloses wherein obtaining the metadata based on the information in the data transform command comprises: obtaining command metadata from a first input buffer in the data transform accelerator; obtaining command pre-data from a second input buffer in the data transform accelerator; and obtaining additional command metadata from a third input buffer in the data transform accelerator [The input assembler stage 302 reads primitive data from user-filled buffers (e.g., buffers filled at the request of software executed by the processor 102, such as an application 126) and assembles the data into primitives for use by the remainder of the pipeline. The input assembler stage 302 can generate different types of primitives based on the primitive data included in the user-filled buffers, paragraph 28].
As per claim 6, Kazakov discloses wherein the command metadata specifies data transform operations to be performed by the one or more data transform engines [FIG. 2A illustrates details of the APD 116, according to an example. The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands., paragraph 18].
As per claim 8, Kazakov discloses wherein the additional command metadata comprises at least one of a source token, or an action token [The APD 116 is configured to perform machine learning related tasks. In some implementations, the APD 116 is configured to accept one or both of general purpose compute commands and graphics rendering commands from processor 102, to process those compute and graphics rendering commands, and, in some implementations, to provide pixel output to display device 118 for display, paragraph 16].
As per claim 9, Kazakov discloses the method further comprising:obtaining, by the data transform accelerator, input data based on the information in the data transform command; and performing, by the data transform accelerator, one or more data transform operations on the input data using the data transform engines [The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands, paragraph 18].
As per claim 10, Kazakov discloses the method further comprising transmitting, by the data transform accelerator, output data produced by the data transform engines to the host computing unit [the APD 116 is additionally or alternatively performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor 102) and configured to provide graphical output to a display device 118, paragraph 17].
As per claim 12, Kazakov discloses, wherein: the address of the first data transform command is accessible by the data transform accelerator; accessing the address of the first data transform command by the data transform accelerator causes the data transform accelerator to obtain the input data, to perform the one or more data transform operations on the input data based on the metadata, and to transmit output data to the output buffer; and the output data is the input data after being transformed by the one or more data transform operations [the APD 116 is additionally or alternatively performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor 102) and configured to provide graphical output to a display device 118, paragraph 17].
As per claim 13, Kazakov discloses, wherein the container data structure is disposed in the data transform accelerator [The input assembler stage 302 reads primitive data from user-filled buffers (e.g., buffers filled at the request of software executed by the processor 102, such as an application 126) and assembles the data into primitives for use by the remainder of the pipeline. The input assembler stage 302 can generate different types of primitives based on the primitive data included in the user-filled buffers, paragraph 28].
As per claim 14, Kazakov discloses wherein the metadata is disposed in the data transform accelerator, or the metadata is disposed in memory of the data transform accelerator and in the memory hardware [The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands, paragraph 18].
As per claim 15, Kazakov discloses wherein the host is in the data communication with the data transform accelerator based on peripheral component interconnect express standard [The dies are operationally coupled via interconnects that allow transfer of data and commands., paragraph 18].
As per claim 16, Kazakov discloses wherein generating the first data transform command comprises: generating a first source descriptor pointing to the input data; generating a second source descriptor pointing to the metadata; and generating a destination descriptor pointing to the output buffer [The input assembler stage 302 reads primitive data from user-filled buffers (e.g., buffers filled at the request of software executed by the processor 102, such as an application 126) and assembles the data into primitives for use by the remainder of the pipeline. The input assembler stage 302 can generate different types of primitives based on the primitive data included in the user-filled buffers, paragraph 28].
As per claim 17, Kazakov discloses wherein the metadata specifies the one or more data transform operations to be performed by the data transform accelerator [The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands, paragraph 18].
As per claim 19, Kazakov discloses wherein the data transform accelerator obtains the metadata from an on-chip memory of the data transform accelerator or from a combination of on-chip memory of data transform accelerator and host memory hardware [the APD 116 is additionally or alternatively performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., processor 102) and configured to provide graphical output to a display device 118, paragraph 17].
As per claim 20, Kazakov discloses wherein a second data transform command associates with the metadata, the second data transform command different from the first data transform command [The APD 116 has a stacked die configuration that includes an APD core die 115 and a memory and machine learning accelerator die 260. These dies are physically stacked, with one die on top of the other. The dies are operationally coupled via interconnects that allow transfer of data and commands, paragraph 18].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 18 are rejected under 35 USC 103(a) as being un-patentable over Kazakov et al. (US 20210374607 A1) (hereinafter Kazakov) in view of LeMay (US 20200125770 A1) (hereinafter LeMay).
As per claims 7 and 18, the rejection of claim 7 is incorporated by claim 1 above. However Kazakov does not disclose wherein the command pre-data comprises at least one of: initialization vector, message authentication code, Galois counter mode authentication tag, or additional authentication data. On the other hand, LeMay discloses wherein the command pre-data comprises at least one of: initialization vector, message authentication code, Galois counter mode authentication tag, or additional authentication data [a tweak may compose all or part of an initialization vector (IV) for a block cipher, paragraph 142]. Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Kazakov with LeMay by modifying Kazakov such that the machine learning accelerator of Kazavak directly accessible by LeMay using a separate instruction to clear tag bits is to define an instruction that clears all tag bits in a range of memory are reduced. The motivation for doing so would have been to ensure a better user experience to obtain the memory address to decode the encoded pointer to obtain the memory address.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOOSHA ARJOMANDI whose telephone number is (571)272-9784. The examiner can normally be reached on (571)272-9784.
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May 30, 2026
/NOOSHA ARJOMANDI/Primary Examiner, Art Unit 2166
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