Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 are pending
Claims 1-6, 9-16 and 18-20 are rejected due to non-statutory double patenting issue
Claims 1-3, 5-13 and 15-20 are rejected under 35 USC § 103
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/02/2025
and 07/02/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Non-Statutory Type Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patenVpatents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIN25, or PTO/AIN26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.isp
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by the earlier claim. ln re Longi-759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
1. Instant claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 15 of reference patent:12380035 (reference app#18/194,716). Although the claims at issue are not identical, they are not patentably distinct from each other because of the reasons explained below.
Although the conflicting claims are not identical, they are not patentably distinct from each other because present Claim 1 is merely a more detailed version of the same core method recited in reference claim 15.
1.1 A comparison of Present Claim 1 and reference Claim 15 is as follows:
Present Claim 1 recites:
A method, comprising:
obtaining, by a first cache level, a snoop request from a second cache level, wherein the first cache level includes a first cache memory and a second cache memory storing data evicted from the first cache memory;
Reference claim 15 claims the equivalent limitation: A method comprising:
receiving, by a cache controller of a first cache level, a snoop request from a second cache level directed to a set of data;
Present Claim 1 further recites:
generating, based on the snoop request, a read operation directed to an address;
determining whether the read operation corresponds to a hit in the second cache memory; and
based on determining that the read operation corresponds to a hit in the second cache memory,
determining whether there is a pending write operation directed to the address;
Reference claim 15 claims the equivalent limitation:
determining, by the cache controller, whether the set of data is present in a victim cache memory of the first cache level [or in a queue associated with pending writes to the victim cache memory]
Analysis of Differences: The reading and getting hit is a way to determine the presence of the data.
Present Claim 1 further recites:
based on determining that there is a pending write operation directed to the address,
obtaining data of the pending write operation; and
providing the data to the second cache level.
Reference claim 15 claims the equivalent limitation:
determining, by the cache controller, whether the set of data is present in a victim cache memory of the first cache level or in a queue associated with pending writes to the victim cache memory;
retrieving, by the cache controller, the set of data from either the victim cache memory or the queue; and
providing, by the cache controller, the set of data to the second cache level.
2. Present claim 2 and Present claim 3 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over Claim 17 of reference patent:12380035 (reference app#18/194,716).
2.1. A comparison of Present Claim 2&3 and reference Claim 17 is as follows:
Present Claim 2 recites:
The method of claim 1, wherein:
the first cache level is a level-one (L1) cache; and
the second cache level is a level-two (L2) cache.
Present Claim 3 recites:
The method of claim 1, wherein:
the first cache memory is a main storage; and
the second cache memory is a victim storage.
Reference claim 17 claims the equivalent limitation:
The method of claim 15, wherein:
the victim cache memory is a level-one (L1) cache memory; and
the snoop request is received from a level two (L2) cache controller.
2.2 Analysis of Differences: As per present claim 1, 'the first cache level includes a first cache memory and a second cache memory storing data evicted from the first cache memory'. So, second cache memory is a victim cache and is part of first cache level and hence victim cache is a level-one cache. Also, present claim 1, teaches ‘obtaining, by a first cache level, a snoop request from a second cache level’. Hence snoop request is from second level cache.
3. Present Claim 4 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over second claim element of Claim 15 of reference patent:12380035 (reference app#18/194,716).
3.1 A comparison of Present Claim 4 and reference Claim 15 is as follows:
Present Claim 4 recites:
The method of claim 1, wherein the data of the pending write operation is stored in a store queue coupled to the second cache memory.
Reference claim 15 claims the equivalent limitation in its second claim element:
determining, by the cache controller, whether the set of data is present [in a victim cache memory of the first cache level or] in a queue associated with pending writes to the victim cache memory.
3.2 Analysis of Differences: Pending data being in the store queue coupled to the second cache (victim cache) and determining the data being in a queue associated to the victim cache indicates the same thing.
4. Present claim 5 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over Claim 19 of reference patent:12380035 (reference app#18/194,716).
4.1 A comparison of Present Claim 5 and reference Claim 19 is as follows:
Present Claim 5 recites:
The method of claim 1, wherein:
the first cache level comprises a tag random access memory; and
determining whether the read operation corresponds to a hit in the second cache memory comprises determining whether the read operation corresponds to a hit in the second cache memory based on content of the tag random access memory
Reference claim 19 claims the equivalent limitation:
The method of claim 18, wherein:
the retrieving of the set of data includes comparing the address to contents of a tag random access memory to determine whether the snoop request is associated with a cache hit; and
the translating of the address is performed based on the snoop request being associated with the cache hit.
4.2 Analysis of Differences: Pending data being in the store queue coupled to the second cache (victim cache) as recited in the present claim and determining the data being in a queue associated to the victim cache as recited in the reference claim indicates the same thing.
5. Present claim 6 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over second claim element of Claim 15 of reference patent:12380035 (reference app#18/194,716).
5.1 A comparison of Present Claim 6 and reference Claim 15 element 2 is as follows:
Present Claim 6 recites:
The method of claim 1, comprising:
based on determining that there is no pending write operation directed to the address, obtaining data from the second cache memory; and
providing the data to the second cache level.
Reference claim 15 claims the equivalent limitation in its second claim element:
determining, by the cache controller, whether the set of data is present in a victim cache memory of the first cache level [or in a queue associated with pending writes to the victim cache memory];
5.2 Analysis of Differences: Having no pending data indicates there is no data in the store queue and hence data needs to be picked from second cache which is the victim cache. Reference claim as quoted teaches the same thing.
6. Present claim 9 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over Claim 19 of reference patent:12380035 (reference app#18/194,716).
6.1 A comparison of Present Claim 9 and reference Claim 19 is as follows:
Present Claim 9 recites:
The method of claim 1, comprising:
based on determining that the read operation corresponds to a hit in the second cache memory, translating the address into an address space of the second cache memory.
Reference claim 19 claims the equivalent limitation:
The method of claim 18, wherein:
the retrieving of the set of data includes comparing the address to contents of a tag random access memory to determine whether the snoop request is associated with a cache hit; and
the translating of the address is performed based on the snoop request being associated with the cache hit.
6.2 Analysis of Differences: determining that the read operation corresponds to a hit in the second cache memory (in the first level) in the present claim is similar to determining whether the snoop request is associated with a cache hit where snoop request is from second cache level to a first cache level and hence in both cases cache hit is determined in the first cache level and address translation happens accordingly.
7. Present claim 10 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over Claim 3 and claim 8 of reference patent:12380035 (reference app#18/194,716).
7.1 A comparison of Present Claim 10 and reference Claim 3 and reference claim 8 is as follows:
Present Claim 10 recites:
The method of claim 1, wherein:
the first cache level comprises a first interface and a second interface; and
the first interface has a width different from the second interface.
Reference claim 3 claims the equivalent limitation:
The circuit device of claim 1, wherein the cache controller comprises:
a first interface coupled to a processor; and
a snoop interface coupled to the second cache level.
Reference claim 8 claims the equivalent limitation:
The circuit device of claim 7, wherein the first interface is a scalar interface and the second interface is a vector interface.
7.2 Analysis of Differences: present claim talks about two interfaces of different width in first cache level. Reference claim 3 talks about two interfaces and reference claim 8 talks about two interfaces having different width. So, combination of reference claim 3 and reference claim 8 teaches the same thing that is taught by present claim 10.
8. Present claim 11 is rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over Claim 10 of reference patent:12380035 (reference app#18/194,716).
8.1 A comparison of Present Claim 1 and reference Claim 10 is as follows:
Present Claim 11 recites:
A system, comprising:
a first cache level that includes: a first cache memory;
a second cache memory capable of storing data evicted from the first cache memory; and
a cache controller capable of:
obtaining a snoop request from a second cache level;
generating, based on the snoop request, a read operation directed to an address indicated by the snoop request;
determining whether the read operation corresponds to a hit in the second cache memory; and
based on determining that the read operation corresponds to a hit in the second cache memory,
determining whether there is a pending write operation directed to the address;
based on determining that there is a pending write operation directed to the address,
obtaining data of the pending write operation; and
providing the data to the second cache level.
Reference claim 10 claims the equivalent limitation:
A circuit device comprising:
a processor core; and
a first cache level that includes:
a first main cache memory;
a first victim cache memory configured to receive data evicted from the first main cache memory;
a victim store queue coupled to the first victim cache memory; and
a cache controller coupled to the processor core, to the first victim cache memory, and to the victim store queue; and
a second cache level that includes:
a second cache memory, wherein the cache controller is configured to:
receive a first request to read or write a set of data from the processor core;
receive a snoop request for the set of data from the second cache level; and
provide the set of data from either the victim store queue or the first victim cache memory to the second cache level.
8.2 Analysis of Differences:
Present claim 11 teaches a first cache level that includes a first cache memory and a second cache memory (victim cache). Reference claim 10 teaches a first cache level that includes a first main cache memory (similar to first cache) and a first victim cache memory (similar to second cache).
Present claim 11 teaches obtaining a snoop request from second cache level and generating a read operation and determining a hit in the second cache (victim cache in the first level) provide data from victim cache to second cache level. Reference claim 10 teaches obtaining a snoop request from second cache level and provide data from victim cache to second cache level. Cache controller in reference claim receives a read/write request and receives snooping data in second cache level. Examiner finds no patentably distinct feature in issuing read following snoop or issuing following a read.
Instant claim 12 is a system claim corresponding to the instant method claim 2 and hence suffers the same double patenting issue with claim 17 of reference patent:12380035 (reference app#18/194,716).
Instant claim 13 is a system claim corresponding to the instant method claim 3 and hence suffers the same double patenting issue with claim 17 of reference patent:12380035 (reference app#18/194,716).
Instant claim 14 is a system claim corresponding to the instant method claim 4 and hence suffers the same double patenting issue with second claim element of claim 15 of reference patent:12380035 (reference app#18/194,716).
Instant claim 15 is a system claim corresponding to the instant method claim 5 and hence suffers the same double patenting issue with claim 19 of reference patent:12380035 (reference app#18/194,716).
Instant claim 16 is a system claim corresponding to the instant method claim 6 and hence suffers the same double patenting issue with second claim element of claim 15 of reference patent:12380035 (reference app#18/194,716).
Instant claim 19 is a system claim corresponding to the instant method claim 9 and hence suffers the same double patenting issue with claim 19 of reference patent:12380035 (reference app#18/194,716).
Instant claim 20 is a system claim corresponding to the instant method claim 10 and hence suffers the same double patenting issue with claim 3 and claim 8 of reference patent:12380035 (reference app#18/194,716).
Claim Rejections - 35 USC§ 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over TRAN; THANG M. (US 20120221793 A1)[Tran] in view of Agarwala; Sanjive et al. (US 6484237 B1) in view of Cypher; Robert E. et al. (US 20120117323 A1)
Regarding claim 11
A system, comprising:
a first cache level that includes: a first cache memory (Tran:[0022], Fig. 2: teaches in a single-thread mode,
MMUs 112 are configured to access L1 data cache 238 and second L1 data cache 240 as a victim cache of the first L1 data cache.);
a second cache memory capable of storing data evicted from the first cache memory (Tran:[0022], Fig. 2: teaches in a single-thread mode, MMUs 112 are configured to access L1 data cache 238 and second L1 data cache 240 as a victim cache of the first L1 data cache); and
a cache controller capable of (Tran: [0020-0022], Fig. 1, Fig. 2: teaches MMU 112 controlling accesses to cache 114. Processor 102 further includes two MMUs 112. In single-thread mode, MMUs 112 are configured to access L1 data cache 238 and second L1 data cache 240 as a victim cache of the first L1 data cache. So, in Tran, MMU works as a cache controller and controls both 11 data cache and 11 victim cache.):
Tran teaches main L1 cache and victim L1 cache. Tran also teaches main and victim cache controller. However, Tran did not explicitly teach receiving snoop request from second cache level.
Agarwala discloses:
obtaining a snoop request from a second cache level (Agarwala: Col11/ln24-col11/ln64,(30): teaches level two unified cache 130 generating a snoop cycle to level one data cache 123 in response to a memory access read from level two unified cache 130. );
generating, based on the snoop request, a read operation directed to an address indicated by the snoop request (Agarwala: Col3/ln7-col3/ln12, (13): The snoop unit generates a read snoop access (read operation) to the level one data cache upon a direct memory read access from the directly addressable memory that triggered the snoop operation.)
determining whether the read operation corresponds to a hit in the second cache memory (Agarwala: Col3/ln7-col3/ln12, (13): The level one data cache invalidates a cache entry upon a snoop hit (snoop read hit) following a read snoop access. So, Agarwala teaches determining snoop read hit (read operation following a snoop)); and
based on determining that the read operation corresponds to a hit in the second cache memory, [determining whether there is a pending write operation directed to the address] (Agarwala: Col3/ln7-col3/ln12, (13): The level one data cache invalidates a cache entry upon a snoop hit (snoop read hit) following a read snoop access. So, Agarwala teaches a condition of read hit (read operation following a snoop));
Both Tran and Agarwala represent works within the same field of endeavor, namely information processing devices focusing on coherent data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran in view of Agarwala as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran receiving snoop request associated with data from the lower cache level and receiving the snoop result as used in Agarwala) to have a more cache coherent and efficient data storage and retrieval operation leading to a more reliable and efficient computing system (see also Agarwala Col11/ln24-col11/ln64,(30), Col3/ln7-col3/ln12, (13)).
Tran/Agarwala teaches first and second level 1 cache and teaches receiving snoop request generating read operation to an address indicated by snoop. However, Tran/Agarwala did not explicitly disclose checking pending write operation and forwarding data that is being written.
Cypher discloses:
based on determining that the read operation corresponds to a hit in the second cache memory, determining whether there is a pending write operation directed to the address (Cypher: [0034, 0041]: teaches processor cores 102 each including an L1 data cache 104, and share L2 cache 110. Processor cores 102 also include store queues 106, which buffers pending stores. Program-order FIFO (POFIFO) 200 holds pending stores for the thread in program order. So, Cypher teaches determining/dealing with pending stores.);
based on determining that there is a pending write operation directed to the address, obtaining data of the pending write operation (Cypher: [0034, 0041]: teaches processor cores 102 also include store queues 106, which buffers pending stores. Program-order FIFO (POFIFO) 200 holds pending stores for the thread in program order. Cypher: [0047]: teaches unordered records 220 is a memory structure that includes a set of entries 222 that can each hold a record of an unordered store. Unordered records 220 facilitates data forwarding for read-after-write (RAW) bypass requests); and
providing the data to the second cache level (Cypher: [0047]: teaches during operation, processor 102 performs lookups in unordered records 220, and forwards data from unordered records 220 in response to RAW (read after write) requests. Examiner makes the only acceptable interpretation that is the read happens after a write that is pending and hence valid data for that location is - the data that is pending to be written. Cypher teaches forwarding that valid data).
Both Tran/Agarwala and Cypher represent works within the same field of endeavor, namely information processing devices focusing on coherent data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran/Agarwala in view of Cypher as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran/Agarwala checking for pending write operation and forwarding data to be written in response to a read hit on the same location on a read after write situation as used in Cypher) to have a more cache coherent and efficient data storage and retrieval operation leading to a more reliable and efficient computing system (see also Cypher [0034], [0041], [0047]).
Regarding claim 1, it is a method claim corresponding to the system claim 11 and is rejected for the same reason mutatis mutandis.
Regarding claim 12 Tran/Agarwala/Cypher discloses:
The system of claim 11, wherein:
the first cache level is a level-one (L1) cache (Tran: [0017, 0022]: teaches Level 1 (L1) data cache having a second data cache configured as a victim cache for the first data cache, effectively doubling the size of the level 1 cache. Victim cache 240 stores data evicted from first data cache 238 when the data in first data cache 238 is replaced.); and
the second cache level is a level-two (L2) cache (Tran: [0022] Victim cache 240 is intended to reduce the number of cache misses with first data cache 238 thereby reducing the number of accesses to more power consuming structures such as Level 2 (L2) cache).
Regarding claim 2, it is a method claim corresponding to the system claim 12 and is rejected for the same reason mutatis mutandis.
Regarding claim 13 Tran/Agarwala/Cypher discloses:
The system of claim 11, wherein:
the first cache memory is a main storage (Tran: [0017, 0022]: teaches level 1 (L1) data cache having a second data cache configured as a victim cache for the first data cache, effectively doubling the size of the level 1 cache. So, level 1 has two data cache, a main cache storage 238 and a victim cache 240.); and
the second cache memory is a victim storage (Tran: [0017, 0022]: teaches Level 1 (L1) data cache having a second data cache configured as a victim cache for the first data cache, effectively doubling the size of the level 1 cache. So, level 1 has two data cache, a main cache storage 238 and a victim cache 240.).
Regarding claim 3, it is a method claim corresponding to the system claim 13 and is rejected for the same reason mutatis mutandis.
Regarding claim 15 Tran/Agarwala/Cypher discloses:
The system of claim 11, wherein:
the first cache level comprises a tag random access memory (Agarwala: col8/ln48-col9/ln17,(20), (22): teaches data cache having two tag memory ports, one for each load/store unit of central processing unit 110. The tag memory includes address and tag bits. The dual ported tag memory permits simultaneous data access by the two load/store units of central processing unit 110 or one load/store unit access and a snoop cycle access by level two unified cache 130. By design all caches includes tag memory and Agarwala teaches it); and
the cache controller is capable of determining whether the read operation corresponds to a hit in the second cache memory based on content of the tag random access memory (Agarwala: col9/ln18-col9/ln41, (23): teaches central processing unit 110 reading its register file and generating a memory address transmitting the address to level one data cache 123 on a read and transmitting the address and data to level one data cache 123 on a write. Teaches, level one data cache 123 performing tag lookup and address comparisons, and accessing the data on a cache hit and sending load data to central processing unit 110.).
Regarding claim 5, it is a method claim corresponding to the system claim 15 and is rejected for the same reason mutatis mutandis.
Regarding claim 16 Tran/Agarwala/Cypher discloses:
The system of claim 11, wherein the cache controller is capable of:
based on determining that there is no pending write operation directed to the address, obtaining data from the second cache memory (Agarwala: col9/ln18-col9/ln41, (23): teaches central processing unit 110 reading its register file and generating a memory address transmitting the address to level one data cache 123 on a read. Teaches, level one data cache 123 performing tag lookup and address comparisons, and accessing the data on a cache hit.); and
providing the data to the second cache level (Agarwala: col9/ln18-col9/ln41, (23): teaches central processing unit 110 reading its register file and generating a memory address transmitting the address to level one data cache 123 on a read. Teaches, level one data cache 123 performing tag lookup and address comparisons, and accessing the data on a cache hit. Agarwala: col8/ln48-col9/ln17,(20), (22): teaches data cache having two tag memory ports, one for each load/store unit of central processing unit 110. Each of the two tag memories includes address and tag bits. The dual ported tag memory permits simultaneous data access by one load/store unit access and a snoop cycle access by level two unified cache 130. If the read is originated due to a snoop by level two or second level cache and it is a snoop read hit then data is provided to the level two or second level cache that initiated the read.).
Regarding claim 6, it is a method claim corresponding to the system claim 16 and is rejected for the same reason mutatis mutandis.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over TRAN (US 20120221793 A1)[Tran] in view of Agarwala et al. (US 6484237 B1) in view of Cypher et al. (US 20120117323 A1) in view of Mulla et al. (US 6507892 B1)
Regarding claim 17 Tran/Agarwala/Cypher discloses all the limitation of claim 11. However, Tran/Agarwala/Cypher did not explicitly disclose MESI protocol.
Mulla discloses:
The system of claim 11, wherein the cache controller is capable of:
based on determining that the read operation corresponds to a hit in the second cache memory (Agarwala: Col3/ln7-col3/ln12, (13): teaches determining snoop read hit (read operation following a snoop) and taking action accordingly),
determining a modified, exclusive, shared, or invalid (MESI) state associated with the address of the second cache memory (Mulla: Col3/ln28-col3/ln55, (11): teaches a way tag match signal indicating whether a match for the physical address was made within the cache level's tag(s) 612. In multi-processor systems, a MESI protocol is typically utilized to indicate whether a line in cache is modified and exclusive, shared, or invalid. Accordingly, in such multi-processor systems the MESI protocol is combined with the way tag match signal to indicate whether a "true" tag hit has been achieved for a level one cache. Thus, in multi-processor systems a true tag hit is achieved when both a tag match is found for tag(s) 612 and the MESI protocol indicates that such tag match is a valid match. Accordingly, in FIG. 6, MESI circuitry 614 is utilized to calculate a "true" tag hit signal to determine whether a true tag hit has been achieved for that level of cache. MESI protocol is a well known, well established method and Mulla teaches it. Any person ordinarily skilled in the art can apply MESI protocol to determine status of contents of some locations in cache.).
Both Tran/Agarwala/Cypher and Mulla represent works within the same field of endeavor, namely information processing devices focusing on coherent data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran/Agarwala/Cypher in view of Mulla as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran/Agarwala/Cypher using MESI protocol to determine state of cache line as used in Mulla) to have a more cache coherent and efficient data storage and retrieval operation leading to a more reliable and efficient computing system (see also Mulla Col3/ln28-col3/ln55, (11)).
Regarding claim 7, it is a method claim corresponding to the system claim 17 and is rejected for the same reason mutatis mutandis.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over TRAN (US 20120221793 A1)[Tran] in view of Agarwala et al. (US 6484237 B1) in view of Cypher et al. (US 20120117323 A1) in view of Mulla et al. (US 6507892 B1) in view of Damron et al. (US 6785796 B1)
Regarding claim 18 Tran/Agarwala/Cypher/Mulla discloses all the limitation of claim 17.
Damron discloses:
The system of claim 17, wherein:
the first cache level comprises a random access memory (Damron: claim 10: teaches first-level cache memory comprises static random access memory (SRAM).); and
wherein the cache controller is capable of determining the MESI state based on content of the random access memory (Mulla: Col3/ln28-col3/ln55, (11): teaches a way tag match signal indicating whether a match for the physical address was made within the cache level's tag(s) 612. In multi-processor systems, a MESI protocol is typically utilized to indicate whether a line in cache is modified and exclusive, shared, or invalid.).
Both Tran/Agarwala/Cypher/Mulla and Damron represent works within the same field of endeavor, namely information processing devices focusing on coherent data storage and retrieval operations. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran/Agarwala/Cypher/Mulla in view of Damron as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran/Agarwala/Cypher/Mulla using random access memory as cache as used in Damron) to have a more cache coherent and efficient data storage and retrieval operation leading to a more reliable and efficient computing system (see also Damron claim 10).
Regarding claim 8, it is a method claim corresponding to the system claim 18 and is rejected for the same reason mutatis mutandis.
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over TRAN (US 20120221793 A1)[Tran] in view of Agarwala et al. (US 6484237 B1) in view of Cypher et al. (US 20120117323 A1) in view of Favor et al. (US 8019944 B1)
Regarding claim 19 Tran/Agarwala/Cypher discloses all the limitation of claim 11. However, Tran/Agarwala/Cypher did not explicitly disclose translating the address into an address space.
The system of claim 11, wherein the cache controller is capable of:
based on determining that the read operation corresponds to a hit in the second cache memory (Agarwala: Col3/ln7-col3/ln12, (13): teaches determining snoop read hit (read operation following a snoop) and taking action accordingly), translating the address into an address space of the second cache memory (Favor: col25/ln5-col25/ln10, (168): teaches performing linear address (LA) to physical address (PA) translation, and various cache verifications. Favor: col53/ln11-col53/ln35, (303): teaches MU (memory unit) executing no more than one memory-accessing operation accessing each bank of the cache in a given clock cycle or pipeline stage. Virtual addresses are generated, and the virtual addresses are then translated to physical addresses, such as by an address translation mechanism. Later pipeline stages use virtual and/or physical addresses.).
Both Tran/Agarwala/Cypher and Favor represent works within the same field of endeavor, namely information processing devices focusing on data storage and retrieval operations including memory and data protections in case of power outage. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran/Agarwala/Cypher in view of Favor as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran/Agarwala/Cypher translating addresses as used in Favor) to have more reliable and cache coherent data storage and retrieval operation leading to a more reliable and efficient computing system (see also Favor col25/ln5-col25/ln10, (168)).
Regarding claim 9, it is a method claim corresponding to the system claim 19 and is rejected for the same reason mutatis mutandis.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over TRAN (US 20120221793 A1)[Tran] in view of Agarwala et al. (US 6484237 B1) in view of Cypher et al. (US 20120117323 A1) in view of Koeplinger et al. (US 20200241844 A1)
Regarding claim 20 Tran/Agarwala/Cypher discloses all the definition of claim 11. However, Tran/Agarwala/Cypher did not explicitly disclose cache having two different interface.
Koeplinger discloses:
The system of claim 11, wherein:
the first cache level comprises a first interface and a second interface (Koeplinger: [0042] FIG. 2A: teaches a switch unit connecting elements in an array level network. A switch unit have 8 interfaces. A set of two switch units have connections to an Address Generation and Coalescing Unit (AGCU) that include multiple address generation (AG) units and a coalescing unit (CU) connected to the multiple address generation units. The coalescing unit (CU) arbitrates between the AGs and processes memory requests using interfaces including a vector interface, a scalar interface, and a control interface to communicate with the vector network, the scalar network, and the control network); and
the first interface has a width larger than the second interface (Koeplinger: [0046]: teaches A configurable unit can interface with the scalar, vector, and control buses using three corresponding sets of inputs and outputs (IO): scalar inputs/outputs, vector inputs/outputs, and control inputs/outputs. Scalar IOs can be used to communicate single words of data. Vector IOs can be used to communicate vectors of data, in cases such as receiving configuration data in a unit configuration load process, and transmitting and receiving data during operation after configuration across a long pipeline between multiple PCUs. Having scalar and vector interface indicates the two interfaces are of different size).
Both Tran/Agarwala/Cypher and Koeplinger represent works within the same field of endeavor, namely information processing devices focusing on data storage and retrieval operations including memory and data protections in case of power outage. It would therefore have been obvious to one of ordinary skill in the art before the claimed invention was effectively filed to apply Tran/Agarwala/Cypher in view of Koeplinger as it represents a combination of known prior art elements according to known methods (cache coherent processor architecture of Tran/Agarwala/Cypher using two interfaces to memory as used in Koeplinger) to have more reliable and cache coherent data storage and retrieval operation leading to a more reliable and efficient computing system (see also Koeplinger [0042]).
Regarding claim 10, it is a method claim corresponding to the system claim 20 and is rejected for the same reason mutatis mutandis.
Potential Allowable Subject Matter
Claims 4 and 14 are being objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 and 14 are also subject to non-statutory double patenting rejection and will also need to overcome that double patenting issue as outlined above in order to be allowed.
The following is an Examiner's statement of reasons for potential allowability:
Claim 14 recites ‘The system of claim 11, wherein the first cache level comprises a store queue coupled to the second cache memory, and wherein the data of the pending write operation is stored in the store queue’
Regarding claim 14 Tran/Agarwala/Cypher discloses:
The system of claim 11, wherein the first cache level comprises [a store queue coupled to the second cache memory], and wherein the data of the pending write operation is stored in the store queue (Spec [0092] and Claim 3 defines second cache memory as a victim storage (victim cache) storing evicted data from first cache. Cypher: [0034-0035]: teaches Processor cores 102 each include an L1 data cache 104, and share L2 cache 110. Processor cores 102 also include store queues 106, which buffer pending stores. During a store operation, processor core 102 first performs a lookup for a corresponding cache line in L1 data cache 104. If the lookup generates a miss in L1 data cache 104 (or if store queue 106 is not empty), processor core 102 creates an entry for the store in store queue 106 and sends a corresponding request for the store to L2 cache 110.).
However, second cache is the victim cache and Cypher did not explicitly disclose the store queue is attached to the victim cache.
No known prior arts taken alone or in combination teach having a store queue coupled to a victim cache.
Claim 4 recites, ‘The method of claim 1, wherein the data of the pending write operation is stored in a store queue coupled to the second cache memory.’
So, method claim 4 contains the same allowable subject matter ‘having a store queue coupled to a victim cache’ as present in the system claim 14 and is potentially allowable for the same reason as system claim 14.
Conclusion
The prior arts made of record and not relied upon that is considered pertinent to applicant's disclosure is recorded in pe2e_search_notes.pdf and is attached as OA.APPENDIX.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammad Hasan whose telephone number is (571) 270 1737 (email: Mohammad.Hasan@uspto.gov). The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the Examiner's supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571- 273-8300.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138
Prosecution Insights