DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 7/2/2025.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/2/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…receiving a host command including: a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels; and accessing second data striped with the first data via a second channel of the number of channels as identified based at least in part on comparing the first and second numerical values” (independent claim 1, lines 2-9).
The Examiner is uncertain if the recitation of “…receiving a host command including: a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels…” means any of the following possible interpretations:
“a host command” that includes “a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels” is received;
“a host command is received,” and “a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels” are also received; or
some other possible, unconsidered interpretation.
The Examiner is uncertain if the recitation of “…accessing second data striped with the first data via a second channel of the number of channels as identified based at least in part on comparing the first and second numerical values” means any of the following possible interpretations:
“second data striped with the first data” is accessed “via a second channel of the of the number of channels” in which “a second channel of the number of channels” is “identified based at least in part on comparing the first and second numerical values”;
“second data striped” “via a second channel of the number of channels” is “identified based at least in part on comparing the first and second numerical values” and accessed “with the first data”; or
some other possible, unconsidered interpretation.
The Examiner is uncertain if the recitation of “the first and second numerical values” refers to “a first numerical value assigned to a first row segment configured for first data” and “a second numerical value assigned to a first channel of a number of channels.”
For the sake of examination, the Examiner has interpreted “…receiving a host command including: a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels; and accessing second data striped with the first data via a second channel of the number of channels as identified based at least in part on comparing the first and second numerical values” to read “…receiving a host command that includes both a first address bit indicative of a first numerical value assigned to a first row segment configured for first data and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels; and, accessing second data that was striped with the first data using a second channel of the number of channels that is identified based at least in part on comparing the first numerical value and the second numerical value.”
Dependent claims 2-6, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 7-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 7 recites “…compare, in response to receipt of a host command, a first numerical value to a second numerical value to identify a second channel to access second data striped with first data, wherein the host command comprises: a first address bit indicative of the first numerical value assigned to a first row segment configured to the first data; and a second address bit indicative of the second numerical value assigned to a first channel of the number of channels; and access the second data via the second channel as identified based at least in part on a result of the comparison” (independent claim 7, lines 2-12).
The Examiner is uncertain if the recitation of “…access the second data via the second channel as identified based at least in part on a result of the comparison” means any of the following possible interpretations:
“the second data” is accessed “via the second channel” that is “identified based at least in part on a result of the comparison”;
“the second data” “identified based at least in part on a result of the comparison” is access “via the second channel”; or
some other possible, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…compare, in response to receipt of a host command, a first numerical value to a second numerical value to identify a second channel to access second data striped with first data, wherein the host command comprises: a first address bit indicative of the first numerical value assigned to a first row segment configured to the first data; and a second address bit indicative of the second numerical value assigned to a first channel of the number of channels; and access the second data via the second channel as identified based at least in part on a result of the comparison” to read “…compare, in response to receipt of a host command, a first numerical value to a second numerical value to identify a second channel to access second data striped with first data, wherein the host command comprises both a first address bit indicative of the first numerical value assigned to a first row segment configured to the first data and a second address bit indicative of the second numerical value assigned to a first channel of the number of channels; and access, by using the second channel that was identified based at least in part on a result of comparing the first numerical value to the second numerical value, the second data.”
Dependent claims 8-9, which ultimately depend from independent claim 7, are rejected for carrying the same deficiencies.
Claims 10-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 10 recites “…a number of channels; and a controller configured to: receive a host command including: a first address bit indicative of a first numerical value assigned to a row segment of a number of row segments configured to host data; and a second address bit indicative of a second numerical value assigned to a base channel associated with a first channel corresponding to the host data; and to access the host data and parity data striped with the host data: compare the first and second numerical values to determine if the second numerical value is less than a difference between a particular amount and the first numerical value; identify a row a memory cells of the first channel configured for the host data based at least in part on the first and second address bits; and identify a second channel and a row of memory cells configured for the parity data based at least in part on the comparison” (independent claim 10, lines 2-18).
The Examiner is uncertain if the recitation of “…a host command including: a first address bit indicative of a first numerical value assigned to a row segment of a number of row segments configured for host data; and a second address bit indicative of a second numerical value assigned to a base channel associated with a first channel corresponding to the host data…” means any of the following possible interpretations:
“a host command” that includes “a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels” is received;
“a host command is received,” and “a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels” are also received; or
some other possible, unconsidered interpretation.
The Examiner is uncertain if the recitation of “the first and second numerical values” refers to “a first numerical value assigned to a row segment of a number of row segments configured for host data” and “a second numerical value assigned to base channel associated with a first channel corresponding to the host data.”
For the sake of examination, the Examiner has interpreted “…a number of channels; and a controller configured to: receive a host command including: a first address bit indicative of a first numerical value assigned to a row segment of a number of row segments configured to host data; and a second address bit indicative of a second numerical value assigned to a base channel associated with a first channel corresponding to the host data; and to access the host data and parity data striped with the host data: compare the first and second numerical values to determine if the second numerical value is less than a difference between a particular amount and the first numerical value; identify a row a memory cells of the first channel configured for the host data based at least in part on the first and second address bits; and identify a second channel and a row of memory cells configured for the parity data based at least in part on the comparison” to read “…a number of channels; and a controller configured to: receive a host command including both a first address bit indicative of a first numerical value assigned to a row segment of a number of row segments configured to host data and a second address bit indicative of a second numerical value assigned to a base channel associated with a first channel corresponding to the host data; and for the controller to access the host data and parity data striped with the host data: compare the first numerical value assigned and the second numerical value to determine if the second numerical value is less than a difference between a particular amount and the first numerical value; identify a row a memory cells of the first channel configured for the host data based at least in part on the first and second address bits; and identify a second channel and a row of memory cells configured for the parity data based at least in part on the comparison.”
Dependent claims 11-20, which ultimately depend from independent claim 10, are rejected for carrying the same deficiencies.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 7 of the instant application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 11 of U.S. Patent No. 12,379,994 (“Balluchi”) in view of USPGPUB 2022/0207193 (“Caraccio”). The following tables, in which similarities between claims 1 and 7 of the instant application and claims 1 and 7 of Balluchi are highlighted in bold, and accompanying reasoning illustrate that claims 1 and 7 of the instant application are not patentably distinct from claims 1 and 7 of Balluchi in view of Caraccio:
Instant Application, Claim 1
Balluchi, Claim 1
1. A method, comprising: receiving a host command including: a first address bit indicative of a first numerical value assigned to a first row segment configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels; and accessing second data striped with the first data via a second channel of the number of channels as identified based at least in part on comparing the first and second numerical values.
1. A method, comprising: receiving a host command including: a first address bit indicative of a first numerical value assigned to a row segment of a first memory device configured for first data; and a second address bit indicative of a second numerical value assigned to a first channel of a number of channels and corresponding to the first memory device; and identifying a second channel of the number of channels and corresponding to a second memory device configured for second data that are striped with the first data based at least in part on comparing the first and second numerical values.
Claim 1 of Balluchi does not appear to explicitly claim accessing second data; however, in an analogous art, Caraccio teaches security management of ferroelectric memory device.
As per claim 1 of the instant application, Caraccio particularly teaches:
accessing second data: (Caraccio, paragraph 0062, where data striped across multiple channels is accessed. Caraccio therefore particularly teaches accessing second data).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Caraccio and the claims of Balluchi before them before the instant application was effectively filed, to modify the system of Balluchi to include the principles of Caraccio of accessing data striped across multiple channels.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance by implementing multiple data lanes in order to increase the amount of data that may be accessed (Caraccio, paragraph 0048).
Instant Application, Claim 7
Balluchi, Claim 7
7. An apparatus, comprising: a number of channels; and a controller coupled to the number of channels, the controller configured to: compare, in response to receipt of a host command, a first numerical value to a second numerical value to identify a second channel to access second data striped with first data, wherein the host command comprises: a first address bit indicative of the first numerical value assigned to a first row segment configured for the first data; and a second address bit indicative of the second numerical value assigned to a first channel of the number of channels; and access the second data via the second channel as identified based at least in part on a result of the comparison.
7. An apparatus, comprising: a number of memory devices respectively corresponding to a number of channels; and a controller coupled to the number of memory devices via the number of channels, the controller configured to: receive a first address bit of a host command, the first address bit indicative of a first numerical value assigned to a row segment of a first memory device configured for first data; receive a second address bit of the host command, the second address bit indicative of a second numerical value assigned to a first channel of the number of channels; compare, in response to receipt of the host command, the first and second numerical values to identify a second channel corresponding to a second memory device configured for second data striped with the first data; and access the first memory device identified based at least in part on the first and the second address bits; and access the second memory device identified based at least in part on a result of the comparison.
Claim 7 of Balluchi does not appear to explicitly claim access second data; however, in an analogous art, Caraccio teaches security management of ferroelectric memory device.
As per claim 7 of the instant application, Caraccio particularly teaches:
access second data: (Caraccio, paragraph 0062, where data striped across multiple channels is accessed. Caraccio therefore particularly teaches access second data).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Caraccio and the claims of Balluchi before them before the instant application was effectively filed, to modify the system of Balluchi to include the principles of Caraccio of accessing data striped across multiple channels.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance by implementing multiple data lanes in order to increase the amount of data that may be accessed (Caraccio, paragraph 0048).
Claim 10 of the instant application is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7, and 11 of U.S. Patent No. 12,379,994 (“Balluchi”). The following table, in which similarities between claim 10 of the instant application and claim 11 of Balluchi are highlighted in bold, and accompanying reasoning illustrate that claim 10 of the instant application is not patentably distinct from claim 11 of Balluchi:
Instant Application, Claim 10
Balluchi, Claim 11
10. An apparatus, comprising: a number of channels; and a controller configured to: receive a host command including: a first address bit indicative of a first numerical value assigned to a row segment of a number of row segments configured for host data; and a second address bit indicative of a second numerical value assigned to a base channel associated with a first channel corresponding to the host data; and to access the host data and parity data striped with the host data: compare the first and second numerical values to determine if the second numerical value is less than a difference between a particular amount and the first numerical value; identify a row of memory cells of the first channel configured for the host data based at least in part on the first and second address bits; and identify a second channel and a row of memory cells configured for the parity data based at least in part on the comparison.
11. An apparatus, comprising: a number of memory devices respectively corresponding to a number of channels, wherein the number of memory devices comprise a number of row segments each comprising a respective set of rows of memory cells of each memory device of the number of memory devices; and a controller coupled to the number of memory devices via the number of channels, the controller configured to: receive a host command including: a first address bit indicative of a first numerical value assigned to a row segment of the number of row segments configured for host data; and a second address bit indicative of a second numerical value assigned to a base channel associated with a first memory device configured for the host data; and to access the host data and parity data striped with the host data: compare the first and second numerical values to determine if the second numerical value is less than a difference between a particular amount and the first numerical value; identify a row of memory cells of the first memory device configured for the host data based at least in part on the first and second address bits; and identify a second memory device and a row of memory cells configured for the parity data based at least in part on the comparison.
While claim 11 of Balluchi does not appear to claim “identify a second channel and a row of memory cells configured for the parity data based at least in part on the comparison,” the Examiner notes that claim 11 of Balluchi claims “identify a second memory device and a row of memory cells configured for the parity data based at least in part on the comparison.” The Examiner notes that identification of a second memory device necessarily identifies a channel (i.e., a second channel used by the second memory device.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
U.S. Patent No. 11,119,855: teaches storage of parity data among different RAID stripes of a memory system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
Prosecution Insights