NON-FINAL REJECTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-2, 5-7, 8-9, 12-15, and 18-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-9, and 13 of U.S. Patent No. 11,977,774. Although the claims at issue are not identical, they are not patentably distinct from each other because as shown below.
Regarding claim 1, U.S. Patent No. 11,977,774 discloses:
A system comprising:
a memory device (claim 1: a memory device); and
a processing device, operatively coupled with the memory device, to perform operations comprising (claim 1: a processing device, operatively coupled with the memory device, to perform operations):
responsive to determining that a representative number of program erase cycles (PECs) for a set of blocks of the memory device satisfies a condition, setting one or more trim values associated with the set of blocks according to the representative number of PECs for the set of blocks (claim 9: identifying an average number of program erase cycles (PECs) for the block family; responsive to determining that the average number of PECs satisfies a criterion, setting one or more trims associated with the block family), wherein each programmed block in the set of blocks was programmed within at least one of: a specified time window or a specified temperature window (claim 9: wherein the block family represents a set of blocks programmed within at least one of: a specified time window or a specified temperature range); and
responsive to receiving a write command directed to a block of the set of blocks (claim 9: receiving a write command directed to a block of a memory device), executing the write command according to the one or more trim values (claim 9: executing the write command according to the one or more trims).
Regarding claim 2, U.S. Patent No. 11,977,774 further discloses:
The system of claim 1, wherein the representative number of PECs comprises an average number of PECs for the set of blocks (claim 9: identifying an average number of program erase cycles (PECs) for the block family).
Regarding claim 5, U.S. Patent No. 11,977,774 further discloses:
The system of claim 1, further comprising:
identifying an entry in a data structure, wherein the entry is associated with the representative number of PECs (claim 13: identifying an entry in a first data structure, wherein the entry is associated with the average number of PECs); and
identifying a set of trims associated with the entry in the data structure, wherein the set of trims comprises the one or more trim values (claim 13: identifying a set of trims associated with the entry in the first data structure).
Regarding claim 6, U.S. Patent No. 11,977,774 further discloses:
The system of claim 1, wherein the operations are performed responsive to at least one of:
a power on event of the system, or a predetermined time interval (claim 7: wherein the operations are performed responsive to at least one of: a power on event of the system or a predetermined time interval.).
Regarding claim 7, U.S. Patent No. 11,977,774 further discloses:
The system of claim 1, wherein the one or more trim values comprise at least one of: an erase trim, a voltage programming trim, or a base trim associated with a threshold voltage distribution of a cell of the memory device (claim 8: wherein the one or more write trims comprise at least one of: an erase trim, a voltage programming trim, or a base trim associated with a threshold voltage distribution of a cell of the memory device).
Claims 8-9, 12-15, and 18-20 recite limitations substantially similar to limitations 1-2 and 5-7. Therefore, claims 8-9, 12-15, and 18-20 are rejected under the same reasoning as claims 1-2 and 5-7.
Allowable Subject Matter
Claims 3-4, 10-11 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and/or upon filing a Terminal Disclaimer as discussed above.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is the examiner’s statement of reasons for allowance:
While one or more reasons are offered below citing reasons that the claims are allowable over the prior art, it is each claim taken as a whole, including interrelationships and interconnections between various claimed elements, which are allowable over the prior art of record and not any individual limitation of a claim. The prior art of Pangal et al. (US 2014/0082460), when taken alone or in combination with the other prior art of record, fails to anticipate and/or make obvious to one of ordinary skill in the art the claimed invention prior to the effective filing date. Pangal et al. discloses implementing a plurality of different trim profiles that are changed after a fixed number of cycles executed on the flash device and or based on a trigger such as a Block Fail Rate (BFR) or an ECC event ([0026], [0030]-[0031], Fig. 4). Pangal et al. do not appear to explicitly teach the limitation “setting one or more trim values associated with a set of blocks of the memory device according to a representative number of program erase cycles (PECs) for the set of blocks, wherein each programmed block in the set of blocks was programmed within at least one of: a specified time window or a specified temperature range” of independent claims 1, 8, and 14.
Regarding claim 1, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A system comprising: a memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: responsive to determining that a representative number of program erase cycles (PECs) for a set of blocks of the memory device satisfies a condition, setting one or more trim values associated with the set of blocks according to the representative number of PECs for the set of blocks, wherein each programmed block in the set of blocks was programmed within at least one of: a specified time window or a specified temperature window; and responsive to receiving a write command directed to a block of the set of blocks, executing the write command according to the one or more trim values.”
Regarding claim 8, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A method comprising: responsive to determining that a representative number of program erase cycles (PECs) for a set of blocks of a memory device satisfies a condition, setting one or more trim values associated with the set of blocks according to the representative number of PECs for the set of blocks, wherein each programmed block in the set of blocks was programmed within at least one of: a specified time window or a specified temperature window; and responsive to receiving a write command directed to a block of the set of blocks, executing the write command according to the one or more trim values.”
Regarding claim 14, the prior art, alone or in combination, does not disclose the following limitations, as claimed, in combination with the other claimed limitations:
“A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: responsive to determining that a representative number of program erase cycles (PECs) for a set of blocks of a memory device satisfies a condition, setting one or more trim values associated with the set of blocks according to the representative number of PECs for the set of blocks, wherein each programmed block in the set of blocks was programmed within at least one of: a specified time window or a specified temperature window; and responsive to receiving a write command directed to a block of the set of blocks, executing the write command according to the one or more trim values.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Penzo et al. (US 2022/0406380) teach determining an initial program voltage for work lines of a non-volatile memory based on a number of program erase cycles.
Hsiao et al. (US 2019/0012228) teach reading data from a non-volatile memory device.
Duzly et al. (US 2016/0342347) teach charge loss mitigation throughout the lifecycle of memory devices by proactive window shift.
Lee (US 2016/0307633) teaches performing erase loops on a memory block using a first voltage, performing program loops on memory cells of the memory block using a second voltage, and increasing the first and second voltages based on program/erase cycle information for the memory cells.
Shen (US 2016/0103630) teaches a system in which a first health scheme may be applied that emphasizes a program/erase count to determine a health status associated with the memory based on the memory being in a first life stage associated with a beginning-of-life condition of the memory. When the memory is in a second life stage associated with an end-of-life condition of the memory, a second health scheme may be applied that emphasizes a failed bit count to determine the health status associated with the memory
Liu (US 2015/0036428) teaches an incrementally programmed non-volatile memory.
Xia et al. (US 2014/0119113) teach threshold voltage adjustment in non-volatile memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137
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