DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
1. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12382599. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of the instant application is anticipated by patent claim 1 in that claim 1 of the patent contains all the limitations of claim 1 of the instant application. Claim 1 of the instant application therefore is not patently distinct from the earlier patent claim and as such is unpatentable for nonstatutory double patenting because claim 1 of the instant application is anticipated by patent claim 1. Please see comparison table as below. See In re Goodman(CA FC) 29 USPQ2d 2010(12/3/1993)
And the limitations of the remaining claims 2-20 are found, with minor variations in the recitation of Patent claims 2-20.
Patent (U.S. Patent No. 12,382,599)
Instant Application (19/258,193)
A semiconductor memory device comprising:
An information processing system comprising: a semiconductor memory device; and a host configured to supply a power of a first power supply and a power of a second power supply to the semiconductor memory device, the second power supply having a voltage equal to or lower than that of the first power supply, wherein the semiconductor memory device includes:
a housing having a first surface, a second surface located on a side opposite to the first surface, a first end edge extending in a first direction, a second end edge located on a side opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion where a notch between the first end edge and the first side edge is formed;
a housing having a first surface, a second surface located on a side opposite to the first surface, a first end edge extending in a first direction, a second end edge located on a side opposite to the first end edge and extending in the first direction, a first side edge extending in a second direction intersecting the first direction, and a first corner portion where a notch between the first end edge and the first side edge is formed;
a nonvolatile memory;
a nonvolatile memory;
a controller configured to control the nonvolatile memory; and
a controller configured to control the nonvolatile memory; and
a plurality of terminals provided on the first surface, wherein the terminals include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals, the first plurality of terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge, the third plurality of terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge, the second plurality of terminals are arranged between the first plurality of terminals and the third plurality of terminals in the first direction with intervals, the first plurality of terminals are closer to the first end edge than the second plurality of terminals are, the first plurality of terminals include at least one pair of first signal terminals for differential data signals, the differential data signals complying with PCIe standard, the first plurality of terminals include a first plurality of ground terminals assigned to ground, each pair of the at least one pair of first signal terminals is located between two of the first plurality of ground terminals, the second plurality of terminals include a second plurality of ground terminals assigned to ground, the third plurality of terminals include differential clock signal terminals assigned to differential clock signals, a single-end signal terminal assigned to a single-end signal, a first power supply terminal assigned to a first power supply and one or more second power supply terminals assigned to a second power supply having a voltage equal to or lower than that of the first power supply, the first power supply terminal is configured to be supplied with a current having one of a first plurality of set current values, and the one or more second power supply terminals are configured to be supplied with a current having one of a second plurality of set current values.
a plurality of terminals provided on the first surface, the terminals include a first plurality of terminals, a second plurality of terminals, and a third plurality of terminals, the first plurality of terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge, the third plurality of terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge, the second plurality of terminals are arranged between the first plurality of terminals and the third plurality of terminals in the first direction with intervals, the first plurality of terminals are closer to the first end edge than the second plurality of terminals are, the first plurality of terminals include at least one pair of first signal terminals for differential data signals, the differential data signals complying with PCIe standard, the first plurality of terminals include a first plurality of ground terminals assigned to ground, each pair of the at least one pair of first signal terminals is located between two of the first plurality of ground terminals, the second plurality of terminals include a second plurality of ground terminals assigned to ground, the third plurality of terminals include differential clock signal terminals assigned to differential clock signals, a single-end signal terminal assigned to a single-end signal, a first power supply terminal assigned to the first power supply and one or more second power supply terminals assigned to the second power supply, the first power supply terminal is configured to be supplied with a current having one of a first plurality of set current values, and the one or more second power supply terminals are configured to be supplied with a current having one of a second plurality of set current values.
3. As per Okada’s reference (Pub. No. US20120117315) discloses the semiconductor memory card comprising a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector, at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal and the clock pin in the first mode are changed to a pin pair for differential clock signal to function as the pin pair for differential clock signal. Whereas Matsumoto’s reference (Pub. No. US2017/0010639) discloses a high-speed signal complying with the PCIe standard, for example, is transmitted between the host interface unit 53 and the host apparatus but do not disclose as Applicant’s recites claims.
Conclusion
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
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