DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Foreign Priority
This application is a continuation of U.S. Patent Application No. 18/429,027 filed on 01/31/2024 that claims priority to Korean Patent Application No. 10-2023-0013070 filed on 01/31/2023. On 07/22/2025, an electronic copy of this document was retrieved by the USPTO, and thus on the office action summary sheet examiner has checked off the box “all” certified copies have been received at this time.
Specification Objections
The specification is objected to because the title is not descriptive. See MPEP 606.01 – “Where the title is not descriptive of the invention claimed, the examiner should require the substitution of a new title that is clearly indicative of the invention to which the claims are directed”. Correction is needed. Examiner suggests by way of example the following title: “DISPLAY PANEL HAS MULTIPLEXERS CONNECTED TO PIXELS THAT INCLUDE SUBPIXELS, AND DISPLAY APPARATUS”.
The abstract needs to be amended to: (i) remove “are provided” so that the abstract is clear and concise (see MPEP Section 608, especially – “It should avoid using phrases which can be implied, such as ‘The disclosure concerns’”); and (ii) remove “a display panel and a display apparatus” to not repeat information from the title (see MPEP Section 608, especially – “The language…should not repeat information given in the title”).
Claim Objections
Claims 3 and 7-9, 11-14 and 18-19 are objected to because of the following informalities:
Claim 3 at lines 3-4 includes “a driving transistor a first light-emitting element” that lacks proper punctuation. This objection may be overcome, for example, by amending claim 3 at lines 3-4 to “a driving transistor; a first light-emitting element”. Appropriate correction is required. This objection applies to claims 8-9, 11-14 and 18-19 that depend upon claim 3.
Claim 7 at line 3 includes “at narrow viewing angle”, which is grammatically incorrect. This objection may be overcome, for example, by amending claim 7 at line 3 to “at a narrow viewing angle”. Appropriate correction is required.
Claim Rejections – 35 USC §112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly
pointing out and distinctly claiming the subject matter which the inventor or a joint inventor
regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly
claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 at lines 7-10 includes “angel mode” the meaning of which is indefinite. This grounds of rejection may be overcome by changing this to “angle mode” in each of lines 7-10. Appropriate correction is required. This rejection applies to claims 2-19 that depend upon claim 1.
Claim 4 at line 4 includes “angel mode” the meaning of which is indefinite. This grounds of rejection may be overcome by changing this to “angle mode”. Appropriate correction is required. This rejection applies to claims 5-6 that depend upon claim 4.
Claim 5 at line 2 includes “angel mode” the meaning of which is indefinite. This grounds of rejection may be overcome by changing this to “angle mode”. Appropriate correction is required.
Claim 6 at line 1 includes “a first pixel”, however it is unclear whether applicant is referring to “a first pixel” in claim 1 at line 2 or to another pixel. This grounds of rejection may be overcome by changing claim 6 at line 1 to “the first pixel”. This would provide proper antecedent basis for “the first pixel” in claim 6 at line 2. Appropriate correction is required.
Claim 7 at line 1 includes “the at least one first lens” that lacks antecedent basis. Note claim 3 at lines 10-11 includes “at least one first lens”, however claim 6 does not depend upon claim 3. This grounds of rejection may be overcome by changing claim 7 at line 1 to “at least one first lens”. Appropriate correction is required.
Claim 7 at line 2 includes “the at least one second lens” that lacks antecedent basis. Note claim 3 at lines 12-13 includes “at least one second lens”, however claim 6 does not depend upon claim 3. This grounds of rejection may be overcome by changing claim 7 at line 2 to “at least one second lens”. Appropriate correction is required.
Claim 8 at lines 1-2 includes “the wide angle mode” that lacks antecedent basis. This grounds of rejection may be overcome by changing claim 1 at line 7 to “a wide angle mode”. Appropriate correction is required.
Claim 8 at line 2 includes “the first control signal” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by changing claim 8 at line 2 to “a first control signal”. Appropriate correction is required.
Claim 8 at line 3 includes “the narrow angle mode” that lacks antecedent basis. This grounds of rejection may be overcome by changing claim 1 at line 11 to “a narrow angle mode”. Appropriate correction is required.
Claim 8 at line 3 includes “the second control signal” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by changing claim 8 at line 3 to “a second control signal”. Appropriate correction is required.
Claim 9 at lines 1-2 includes “the wide angle mode” that lacks antecedent basis. This grounds of rejection may be overcome by changing claim 1 at line 7 to “a wide angle mode”. Appropriate correction is required.
Claim 9 at line 2 includes “the first control signal” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by changing claim 9 at line 2 to “a first control signal”. Appropriate correction is required.
Claim 9 at line 3 includes “the narrow angle mode” that lacks antecedent basis. This grounds of rejection may be overcome by changing claim 1 at line 11 to “a narrow angle mode”. Appropriate correction is required.
Claim 9 at line 3 includes “the second control signal” that lacks antecedent basis. This grounds of rejection may be overcome, for example, by changing claim 9 at line 3 to “a second control signal”. Appropriate correction is required.
Claim 12 at line 5 includes “the first direction” that lacks antecedent basis. Note that claim 7 at line 2 includes “a first direction”, however claim 12 does not depend upon claim 7. This grounds of rejection may be overcome, for example, by changing claim 12 at line 5 to “a first direction”. Appropriate correction is required.
Claim 13 at line 6 includes “the first direction” that lacks antecedent basis. Note that claim 7 at line 2 includes “a first direction”, however claim 13 does not depend upon claim 7. This grounds of rejection may be overcome, for example, by changing claim 13 at line 6 to “a first direction”. Appropriate correction is required.
Claim 14 at lines 4-5 includes “a plurality of the second lenses” that lacks antecedent basis. Note that claim 13 at line 3 includes “a plurality of second lenses”, however claim 14 does not depend upon claim 13. This grounds of rejection may be overcome, for example, by changing claim 14 at lines 4-5 to “a plurality of second lenses”. This would provide proper antecedent basis for “the second lenses” in claim 14 at line 8. Appropriate correction is required.
Claim 18 at line 1 includes “the display panel” that lacks antecedent basis. Note that claim 15 at line 2 includes “a display panel”, however claim 18 does not depend upon claim 15. This grounds of rejection may be overcome, for example, by changing claim 18 at line 1 to “a first display panel”. Appropriate correction is required.
Claim 18 at line 3 includes “a view angel of the first display area” the meaning of which is indefinite. This grounds of rejection may be overcome by changing this to “a view angle of the first display area”. Appropriate correction is required. This rejection applies to claim 19 that depends upon claim 18.
Claim 18 at line 5 includes “a view angel of the second display area” the meaning of which is indefinite. This grounds of rejection may be overcome by changing this to “a view angle of the second display area”. Appropriate correction is required. This rejection applies to claim 19 that depends upon claim 18.
Claim 19 at line 1 includes “the display panel” that lacks antecedent basis. Note that claim 15 at line 2 includes “a display panel”, however claim 19 does not depend upon claim 15. This grounds of rejection may be overcome, for example, by changing claim 19 at line 1 to “a first display panel”. Appropriate correction is required.
Claim 19 at line 3 includes “a view angel of the third display area” the meaning of which is indefinite and lacks antecedent basis. Note that claim 4 includes “a third multiplexer”, however claim 19 does not depend upon claim 4. This grounds of rejection may be overcome by changing this to “a view angle of a third display area”. Appropriate correction is required.
Claim Rejections – Nonstatutory Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
9. Claims 1-3, 8-10, 15 and 18-19 are rejected based on nonstatutory double patenting as being unpatentable over claims 14-15 and 19 of U.S. Patent No. 12,374,270 B2 in view of U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”).
See the below juxtaposition of applicant’s claims to those of U.S. Patent No. 12,374,270 B2.
Claim 1 of the present application
Claim 14 of U.S. Patent No. 12,374,270 B2
A display apparatus, comprising:
a first pixel including a first subpixel;
a second pixel including a second subpixel;
a first multiplexer circuit connected to the first pixel; and a second multiplexer circuit connected to the second pixel;
wherein: in a first mode, the first pixel is configured to operate at a wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at the wide angle mode by controlling the second multiplexer circuit; and in a second mode, the first pixel is configured to operate at the wide angel mode by controlling the first multiplexer circuit and the second pixel is configured to operate at a narrow angle mode by controlling the second multiplexer circuit.
A display apparatus, comprising:
a display panel including a plurality of pixel blocks including a plurality of subpixels disposed in a display area and a plurality of multiplexer circuits disposed in a bezel area adjacent to the display area, supplying first and second mode control signals to each of the plurality of pixel blocks; and
wherein each of the multiplexer circuits activates one of the first mode control signal and the second mode control signal based
Claim 2 of the present application
Claim 19 (depends on claims 14-15) of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 1, wherein: the first multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the first pixel; and the second multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the second pixel.
Claim 14: wherein each of the multiplexer circuits activates one of the first mode control signal and the second mode control signal based on a control signal
Claim 19: The display apparatus of claim 15, wherein each of the plurality of multiplexer circuits outputs a gate-on voltage as the first mode control signal and outputs a gate-off voltage as the second mode control signal based on the control signal indicating a wide viewing angle mode.
Claim 3 of the present application
Claim 19 (depends on claims 14-15) of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 2, wherein each of the first subpixel and the second subpixel includes: a driving transistor a first light-emitting element; a second light-emitting element;
a first mode control transistor configured to connect the driving transistor and the first light-emitting element in response to the first mode control signal; a second mode control transistor configured to connect the driving transistor and the second light-emitting element in response to the second mode control signal;
a first lens area disposed on the first light-emitting element, the first lens area including at least one first lens; and a second lens area disposed on the second light-emitting element, the second lens area including at least one second lens.
Claim 14: each of the subpixels includes:
a first light-emitting element connected to a driving transistor through a first mode control transistor controlled by the first mode control signal; a second light-emitting element connected to the driving transistor through a second mode control signal
Claim 14: a first lens area disposed on the first light-emitting element, the first lens area including at least one lens; and a second lens area disposed on the second light-emitting element, the second lens area including at least one lens
Claim 10 of the present application
Claim 14 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 2, wherein each of the first multiplexer circuit and second multiplexer circuit includes: a first switching element configured to output a gate-on voltage as the second mode control signal based on a control signal; a second switching element configured to output a gate-off voltage as the second mode control signal based on an inverted control signal opposite to the control signal; a third switching element configured to output the gate-on voltage as the first mode control signal based on the inverted control signal; and a fourth switching element configured to output the gate-off voltage as the first mode control signal based on the control signal.
a plurality of multiplexer circuits
Claim 11 of the present application
Claim 22 (depends on claims 14-15) of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 3, wherein each of the first subpixel and the second subpixel further includes: a storage capacitor connected to a gate electrode of the driving transistor;
a first switching transistor configured to supply a data voltage of a data line to a first electrode of the storage capacitor based on a first scan signal of a first gate line;
a second switching transistor configured to connect the driving transistor to a diode structure based on a second scan signal of a second gate line;
a third switching transistor configured to supply an initialization voltage of an initialization voltage line to the first electrode of the storage capacitor based on an emission control signal of a third gate line;
a fourth switching transistor configured to connect the driving transistor with the first and second mode control transistors based on the emission control signal of the third gate line;
a fifth switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the second light-emitting element based on the second scan signal of the second gate line; and
a seventh switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the first light-emitting element based on the second scan signal of the second gate line.
Claim 14: a plurality of subpixels
Claim 22: The display apparatus of claim 15, wherein each subpixel further includes: a storage capacitor connected to a gate electrode of the driving transistor;
a first switching transistor supplying a data voltage of a data line to a first electrode of the storage capacitor based on a first scan signal of a first gate line;
a second switching transistor connecting the driving transistor to a diode structure based on a second scan signal of a second gate line;
a third switching transistor supplying an initialization voltage of an initialization voltage line to the first electrode of the storage capacitor based on an emission control signal of a third gate line;
a fourth switching transistor connecting the driving transistor with the first and second mode control transistors based on the emission control signal of the third gate line;
a fifth switching transistor supplying the initialization voltage of the initialization voltage line to an anode electrode of the second light-emitting element based on the second scan signal of the second gate line; and
a seventh switching transistor supplying the initialization voltage of the initialization voltage line to an anode electrode of the first light-emitting element based on the second scan signal of the second gate line.
Claim 12 of the present application
Claim 11 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 3, wherein: the first light-emitting element includes a first light emission area, and the first lens area includes a first lens; and the first lens overlaps the first light emission area, has a bottom surface wider than the first light emission area, controls a viewing angle in the first direction at a wide viewing angle, and controls a viewing angle in a second direction perpendicular to the first direction at a narrow viewing angle.
The display panel of claim 4, wherein: the first light-emitting element includes a first light emission area, and the first lens area includes a first lens; and the first lens overlaps the first light emission area, has a bottom surface wider than the first light emission area, controls a viewing angle in the first direction at a wide viewing angle, and controls a viewing angle in a second direction perpendicular to the first direction at a narrow viewing angle.
Claim 13 of the present application
Claim 12 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 3, wherein: the second light-emitting element includes a plurality of second light emission areas, and the second lens arca includes a plurality of second lenses that overlap the plurality of second light emission areas, respectively; and each of the plurality of second lenses has a bottom surface wider than each of the plurality of second light emission areas and controls a viewing angle in the first direction and a second direction perpendicular to the first direction at a narrow viewing angle.
The display panel of claim 4, wherein:
the second light-emitting element includes a plurality of second light emission areas, and the second lens area includes a plurality of second lenses that overlap the plurality of second light emission areas, respectively; and
each of the plurality of second lenses has a bottom surface wider than each of the plurality of second light emission areas and controls a viewing angle in the first direction and a second direction perpendicular to the first direction at a narrow viewing angle.
Claim 14 of the present application
Claim 13 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 3, wherein: each of the first pixel and the second pixel includes a first colored subpixel, a second colored subpixel and a third colored subpixel;
the first lens area includes the first lens, and the second lens area includes a plurality of the second lenses;
a size of the first lens of at least one of the first, second and third colored subpixels is different;
and a number of the second lenses of at least one of the first, second and third colored subpixels is different.
The display apparatus of claim 4, wherein: the plurality of subpixels includes a first colored subpixel, a second colored subpixel and a third colored subpixel;
the first lens area includes a first lens, and the second lens area includes a plurality of the second lenses;
a size of the first lens is different for each of the first, second and third colored subpixels;
and a number of the second lenses is different for each of the first, second and third colored subpixels.
Claim 15 of the present application
Claim 14 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 2, wherein: the first pixel and the second pixel are disposed in a display area of a display panel, and the first multiplexer circuit and the second multiplexer circuit are disposed in a bezel area adjacent to the display area.
A display apparatus, comprising:
a display panel including a plurality of pixel blocks including a plurality of subpixels disposed in a display area and a plurality of multiplexer circuits disposed in a bezel area adjacent to the display area
Claim 16 of the present application
Claim 17 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 15, wherein each of the first multiplexer circuit and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller.
The display apparatus of claim 15, wherein each of the plurality of multiplexer circuits and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller.
Claim 17 of the present application
Claim 6 of U.S. Patent No. 12,374,270 B2
The display apparatus of claim 16, wherein each of the first multiplexer circuit and the second multiplexer circuit is selectively configured to output a gate-on voltage and a gate-off voltage as the first and second mode control signals based on the control signal.
The display panel of claim 4, wherein each of the plurality of multiplexer circuits selectively outputs a gate-on voltage and a gate-off voltage as the first and second mode control signals based on the control signal.
As to claim 1, claim 14 of U.S. Patent No. 12,374,270 B2 does not expressly disclose a first multiplexer circuit connected to the first pixel; and a second multiplexer circuit connected to the second pixel; wherein: in a first mode, the first pixel is configured to operate at a wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at the wide angle mode by controlling the second multiplexer circuit; and in a second mode, the first pixel is configured to operate at the wide angel mode by controlling the first multiplexer circuit and the second pixel is configured to operate at a narrow angle mode by controlling the second multiplexer circuit.
Cohen discloses wherein: in a first mode(content displayed to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A)(¶¶0014, 0036), the first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at a wide angle mode (FIGs. 2A, 4A: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404; ¶¶0022, 0024, 0036) and the second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at the wide angle mode(FIGs. 2A, 4A: a pixel 202A displaying confidential information, e.g., a pixel 202A using 204A in part of 406; ¶¶0022, 0024, 0036); and in a second mode(content displayed to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B)(¶¶0024, 0037), the first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at the wide angel mode (FIGs. 2A, 4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404; ¶¶0022, 0024, 0037) and the second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at a narrow angle mode (FIGs. 2A, 4B: a pixel 202A displaying confidential information, e.g., a pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0037).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2 with Cohen to provide a display apparatus that is able to protect confidential or sensitive content from being viewed by an unauthorized user (¶0014).
Shikina discloses a first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) connected to the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072); and a second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) connected to the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072);
the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at a wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) and the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at the wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099); and
the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at the wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) and the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at a narrow angle FIGs. 3, 6: 27, 312; ¶¶0064, 0074) mode by controlling the second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2 and Cohen and Shikina to provide a display apparatus that is able to switch pixels between a wide angle mode and a narrow angle mode using commonly used circuit components.
Yokoyama discloses a first multiplexer circuit(28a, 28G directly connected to pixels in a first row of pixels )(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) connected to the first pixel(a first 15m in a first row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106); and a second multiplexer circuit(28a, 28G directly connected to pixels in a second row of pixels)(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) connected to the second pixel(a first 15m in a second row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106);
the first pixel(a first 15m in a first row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106) is configured to operate by controlling the first multiplexer circuit(28a, 28G directly connected to pixels in a first row of pixels )(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) and the second pixel(a first 15m in a second row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106) is configured to operate by controlling the second multiplexer circuit(28a, 28G directly connected to pixels in a second row of pixels)(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen and Shikina with Yokohama to provide a display apparatus that provides first and second mode control signals using simple circuit components.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach in a first mode, the first pixel is configured to operate at a wide angle mode by controlling the first multiplexer circuit (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A: a pixel 202A using 204A to display nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: 26, 311, a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and the second pixel is configured to operate at the wide angle mode by controlling the second multiplexer circuit (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected confidential information, e.g., a pixel 202A using 204A in part of 406 to display confidential information; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 311; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels); and
in a second mode, the first pixel is configured to operate at the wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at a narrow angle mode by controlling the second multiplexer circuit (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B: a pixel 202A using 204A to display nonconfidential information in a wide angle mode, and a pixel 202A displaying confidential information in a narrow angle mode, e.g., a pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60 controls a pixel 14 in a first region of 11, a second 60 controls a pixel 14 in a second region of 11, 26, 311, 27, 312; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – first and second multiplexer circuits {FIGs. 12a, 13b, 14a: 28a, 28G}, which are directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels and a first 15m in a second row of pixels).
As to claim 2, Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 1, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach wherein: the first multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the first pixel (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404 and the pixel 202A displaying confidential information e.g., the pixel 202A using 206A in the part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 5-6: 54, 57-58, P2: ON or OFF of M3, P3: OFF or ON of M4; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}); and the second multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the second pixel (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 406, and the pixel 202A displaying confidential information, e.g., the pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 5-6: 54, 57-58, P2: ON or OFF of M3, P3: OFF or ON of M4; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a second row of pixels; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 8, Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach wherein the first subpixel operates the wide angle mode when the first control signal of the first multiplexer circuit is activated (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A ON and adjacent 206A OFF of the pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 26 is activated for wide angle mode by P2/M3 ON while P3/M4 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a ON to turn 14a ON while 28Gbl turns 26b OFF to turn 14b OFF), and the first subpixel operates the narrow angle mode when the second control signal of the first multiplexer circuit is activated (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A OFF and adjacent 206A ON of the pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 27 is activated for narrow angle mode by P3/M4 ON while P2/M3 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a OFF to turn 14a OFF while 28Gbl turns 26b ON to turn 14b ON).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 9, Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach wherein the second subpixel operates the wide angle mode when the first control signal of the second multiplexer circuit is activated (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: in part 406: a 204A ON and adjacent 206A OFF of the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 26 is activated for wide angle mode by P2/M3 ON while P3/M4 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a ON to turn 14a ON while 28Gbl turns 26b OFF to turn 14b OFF), and the second subpixel operates the narrow angle mode when the second control signal of the second multiplexer circuit is activated (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: in part 406: a 204A OFF and adjacent 206A ON of the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 3: one of 31, 32 and 33; FIG. 6: 26 and 27; ¶¶0048-0051, 0093; Shikina: FIGs. 1, 3, 6: a first 60, 27 is activated for narrow angle mode by P3/M4 ON while P2/M3 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a OFF to turn 14a OFF while 28Gbl turns 26b ON to turn 14b ON).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 10, Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 2, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach wherein each of the first multiplexer circuit (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A: a pixel 202A using 204A to display nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: 26, 311, a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and second multiplexer circuit (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected confidential information, e.g., a pixel 202A using 204A in part of 406 to display confidential information; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 311; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels) includes: a first switching element configured to output a gate-on voltage as the second mode control signal based on a control signal (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Shikina: FIGs. 5-6: 54, 57-58, M4 ON to provide narrow angle display mode; ¶¶0069, 0073, 0095; Yokoyama: FIG. 14A: PMOS of 28Gb outputs a VDD/ON signal to 26a based on control signal {FIG. 14A: Sig_trim signal} during the second mode when 26a is turned on); a second switching element configured to output a gate-off voltage as the second mode control signal based on an inverted control signal opposite to the control signal (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Shikina: FIGs. 5-6: 54, 57-58, M4 OFF during narrow angle display mode; ¶¶0069, 0073, 0096; Yokoyama: FIG. 14A: NMOS of 28G outputs a VSS/OFF signal to 26b based on a signal 2Gal, which is inverted to the control signal {FIG. 14A: Sig_trim signal}); a third switching element configured to output the gate-on voltage as the first mode control signal based on the inverted control signal (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Shikina: FIGs. 5-6: 54, 57-58, ON signal to M3 during wide angle viewing mode; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, LS1, LS3, LED_SEL1, LED_SEL2, Vga, PMOS of 28Ga outputs an ON signal via its lower drain/source terminal to 26a, which is due to is an inverted signal of the signal output by 28t; ¶¶0093, 0098-0100, 0106); and a fourth switching element configured to output the gate-off voltage as the first mode control signal based on the control signal (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Shikina: FIGs. 5-6: 54, 57-58, OFF signal to M4 during wide angle viewing mode; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, LS1, LS3, LED_SEL1, LED_SEL2, Vga, NMOS of 28Gbl outputs an VSS/OFF signal to 26b, which based on the signal output by 28t; ¶¶0093, 0098-0100, 0106).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
10. Claim 7 is rejected based on nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,374,270 B2 in view of U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) as applied to claim 1 above, in view of U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”).
As to claim 7, claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 1, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach to control a viewing angle in a wide viewing angle, and to control the viewing angle at narrow viewing angle (Claim 14 of U.S. Patent No. 12,374,270 B2: see claim chart above; Cohen: FIGs. 2A, 4A-4B; ¶¶0014, 0022, 0024, 0036-0037 - in the first mode {content displayed to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A}, the second pixel operates in the wide angle mode {FIGs. 2A, 4A: a pixel 202A displaying confidential information when an unauthorized has not been detected , e.g., a pixel 202A using 204A in part of 406}; and in the second mode {content displayed to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B}, the second pixel 202A operates in the narrow angle mode displaying confidential information, e.g., a pixel 202A using 206A in part of 406; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 27, 311, 312; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099).
The motivation to combine the additional teachings of Shikina is for the same reasoning set forth above for claim 1.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama do not expressly disclose wherein the at least one first lens is configured to control a viewing angle in a first direction at a wide viewing angle, and the at least one second lens is configured to control the viewing angle in the first direction at narrow viewing angle.
Shin discloses wherein the at least one first lens(area of 442 above 320)(FIG. 4; ¶¶0078, 0081) is configured to control a viewing angle in a first direction(above 430) at a wide viewing angle (FIG. 4: L2; ¶0081), and the at least one second lens is configured to control the viewing angle in the first direction(above 430) at narrow viewing angle (FIG. 4: L1; ¶0081).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with Shin to provide a display apparatus: (i) having a flat surface; and (ii) that is better able to display content to a viewer not directly in front of the display panel (see e.g., ¶0081, especially - “a relatively wide viewing angle”).
11. Claims 11-14 and 16-19 are rejected based on nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,374,270 B2 in view of U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) as applied to claim 3 above, in view of claims 11-13, 17 and 22 of U.S. Patent No. 12,374,270 B2.
As to claim 11, claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein each of the first subpixel and the second subpixel further includes: a storage capacitor connected to a gate electrode of the driving transistor; a first switching transistor configured to supply a data voltage of a data line to a first electrode of the storage capacitor based on a first scan signal of a first gate line;
a second switching transistor configured to connect the driving transistor to a diode structure based on a second scan signal of a second gate line;
a third switching transistor configured to supply an initialization voltage of an initialization voltage line to the first electrode of the storage capacitor based on an emission control signal of a third gate line;
a fourth switching transistor configured to connect the driving transistor with the first and second mode control transistors based on the emission control signal of the third gate line;
a fifth switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the second light-emitting element based on the second scan signal of the second gate line; and
a seventh switching transistor configured to supply the initialization voltage of the initialization voltage line to an anode electrode of the first light-emitting element based on the second scan signal of the second gate line.
Claim 22 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 22 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that is able to display images with uniform brightness by compensating for threshold voltage variation of each pixels driving transistors.
As to claim 12, claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein: the first light-emitting element includes a first light emission area, and the first lens area includes a first lens; and the first lens overlaps the first light emission area, has a bottom surface wider than the first light emission area, controls a viewing angle in the first direction at a wide viewing angle, and controls a viewing angle in a second direction perpendicular to the first direction at a narrow viewing angle.
Claim 11 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 11 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that is able to display content with a wide viewing angle using a simple component.
As to claim 13, claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein: the first light-emitting element includes a first light emission area, and the first lens area includes a first lens; and the first lens overlaps the first light emission area, has a bottom surface wider than the first light emission area, controls a viewing angle in the first direction at a wide viewing angle, and controls a viewing angle in a second direction perpendicular to the first direction at a narrow viewing angle.
Claim 12 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 12 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that is able to display content with a narrow viewing angle using a simple component.
As to claim 14, claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 3, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein: each of the first pixel and the second pixel includes a first colored subpixel, a second colored subpixel and a third colored subpixel;
the first lens area includes the first lens, and the second lens area includes a plurality of the second lenses; a size of the first lens of at least one of the first, second and third colored subpixels is different; and a number of the second lenses of at least one of the first, second and third colored subpixels is different.
Claim 13 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 13 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that is able to display colored content having uniform luminance.
As to claim 16, claims 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 15, as applied above.
Claim 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein each of the first multiplexer circuit and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller.
Claim 17 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claims 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 17 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that displays images that are brighter and with higher resolution (i.e., by maximizing the display area).
As to claim 17, claims 14 and 17 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 15, as applied above.
Claims 14 and 17 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama does not expressly disclose wherein each of the first multiplexer circuit and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller.
Claim 6 of U.S. Patent No. 12,374,270 B2 discloses these limitations (see above claim chart).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify claims 14 and 17 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama with claim 6 of U.S. Patent No. 12,374,270 B2 to provide a display apparatus that displays images that are brighter and with higher resolution (i.e., by maximizing the display area).
As to claim 18, claims 12, 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 13, as applied above.
Claims 12, 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach wherein the display panel includes a first display area and a second display area (Claims 12, 14 of U.S. Patent No. 12,374,270 B2: see above claim chart; Cohen: FIGs. 2A, 4A-4B: 201A, a pixel 202A in part of 404, a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1-3: 11, 14, a pixel 14 in a first region of 11, a pixel 14 in a second region of 11; ¶¶0030-0031, 0033, 0035-0036, 0047, 0049-0052, 0071-0072), wherein a view angel of the first display area changed by controlling by the first multiplexer circuit (Claims 12, 14 of U.S. Patent No. 12,374,270 B2: see above claim chart; Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0073-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}), wherein a view angel of the second display area changed by controlling by the second multiplexer circuit (Claims 12, 14 of U.S. Patent No. 12,374,270 B2: see above claim chart; Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a second row of pixels; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 19, claims 12, 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama teach the display apparatus of claim 18, as applied above.
Claims 12, 14 of U.S. Patent No. 12,374,270 B2, Cohen, Shikina and Yokohama further teach wherein the display panel (Claims 12, 14 of U.S. Patent No. 12,374,270 B2: see above claim chart; Cohen: FIG. 2A: 201A, 202A; ¶0022; Shikina: FIGs. 1-3: 11, 14; ¶¶0030, 0033, 0047, 0071) further includes a third display area (Cohen: FIGs. 2A, 4A-4B: 201A, a third pixel in part of a second 404 or a second 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1-3: 11, 14, a second pixel 14 in a first region of 11 or a first pixel 14 in a third region of 11; ¶¶0030-0031, 0033, 0035-0036, 0047, 0049-0052, 0071-0072), wherein a view angel of the third display area changed by controlling by the third multiplexer circuit (Claims 12, 14 of U.S. Patent No. 12,374,270 B2: see above claim chart; Cohen: FIGs. 2A, 4A-4B: 201A, a third pixel in part of a second 404 or a second 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1-3: 11, 14, a second pixel 14 in a first region of 11 or a first pixel 14 in a third region of 11; ¶¶0030-0031, 0033, 0035-0036, 0047, 0049-0052, 0071-0072; Yokohama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a second row of pixels; ¶¶0098-0100, 0106 – a third multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a third row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
The motivation to combine the additional teachings of Cohen, Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
Claim Rejections – 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
13. Claims 1-2, 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”).
As to claim 1, Cohen discloses a display apparatus(101)(FIGs. 1, 2A: 102, 201A; ¶¶0021-0022), comprising:
a first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) including a first subpixel(in part 404: a 204A and adjacent 206A of the pixel 202A)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037);
a second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) including a second subpixel(in part 406: a 204A and adjacent 206A of a pixel 202A)(FIG. 2A: 202A; ¶¶0022, 0024, 0036-0037);
the first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037); and
the second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037);
wherein:
in a first mode(content displayed to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A)(¶¶0014, 0036), the first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at a wide angle mode (FIGs. 2A, 4A: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404; ¶¶0022, 0024, 0036) and the second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at the wide angle mode (FIGs. 2A, 4A: a pixel 202A displaying confidential information, e.g., a pixel 202A using 204A in part of 406; ¶¶0022, 0024, 0036); and
in a second mode(content displayed to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B)(¶¶0024, 0037), the first pixel(a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at the wide angle mode (FIGs. 2A, 4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404; ¶¶0022, 0024, 0037) and the second pixel(a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406)(FIGs. 2A, 4A-4B: 202A; ¶¶0022, 0024, 0036-0037) is configured to operate at a narrow angle mode (FIGs. 2A, 4B: a pixel 202A displaying confidential information, e.g., a pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0037).
Cohen does not expressly disclose a first multiplexer circuit connected to the first pixel; and a second multiplexer circuit connected to the second pixel; wherein: in a first mode, the first pixel is configured to operate at a wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at the wide angle mode by controlling the second multiplexer circuit; and
in a second mode, the first pixel is configured to operate at the wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at a narrow angle mode by controlling the second multiplexer circuit.
Shikina discloses a first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) connected to the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072); and a second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) connected to the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072);
the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at a wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) and the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at the wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099); and
the first pixel(a pixel 14 in a first region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at the wide angle mode (FIGs. 3, 6: 26, 311; ¶¶0063, 0074) by controlling the first circuit(a first 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099) and the second pixel(a pixel 14 in a second region of 11)(FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072) is configured to operate at a narrow angle FIGs. 3, 6: 27, 312; ¶¶0064, 0074) mode by controlling the second circuit(a second 60)(FIG. 6; ¶¶0063-0065, 0073-0075, 0099).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen with Shikina to provide a display apparatus that is able to switch pixels between a wide angle mode and a narrow angle mode using commonly used circuit components.
Yokoyama discloses a first multiplexer circuit(28a, 28G directly connected to pixels in a first row of pixels )(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) connected to the first pixel(a first 15m in a first row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106); and a second multiplexer circuit(28a, 28G directly connected to pixels in a second row of pixels)(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) connected to the second pixel(a first 15m in a second row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106);
the first pixel(a first 15m in a first row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106) is configured to operate by controlling the first multiplexer circuit(28a, 28G directly connected to pixels in a first row of pixels )(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}) and the second pixel(a first 15m in a second row of pixels)(FIGs. 13A, 13B, 14A: 28g; ¶¶0093, 0098-0100, 0106) is configured to operate by controlling the second multiplexer circuit(28a, 28G directly connected to pixels in a second row of pixels)(FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen and Shikina with Yokohama to provide a display apparatus that provides first and second mode control signals using simple circuit components.
Cohen, Shikina and Yokohama teach in a first mode, the first pixel is configured to operate at a wide angle mode by controlling the first multiplexer circuit (Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A: a pixel 202A using 204A to display nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: 26, 311, a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and the second pixel is configured to operate at the wide angle mode by controlling the second multiplexer circuit (Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected confidential information, e.g., a pixel 202A using 204A in part of 406 to display confidential information; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 311; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels); and
in a second mode, the first pixel is configured to operate at the wide angle mode by controlling the first multiplexer circuit and the second pixel is configured to operate at a narrow angle mode by controlling the second multiplexer circuit (Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B: a pixel 202A using 204A to display nonconfidential information in a wide angle mode, and a pixel 202A displaying confidential information in a narrow angle mode, e.g., a pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60 controls a pixel 14 in a first region of 11, a second 60 controls a pixel 14 in a second region of 11, 26, 311, 27, 312; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – first and second multiplexer circuits {FIGs. 12a, 13b, 14a: 28a, 28G}, which are directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels and a first 15m in a second row of pixels).
As to claim 2, Cohen, Shikina and Yokohama teach the display apparatus of claim 1, as applied above.
Cohen, Shikina and Yokohama further teach wherein: the first multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the first pixel (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 404 and the pixel 202A displaying confidential information e.g., the pixel 202A using 206A in the part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 5-6: 54, 57-58, P2: ON or OFF of M3, P3: OFF or ON of M4; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}); and the second multiplexer circuit is configured to output a first mode control signal and a second mode control signal to the second pixel (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A using 204A in part of 406, and the pixel 202A displaying confidential information, e.g., the pixel 202A using 206A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 5-6: 54, 57-58, P2: ON or OFF of M3, P3: OFF or ON of M4; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a second row of pixels; ¶¶0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 10, Cohen, Shikina and Yokohama teach the display apparatus of claim 2, as applied above.
Cohen, Shikina and Yokohama teach wherein each of the first multiplexer circuit (Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A: a pixel 202A using 204A to display nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: 26, 311, a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and second multiplexer circuit (Cohen: FIGs. 2A, 4A-4B: displaying to an authorized user when an unauthorized has not been detected confidential information, e.g., a pixel 202A using 204A in part of 406 to display confidential information; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 311; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokohama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels) includes: a first switching element configured to output a gate-on voltage as the second mode control signal based on a control signal (Shikina: FIGs. 5-6: 54, 57-58, M4 ON to provide narrow angle display mode; ¶¶0069, 0073, 0095; Yokoyama: FIG. 14A: PMOS of 28Gb outputs a VDD/ON signal to 26a based on control signal {FIG. 14A: Sig_trim signal} during the second mode when 26a is turned on); a second switching element configured to output a gate-off voltage as the second mode control signal based on an inverted control signal opposite to the control signal (Shikina: FIGs. 5-6: 54, 57-58, M4 OFF during narrow angle display mode; ¶¶0069, 0073, 0096; Yokoyama: FIG. 14A: NMOS of 28G outputs a VSS/OFF signal to 26b based on a signal 2Gal, which is inverted to the control signal {FIG. 14A: Sig_trim signal}); a third switching element configured to output the gate-on voltage as the first mode control signal based on the inverted control signal (Shikina: FIGs. 5-6: 54, 57-58, ON signal to M3 during wide angle viewing mode; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, LS1, LS3, LED_SEL1, LED_SEL2, Vga, PMOS of 28Ga outputs an ON signal via its lower drain/source terminal to 26a, which is due to is an inverted signal of the signal output by 28t; ¶¶0093, 0098-0100, 0106); and a fourth switching element configured to output the gate-off voltage as the first mode control signal based on the control signal (Shikina: FIGs. 5-6: 54, 57-58, OFF signal to M4 during wide angle viewing mode; ¶¶0069, 0073, 0096; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, LS1, LS3, LED_SEL1, LED_SEL2, Vga, NMOS of 28Gbl outputs an VSS/OFF signal to 26b, which based on the signal output by 28t; ¶¶0093, 0098-0100, 0106).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
As to claim 15, Cohen, Shikina and Yokohama teach the display apparatus of claim 2, as applied above.
Cohen, Shikina and Yokohama further teach wherein: the first pixel (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0072) and the second pixel (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a pixel 14 in a second region of 11; ¶¶0031, 0035-0036, 0049-0052, 0072) are disposed in a display area of a display panel (Cohen: FIG. 2A: 201A, 202A; ¶0022; Shikina: FIGs. 1-3: 11, 14; ¶¶0030, 0033, 0047, 0071), and the first multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and the second multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels) are disposed in a bezel area adjacent to the display area (Shikina: FIGs. 1, 5-6, 14: area outside area of 14s; ¶¶0071, 0073; Yokoyama: FIG. 14A: area outside of area including pixel blocks 15m; ¶¶0093, 0106-0107).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokohama with Shikina’s further teachings to provide a display apparatus that displays images that are brighter and with a higher resolution (i.e., by optimizing the display area by placing the control elements outside the display area).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokohama with Yokoyama’s further teachings to provide a display apparatus that displays images that are brighter and with a higher resolution (i.e., by optimizing the display area by placing the multiplexers outside the display area).
14. Claims 3 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) as applied to claims 1-2 above, in view of U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”).
As to claim 3, Cohen, Shikina and Yokohama teach the display apparatus of claim 2, as applied above.
Cohen, Shikina and Yokohama teach wherein each of the first subpixel (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of the first pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 3: one of 31, 32 and 33; FIG. 6: 26 and 27; ¶¶0048-0051, 0093) and the second subpixel (Cohen: FIGs. 2A, 4A-4B: in part 406: a 204A and adjacent 206A of the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 3: one of 31, 32 and 33; FIG. 6: 26 and 27; ¶¶0048-0051, 0093) includes: a driving transistor (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, M2; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073, 0093)
a first light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, one of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073);
a second light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, the other of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073);
a first mode control transistor (Shikina: FIG. 6: M3; ¶0092) configured to connect the driving transistor (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, M2; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073, 0093) and the first light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, one of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073) in response to the first mode control signal (Shikina: FIGs. 5-6: 54, 57-58, P2, ON or OFF of M3; ¶¶0069, 0073, 0096);
a second mode control transistor (Shikina: FIG. 6: M4; ¶0092) configured to connect the driving transistor (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, M2; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073, 0093) and the second light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, one of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073) in response to the second mode control signal (Shikina: FIGs. 5-6: 54, 57-58, P3, OFF or ON of M4; ¶¶0069, 0073, 0095);
the first light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, one of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073); and
the second light-emitting element (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A and adjacent 206A of each of the first pixel 202A and the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 6: a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, the other of: 26 or 27; FIGs. 1, 3, 6; ¶¶0031, 0035-0036, 0049-0052, 0072-0073).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
Cohen, Shikina and Yokohama do not expressly disclose a first lens area disposed on the first light-emitting element, the first lens area including at least one first lens; and
a second lens area disposed on the second light-emitting element, the second lens area including at least one second lens.
Shin discloses a first lens area(area of 442 and/or 443 above 320)(FIG. 4; ¶¶0078, 0081) disposed on the first light-emitting element(320)(FIG. 4; ¶¶0078, 0081), the first lens area(area of 442 above 320)(FIG. 4; ¶¶0078, 0081) including at least one first lens(area of 442 above 320)(FIG. 4; ¶¶0078, 0081); and a second lens area(area of 442 and/or 443 above 310)(FIG. 4; ¶¶0078, 0081) disposed on the second light-emitting element(310)(FIG. 4; ¶¶0078, 0081), the second lens area(area of 442 and/or 443 above 310)(FIG. 4; ¶¶0078, 0081) including at least one second lens(area of 442 and/or 443 above 310)(FIG. 4; ¶¶0078, 0081).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokohama with Shin to provide a display apparatus: (i) having a flat surface; and (ii) that is better able to display content to a viewer not directly in front of the display panel (see e.g., ¶0081, especially - “a relatively wide viewing angle”).
As to claim 7, Cohen, Shikina and Yokohama teach the display apparatus of claim 1, as applied above.
Cohen, Shikina and Yokohama further teach to control a viewing angle in a wide viewing angle, and to control the viewing angle at narrow viewing angle (Cohen: FIGs. 2A, 4A-4B; ¶¶0014, 0022, 0024, 0036-0037 - in the first mode {content displayed to an authorized user when an unauthorized has not been detected, e.g., as shown in FIG. 4A}, the second pixel operates in the wide angle mode {FIGs. 2A, 4A: a pixel 202A displaying confidential information when an unauthorized has not been detected , e.g., a pixel 202A using 204A in part of 406}; and in the second mode {content displayed to an authorized user when an unauthorized has been detected, e.g., as shown in FIG. 4B}, the second pixel 202A operates in the narrow angle mode displaying confidential information, e.g., a pixel 202A using 206A in part of 406; Shikina: FIGs. 1, 3, 6: a second 60, a pixel 14 in a second region of 11, 26, 27, 311, 312; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099).
The motivation to combine the additional teachings of Shikina is for the same reasoning set forth above for claim 1.
Cohen, Shikina and Yokohama do not expressly disclose wherein the at least one first lens is configured to control a viewing angle in a first direction at a wide viewing angle, and the at least one second lens is configured to control the viewing angle in the first direction at narrow viewing angle.
Shin discloses wherein the at least one first lens(area of 442 above 320)(FIG. 4; ¶¶0078, 0081) is configured to control a viewing angle in a first direction(above 430) at a wide viewing angle (FIG. 4: L2; ¶0081), and the at least one second lens is configured to control the viewing angle in the first direction(above 430) at narrow viewing angle (FIG. 4: L1; ¶0081).
The motivation to combine Shin is set forth above for claim 3.
As to claim 8, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above.
Cohen, Shikina, Yokohama and Shin further teach wherein the first subpixel operates the wide angle mode when the first control signal of the first multiplexer circuit is activated (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A ON and adjacent 206A OFF of the pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 26 is activated for wide angle mode by P2/M3 ON while P3/M4 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a ON to turn 14a ON while 28Gbl turns 26b OFF to turn 14b OFF), and the first subpixel operates the narrow angle mode when the second control signal of the first multiplexer circuit is activated (Cohen: FIGs. 2A, 4A-4B: in part 404: a 204A OFF and adjacent 206A ON of the pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 27 is activated for narrow angle mode by P3/M4 ON while P2/M3 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a OFF to turn 14a OFF while 28Gbl turns 26b ON to turn 14b ON).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1, and the motivation to combine the additional teachings of Shin is for the same reasoning set forth above for claim 3.
As to claim 9, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above.
Cohen, Shikina, Yokohama and Shin further teach wherein the second subpixel operates the wide angle mode when the first control signal of the second multiplexer circuit is activated (Cohen: FIGs. 2A, 4A-4B: in part 406: a 204A ON and adjacent 206A OFF of the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, 26 is activated for wide angle mode by P2/M3 ON while P3/M4 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a ON to turn 14a ON while 28Gbl turns 26b OFF to turn 14b OFF), and the second subpixel operates the narrow angle mode when the second control signal of the second multiplexer circuit is activated (Cohen: FIGs. 2A, 4A-4B: in part 406: a 204A OFF and adjacent 206A ON of the second pixel 202A; ¶¶0022, 0024, 0036-0037; Shikina: FIG. 3: one of 31, 32 and 33; FIG. 6: 26 and 27; ¶¶0048-0051, 0093; Shikina: FIGs. 1, 3, 6: a first 60, 27 is activated for narrow angle mode by P3/M4 ON while P2/M3 is OFF, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0072-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}). Thus, 28Gal turns 26a OFF to turn 14a OFF while 28Gbl turns 26b ON to turn 14b ON).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
15. Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”) in view of U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”) in view of U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) as applied to claim 2 above, in view of claim 15 above, in view of U.S. Patent Pub. No. 2020/0286448 A1 to Kim et al. (“Kim”).
As to claim 16, Cohen, Shikina and Yokohama teach the display apparatus of claim 15, as applied above.
Cohen, Shikina and Yokohama further teach wherein each of the first multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and the second multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels) is configured to be supplied with control signals from a gate line controller or an emission line controller (Shikina: FIGs. 1, 5-6: 13, M3, M4, 60, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0068-0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, Sig 1 or Cont signal to 28b; ¶¶0045, 0063, 0074-0076, 0098-0100, 0106); the data driver (Shikina: FIG. 1: 12; ¶0031; Yokoyama: FIGs. 1, 13A, 13B, 14: 12; ¶¶0031, 0069).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokoyama with Shikina’s further teachings to provide a display apparatus that the display of light by pixels at desired times.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokoyama with Yokoyama’s further teachings to provide a display apparatus that the display of light by pixels at desired times.
Cohen, Shikina and Yokohama do not expressly disclose wherein each of the first multiplexer circuit and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller.
Kim discloses the data driver is integrated with gate line controller and the emission line controller (¶0069).
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify Cohen, Shikina and Yokohama with Kim to provide a display apparatus that operates more reliably (i.e., an integrated circuit is less prone to having loose electrical connections) and has a smaller non-display area.
Cohen, Shikina, Yokohama and Kim teach wherein each of the first multiplexer circuit and the second multiplexer circuit is configured to be supplied with control signals from any one of a data driver and a timing controller (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404, a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037).
As to claim 17, Cohen, Shikina, Yokohama and Kim teach the display apparatus of claim 16, as applied above.
Cohen, Shikina, Yokohama and Kim further teach wherein each of the first multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a: 28g; ¶¶0093, 0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28a, 28G directly connected to pixels in a first row of pixels}, which is directly connected to pixels in a first row of pixels including a first 15M, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a first row of pixels) and the second multiplexer circuit (Shikina: FIGs. 5-6: M3, M4, P2, P3, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0069, 0073; Yokoyama: FIGs. 13a, 13b, 14a; ¶¶0093, 0098-0100, 0106 – a second multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a second row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2} for a first 15m in a second row of pixels) is selectively configured to output a gate-on voltage and a gate-off voltage as the first and second mode control signals based on the control signal (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404, a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1-3, 5-6: 14s, 54, 57, 58, M3, M4, P2, P3, 60, a pixel 14 in a first region of 11, a pixel 14 in a second region of 11, each portion of 54 providing signals to a pair of adjacent 57 and 58; ¶¶0031, 0033, 0063, 0068-0069, 0071-0075, 0095-0096, 0099-0100, 0172; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28g, ON or OFF provided to 26a, OFF or ON provided to 26b, 15m, Sig 1 or Cont signal to 28b; ¶¶0074-0076, 0093, 0098-0100, 0106).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1.
Potentially Allowable Subject Matter
16. As to claims 4-6, if the above grounds of rejection based on double patenting and 35 U.S.C. 112(b) are overcome, then these claims would become allowable, i.e., objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claim 11-14 and 18-19, if the above objections to these claims as well as the grounds of rejection based on double patenting and 35 U.S.C. 112(b) is overcome, then they would become allowable if rewritten in independent form.
Reasons for Allowance
17. The following is examiner’s statement of reasons for allowance: the claimed invention is directed to:
Dependent claim 11 identifies the distinct features: “wherein each of the first subpixel(FIGs. 3A, 8: SP11, SP) and the second subpixel(FIGs. 3A, 8: SP21, SP) further includes: a storage capacitor(FIG. 8: C1) connected to a gate electrode(FIG. 8: DT’s gate electrode) of the driving transistor(FIG. 8: DT); a first switching transistor(FIG. 8: T1) configured to supply a data voltage(FIG. 8: Vdata) of a data line(FIG. 8: 22) to a first electrode(FIG. 8: C1’s left electrode) of the storage capacitor(FIG. 8: C1) based on a first scan signal(FIG. 8: SCAN1) of a first gate line(FIG. 8: 12);
a second switching transistor(FIG. 8: T2) configured to connect the driving transistor(FIG. 8: DT) to a diode structure(FIG. 8: DT) based on a second scan signal(FIG. 8: SCAN2) of a second gate line(FIG. 8: 14);
a third switching transistor(FIG. 8: T3) configured to supply an initialization voltage(FIG. 8: Vref) of an initialization voltage line(FIG. 8: 24) to the first electrode(FIG. 8: C1’s left electrode) of the storage capacitor(FIG. 8: C1) based on an emission control signal(FIG. 8: EM) of a third gate line(FIG. 8: 16);
a fourth switching transistor(FIG. 8: T4) configured to connect the driving transistor(FIG. 8: DT) with the first and second mode control transistors(FIG. 8: T6, T8) based on the emission control signal(FIG. 8: EM) of the third gate line(FIG. 8: 16);
a fifth switching transistor(FIG. 8: T5) configured to supply the initialization voltage(FIG. 8: Vref) of the initialization voltage line(FIG. 8: 24) to an anode electrode(FIG. 8: EL2’s top electrode) of the second light-emitting element(FIG. 8: EL2) based on the second scan signal(FIG. 8: SCAN2) of the second gate line(FIG. 8: 14); and
a seventh switching transistor(FIG. 8: T7) configured to supply the initialization voltage(FIG. 8: Vref) of the initialization voltage line(FIG. 8: 24) to an anode electrode(FIG. 8: EL1’s top electrode) of the first light-emitting element(FIG. 8: EL1) based on the second scan signal(FIG. 8: SCAN2) of the second gate line(FIG. 8: 14)”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”), U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”), U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) and U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 11, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above but do not teach the above underlined limitations.
Dependent claim 12 identifies the distinct features: “and the first lens(FIG. 4A: LZ1) has a bottom surface wider than the first light emission area, and controls a viewing angle in a second direction(FIG. 4A: Y axis) perpendicular to the first direction(FIG. 4A: X axis) at a narrow viewing angle”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”), U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”), U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) and U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 12, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above.
Cohen, Shikina, Yokohama and Shin further teach wherein: the first light-emitting element includes a first light emission area, and the first lens area includes a first lens (Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0073-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}; Shin: FIG. 4: area of 442 and/or 443 above 320; ¶¶0078, 0081); and the first lens overlaps the first light emission area (Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0073-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}; Shin: FIG. 4: area of 442 and/or 443 above 320; ¶¶0078, 0081), has a bottom surface wider than the first light emission area, controls a viewing angle in the first direction at a wide viewing angle (Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0073-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}; Shin: FIG. 4: area of 442 and/or 443 above 320; ¶¶0078, 0081).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1, and the motivation to combine the additional teachings of Shin is for the same reasoning set forth above for claim 1.
Cohen, Shikina, Yokohama and Shin do not teach the above underlined limitations.
Dependent claim 13 identifies the distinct features: “wherein: the second light-emitting element(FIG. 3A: EL2) includes a plurality of second light emission areas(FIG. 5: RE2, GE2, BE2), and the second lens area(FIG. 5: RNE, GNE, BNE) includes a plurality of second lenses(FIGs. 4B, 5: LZ2) that overlap the plurality of second light emission areas(FIG. 5: RPA, GPA, BPA), respectively; and each of the plurality of second lenses(FIGs. 4B, 5: LZ2) has a bottom surface wider than each of the plurality of second light emission areas(FIG. 5: RE2, GE2, BE2) and controls a viewing angle in the first direction(X axis direction) and a second direction(Y axis direction) perpendicular to the first direction(X axis direction) at a narrow viewing angle”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”), U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”), U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) and U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 13, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above but do not teach the above underlined limitations.
Dependent claim 14 identifies the distinct features: “and the second lens area(FIG. 5: BNE, GNE, RNE) includes a plurality of the second lenses(FIG. 5: LZ2); a size of the first lens(FIG. 5: LZ1) of at least one of the first(FIG. 5: BPA), second(FIG. 5: GPA) and third(FIG. 5: RPA) colored subpixels is different; and a number of the second lenses(FIG. 5: LZ2) of at least one of the first(FIG. 5: BPA), second(FIG. 5: GPA) and third(FIG. 5: RPA) colored subpixels is different”, with all other limitations as claimed.
The closest prior art, U.S. Patent Pub. No. 2016/0210473 A1 to Cohen et al. (“Cohen”), U.S. Patent Pub. No. 2011/0284881 A1 to Shikina et al. (“Shikina”), U.S. Patent Pub. No. 2022/0139300 A1 to Yokoyama et al. (“Yokoyama”) and U.S. Patent Pub. No. 2021/0265537 A1 to Shin et al. (“Shin”), either singularly or in combination, fails to anticipate or render obvious the above underlined features associated with other features of this claim.
As to claim 14, Cohen, Shikina, Yokohama and Shin teach the display apparatus of claim 3, as applied above.
Cohen, Shikina, Yokohama and Shin teach wherein: each of the first pixel and the second pixel includes a first colored subpixel, a second colored subpixel and a third colored subpixel (Cohen: FIGs. 2A, 4A-4B: 202A: a pixel 202A displaying nonconfidential information, e.g., a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1-3, 6; ¶¶0035-0036, 0046, 0049-0052, 0072-0073; Shin: FIG. 4: area of 442 above 320; ¶¶0078, 0081);
the first lens area includes the first lens(Cohen: FIGs. 2A, 4A-4B: a pixel 202A in part of 404; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a first 60, a pixel 14 in a first region of 11; ¶¶0031, 0035-0036, 0049-0052, 0063-0065, 0073-0075, 0099; Yokoyama: FIGs. 13a, 13b, 14a: 28a, 28G directly connected to pixels in a first row of pixels; ¶¶0098-0100, 0106 – a first multiplexer circuit {FIGs. 12a, 13b, 14a: 28a, 28G}, which is directly connected to pixels in a first row of pixels, multiplexes a VDD/ON signal and a VSS/OFF signal to each of the connection lines {FIGs. 12a, 13b, 14a: LS1, LS3, LED_SEL1, LED_SEL2}; Shin: FIG. 4: area of 442 and/or 443 above 320; ¶¶0078, 0081), and the second lens area includes a second lens (Cohen: FIGs. 2A, 4A-4B: a pixel 202A displaying confidential information, e.g., a pixel 202A in part of 406; ¶¶0022, 0024, 0036-0037; Shikina: FIGs. 1, 3, 6: a pixel 14 in a second region of 11; ¶¶0031, 0035-0036, 0049-0052, 0072; Shin: FIG. 4: area of 442 and/or 443 above 310; ¶¶0078, 0081).
The motivation to combine the additional teachings of Shikina and Yokoyama is for the same reasonings set forth above for claim 1, and the motivation to combine the additional teachings of Shin is for the same reasoning set forth above for claim 1.
Cohen, Shikina, Yokohama and Shin do not teach the above underlined limitations.
Other Relevant Prior Art
18. Other relevant prior art includes:
(i) U.S. Patent Pub. No. 2021/0193763 A1 to Sun et al. discloses a wide angle lens(180/181)(FIG. 9; ¶0084) overlapping a pixel(P)(FIG. 5A; ¶0081) including subpixels(S)(FIG. 5A; ¶0081).
(ii) U.S. Patent Pub. No. 2018/0143354 A1 to Li discloses a wide angle lens(163)(Fig. 4A; ¶0023).
Conclusion
19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIRK W HERMANN whose telephone number is (571) 270-3891. The examiner can normally be reached on Monday-Friday, 9am-5pm, EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIRK W HERMANN/Primary Examiner, Art Unit 2623
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