DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: the claim recites “wherein the generating of the target cache block comprises: storing the data in the data field; setting a bit value corresponding to the location within the data field at which the data is stored; and setting a bit value of the global field,” of which the second recitation of “a bit value” should be renamed to --a second bit value-- to distinguish between the two bit values. Appropriate correction is required.
Claim 13 is objected to for the same reasons as claim 3, as outlined above.
Claim 4 is objected to because of the following informalities: the claim recites “the generating of the target cache” which should be --the generating of the target cache block--. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 9-11 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Krafka et al. (US 2009/0089511 A1) hereinafter O’Krafka et al. in view of Kahle et al. (US 2020/0183842 A1) hereinafter Kahle et al.
Regarding claim 1, O’Krafka et al. teaches an operating method of a compute cluster comprised of a first node and a second node sharing a virtual memory (four nodes 110 sharing a global or distributed memory 160 Paragraph [0028]), the operating method comprising:
generating, by the first node, an instruction to store data of the first node in the virtual memory (direct messages received by a node are converted into local hardware transactions directing load/store memory access Paragraph [0024], for example, a cache miss request 210 is issued at the first node from one of the processors Paragraph [0040]);
determining, by the first node whether a cache block is stored in a cache of the first node (it is determined whether the cache miss request is a store miss request Paragraph [0041]);
based on the determining indicating that a cache block is not stored in the cache of the first node, generating, in the first node, a target cache block comprising the data, wherein the target cache block is stored in the cache of the first node (for a write-back operation, data is written back to the requesting node as a normal write-back transaction Paragraph [0051]); and
updating, by the second node, a cache block stored in a cache of the second node, wherein the cache block in the cache of the second node corresponds to the virtual address, and wherein the updating is based on the target cache block (a remote shared state indicates that the cache block that is the target of the store miss request is shared among other processors, and a modification to the block would render the other cached copies invalid or non-coherent Paragraph [0041], consequently, a second direct message is sent to other nodes in the system possessing the cache directing the invalidation of the cache block on other remote nodes Paragraph [0042]-[0043]).
O’Krafka et al. does not appear to explicitly teach, however, Kahle et al. teaches an instruction to store data of the computing device is at a virtual address in a virtual memory shared by the computing device and a target computing device (the process receives a load/store instruction referencing a virtual address (VA) Paragraph [0134]), as well as determining, according to the virtual address of the instruction, whether a cache block corresponding to the virtual address of the instruction is stored in a cache of the computing device, and based on the determining indicating that the cache block corresponding to the virtual address is not stored in the cache of the first node… generating a target cache block in the cache of the computing device (the process determines as to whether the data Granule is in the cache and if not, the process allocates entry for the data granule in the cache Paragraph [0136]).
The disclosures of O’Krafka et al. and Kahle et al., hereinafter OK, are analogous art to the claimed invention because they are in the same field of endeavor of caching in a multi-node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of OK before them, to modify the teachings of O’Krafka et al. to include the teachings of Kahle et al. since both OK teach caching data in a system with a plurality of nodes. Therefore it is applying a known technique (the store instruction includes a virtual address of Kahle et al.) to a known device (a cluster system processing a cache miss request of O’Krafka et al.) ready for improvement to yield predictable results (the virtual address is sent with the store or write instruction of Kahle et al.), KSR, MPEP 2143.
Regarding claim 6, OK teaches all of the features with respect to claim 1 as outlined above.
O’Krafka et al. further teaches wherein the updating of the cache block in the cache of the second node, based on the target cache block, comprises: updating only the data included in the target cache block (a remote shared state indicates that the cache block that is the target of the store miss request is shared among other processors, and a modification to the block would render the other cached copies invalid or non-coherent Paragraph [0041], consequently, a second direct message is sent to other nodes in the system possessing the cache directing the invalidation of the cache block on other remote nodes Paragraph [0042]-[0043]).
Regarding claim 9, OK teaches all of the features with respect to claim 1 as outlined above.
Kahle et al. teaches a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the method of claim 1 (a computer readable storage medium having instructions thereon for causing a processor to carry out, wherein the computer readable storage medium can be a disk Paragraphs [0206]-[0207]).
Regarding claim 10, O’Krafka et al. teaches an operating method of a computing device, the operating method comprising:
receiving or generating, by the computing device, an instruction to store data of the computing device in a virtual memory shared by the computing device and a target computing device (direct messages received by a node are converted into local hardware transactions directing load/store memory access Paragraph [0024], for example, a cache miss request 210 is issued at the first node from one of the processors Paragraph [0040]);
determining whether a cache block is stored in a cache of the computing device (it is determined whether the cache miss request is a store miss request Paragraph [0041]);
based on the determining indicating that the cache block is not stored in the cache of the first node, generating a target cache block comprising the data and storing the target cache block in the cache of the computing device (for a write-back operation, data is written back to the requesting node as a normal write-back transaction as part of the store miss request Paragraph [0051]); and
updating a cache block stored in a cache of the target computing device based on the target cache block, the cache block in the cache of the target computing device corresponding to the virtual address (a remote shared state indicates that the cache block that is the target of the store miss request is shared among other processors, and a modification to the block would render the other cached copies invalid or non-coherent Paragraph [0041], consequently, a second direct message is sent to other nodes in the system possessing the cache directing the invalidation of the cache block on other remote nodes Paragraph [0042]-[0043]).
O’Krafka et al. does not appear to explicitly teach, however, Kahle et al. teaches an instruction to store data of the computing device is at a virtual address in a virtual memory shared by the computing device and a target computing device (the process receives a load/store instruction referencing a virtual address (VA) Paragraph [0134]), as well as determining, according to the virtual address, whether a cache block corresponding to the virtual address is stored in a cache of the computing device, and based on the determining indicating that the cache block corresponding to the virtual address is not stored in the cache of the first node… storing the target cache block in the cache of the computing device (the process determines as to whether the data Granule is in the cache and if not, the process allocates entry for the data granule in the cache Paragraph [0136]).
The disclosures of O’Krafka et al. and Kahle et al., hereinafter OK, are analogous art to the claimed invention because they are in the same field of endeavor of caching in a multi-node system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of OK before them, to modify the teachings of O’Krafka et al. to include the teachings of Kahle et al. since both OK teach caching data in a system with a plurality of nodes. Therefore it is applying a known technique (the store instruction includes a virtual address of Kahle et al.) to a known device (a cluster system processing a cache miss request of O’Krafka et al.) ready for improvement to yield predictable results (the virtual address is sent with the store or write instruction of Kahle et al.), KSR, MPEP 2143.
Claim 11 is rejected under 35 USC 103 for the same reasons as claim 1, as outlined above.
Claim 16 is rejected under 35 USC 103 for the same reasons as claim 6, as outlined above.
Claim(s) 4-5 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over OK in further view of Ivester et al. (US 2022/0300420 A1) hereinafter Ivester et al.
Regarding claim 4, OK teaches all of the features with respect to claim 1 as outlined above.
OK does not appear to explicitly teach, however, Ivester et al. teaches wherein the generating of the target cache is based on determining that an empty storage space exists in the cache of the first node, and wherein the target cache block is stored in the empty storage space (if the backend-track BE TRK data is not present in the cache slots, then the compute node obtains an empty cache slot and then copies the BE TRK from the drives into the empty cache slot, which is local to the compute node Paragraph [0017]).
OK and Ivester et al., hereinafter OKI, both teach caching, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of OKI before the effective filing date of the invention, to modify the teachings of OK by including wherein the generating of the target cache is based on determining that an empty storage space exists in the cache of the first node, and wherein the target cache block is stored in the empty storage space, as taught by Ivester et al.
One of ordinary skill in the art would have been motivated to include wherein the generating of the target cache is based on determining that an empty storage space exists in the cache of the first node, and wherein the target cache block is stored in the empty storage space to improve the cache hit rate.
Regarding claim 5, OK teaches all of the features with respect to claim 1 as outlined above.
OK does not appear to explicitly teach, however, Ivester et al. teaches wherein the generating of the target cache block comprises: based on determining that an empty storage space does not exist in the cache of the first node, removing one of cache blocks stored in the cache of the first node and storing the generated the target cache block into a space from which the one of the cache blocks has been removed (if the primary queue including the cache slots are full, then recycled cache slots are used Paragraph [0022], wherein allocated, used cache slots are converted into free (unused) cache slots that can be used to service Ios Paragraph [0019]).
OK and Ivester et al., hereinafter OKI, both teach caching, therefore they are analogous arts.
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of OKI before the effective filing date of the invention, to modify the teachings of OK by including removing one of cache blocks stored in the cache of the first node and storing the generated the target cache block into a space from which the one of the cache blocks has been removed, as taught by Artan et al.
One of ordinary skill in the art would have been motivated to include removing one of cache blocks stored in the cache of the first node and storing the generated the target cache block into a space from which the one of the cache blocks has been removed in order to recycle cache slots for new IO workloads.
Claim 14 is rejected under 35 USC 103 for the same reasons as claim 4, as outlined above.
Claim 15 is rejected under 35 USC 103 for the same reasons as claim 5, as outlined above.
Allowable Subject Matter
Claims 2-3, 7-8, 12-13 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, “wherein the target cache block comprises: a data field that stores the data; a global field that indicates whether a location of the cache block exists outside the first node, wherein the updating of the cache block in the cache of the second node is based on the global field; and a vector field that indicates a location within the data field where the data is stored,” is not taught by the prior art. The closest prior art is O’Krafka et al. and Eickemever et al. (US 2006/0149934 A1). O’Krafka et al. teaches that a block can be in a shared state, which indicates that the cache block is the target of a store request that is shared among other processors of different node. Eickemever et al. teaches a modified bit vector for tracking results that have changed, where the modified indication is use to select certain data sources for future instructions, however, does not teach the vector field indicating a location within the data field where the data is stored. Claim 3 depends upon claim 2 and would be allowable for at least the same reasons as claim 2, as discussed above.
Claim 12 recites substantially similar subject matter as claim 2 and would be allowable for the same reasons indicated above. Claim 13 depends upon claim 12 and would be allowable for at least the same reasons as claim 12, as discussed above.
Regarding claim 7, “wherein the updating of the cache block in the cache of second node, based on the target cache block, comprises: based on a vector field indicating a location in which the data is stored within a data field of the target cache block, determining a location to be updated and updating the data to be updated, in a data field of the cache block, to the data,” is not taught by the prior art. The closest prior art is Eickemever et al. which teaches a modified bit vector for tracking results that have changed, where the modified indication is use to select certain data sources for future instructions, however, does not teach the vector field indicating a location within the data field where the data is stored and based on said vector field, determining a location to be updated in the data field.
Claim 17 recites substantially similar subject matter as claim 7 and would be allowable for the same reasons indicated above.
Regarding claim 8, “in response to the first node executing a target application configured to perform a sequential write, storing sequentially generated data in the target cache block sequentially; and updating the cache block in the cache of the second node based on the target cache block, in response to a data field of the target cache block being filled with the sequentially generated data,” is not taught by the prior art. The closest prior art is van Greunen et al. (US 2017/0168956 A1) which teaches that data can be sequentially written to a target cache block, however, is silent with regards to the remaining limitations.
Claim 18 recites substantially similar subject matter as claim 8 and would be allowable for the same reasons indicated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Somani et al. (US 5524212) teaches using a write generate to update a cache which validates an address in the first area on a cache-write miss without reading data from shared memory.
Gara et al. (US 2024/0311315 A1) teaches a plurality of nodes utilizing a shared global memory and performing global synchronization.
Werner et al. (US 2025/0307147 A1) teaches different modes of operation specifying different caching policies across the workload.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANE W BENNER whose telephone number is (571)270-0067. The examiner can normally be reached Mon - Thurs (8 AM - 5 PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, REGINALD BRAGDON can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139
Prosecution Insights