Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Status of the Claims
This action is responsive to the amendment and remarks filed 15 July 2026.
Claims 1-20 are pending.
Claims 15-20 stand withdrawn from consideration pursuant to 37 CFR 1.142(b) as directed to a non-elected invention (election without traverse, 16 March 2026).
Claims 1-14 are examined herein.
Claims 1-7, 13, and 14 are amended; claims 8-12 are original.
Paragraph 19 of the Office action of 22 April 2026 recited the withdrawn claims as “1-14”; the correct range is 15-20, and the record is clarified accordingly.
Applicant’s amendment necessitated the new grounds of rejection presented herein: independent claim 1 was amended to require, inter alia, the optical-area/normal-area architecture with transmission areas, the present/absent capacitor recitations, and the re-dependency of claims 3-7, 13, and 14 directly from claim 1. Accordingly, THIS ACTION IS MADE FINAL. MPEP § 706.07(a).
Response to Arguments
Applicant’s arguments (Remarks, 15 July 2026) directed to the rejection of former claims 1-14 over So et al. (KR 10-2018-0025488 A, machine translation of record, “Lim” in the prior action) have been fully considered.
To the extent the arguments contend that Lim, as previously applied, does not disclose the newly added optical-area architecture (a first optical area with transmission areas, surrounded by a normal area having none) or a subpixel-to-subpixel difference in compensation-capacitor complement, the arguments are persuasive as to the amended claims, and the rejections over Lim as primary reference are withdrawn in favor of the grounds below.
The arguments are otherwise moot in view of the new grounds. Applicant’s further contention that the capacitances Cl-C3 of Lim are “merely parasitic” and therefore not “capacitors” within the meaning of the claims is not conceded:
Lim’s translation of record expressly denominates these elements capacitances and draws each as a capacitor at the second node [Paragraph 056: the first parasitic capacitance C1 represents a capacitance], and
the instant specification itself treats deliberately configured and parasitic couplings at the same node as interchangeable in function (compare instant Paragraphs 306-308 with 358). The claims recite “capacitor” without restriction to intentionally patterned structures, and no lexicographic definition narrows the term.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 is rejected under 35 U.S.C. 112(b) as indefinite.
The final wherein clause recites that at least one second subpixel “does not comprise at least one of the first compensation capacitor or the second compensation capacitor.”
The scope of the negation is unclear: the clause is reasonably read either as
(i) the second subpixel comprises neither capacitor, or
(ii) there is at least one of the two capacitors that the second subpixel does not comprise - a materially broader scope satisfied by a subpixel having one capacitor but not the other.
The specification does not resolve the ambiguity; it uses a still different formulation for the normal-area subpixel [Paragraph 368: does not include both the first compensation capacitor C1 and the second compensation capacitor C2].
Because the metes and bounds of the exclusion cannot be ascertained with reasonable certainty, claim 1 is indefinite.
Claims 2-14 are rejected under 35 U.S.C. 112(b) for their dependence from claim 1, each failing to cure the ambiguity of the negation therein.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
The analysis compares the examined claims with the claims of the reference patent; the reference patent’s disclosure is not available as prior art in this analysis and is consulted, if at all, only to construe the meaning of the reference claims. In re Vogel, 422 F.2d at 441-42. The one-way test for distinctness applies. It is noted that 35 U.S.C. 121 provides no shield here: the instant application is a continuation of the application that issued as the reference patent, not a divisional filed as a result of a restriction requirement, so the § 121 prohibition does not apply. A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321(d) may be used to overcome this rejection; the reference patent and the instant application name the same applicant (LG Display Co., Ltd.), so common ownership under 1.321(c) is available.
Claims 1-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-13 and 18-22 of U.S. Patent No. 12,400,592 B2 in view of
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Cha (US 2021/0359073 A1).
Although the claims at issue are not identical, they are not patentably distinct, as follows. Claim-number citations below are to the ‘592
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patent’s claims.
Instant claim 1 is unpatentable over ‘592 claims 1-3 with 6, 9, and 12.
‘592 claim 1 recites the identical four-node pixel circuit (the driving transistor controlled at the second node; the first transistor on the first scan line controlling the second-node/ third-node connection; the second and third transistors on the light emitting control line),
an optical area whose subpixels have light emitting areas together with [‘592 claim 1: a plurality of transmission areas allowing light reaching a surface of the display device to be transmitted], and
a first subpixel whose second node is [‘592 claim 1: capacitively coupled with at least one of the first scan line and the light emitting control line].
‘592 claim 2 adds [‘592 claim 2: a normal area that is different from the optical area and is located outside of the optical area], and
‘592 claim 3 adds a second subpixel in the normal area for which [‘592 claim 3: the second node in the second subpixel does not have capacitive coupling with the first scan line and the light emitting control line] - which satisfies the instant negative limitation under every reading advanced in paragraph 8, a fortiori (a subpixel with no coupling to either line necessarily does not comprise at least one of the recited capacitors).
The recited capacitors themselves are claimed in haec verba: [‘592 claim 6: a first compensation capacitor between the second node and the first scan line]; [‘592 claim 9: a second compensation capacitor between the second node and the light emitting control line]; and both together in claim 12.
The instant claim differs in two respects, neither of which is a patentable distinction.
First, it recites the normal area surrounding the first optical area, where ‘592 claim 2 places the normal area outside of the optical area;
complete encirclement of an interior component area by the main display area is one of a finite number of predictable placements and is, in any event, expressly taught by Cha [Paragraph 53: the main display area MDA at least partially surrounding the component area; Paragraph 81: surrounded by the main display area MDA].
It would have been obvious to arrange the ‘592 claimed normal area to surround the optical area as Cha teaches, to place the component region within the active display.
Second, the instant claim is broader than ‘592 claim 1 in omitting that claim’s locational limitation ([‘592 claim 1: between at least two adjacent transmission areas]) and in hedging the coupling as “at least one of” the two capacitors; a later claim that is broader than, and encompasses, the earlier patented claim is not patentably distinct from it. In re Van Ornum, 686 F.2d 937; In re Berg, 140 F.3d 1428.
Instant claim 2 is unpatentable over ‘592 claims 1, 3, and 5.
The recited “luminance difference compensation structure including the at least one of the first compensation capacitor or the second compensation capacitor” is the claimed coupling itself under another name:
‘592 claim 1 provides it in the first subpixel,
claim 3 excludes it from the second subpixel, and
claim 5 recites its luminance-equalizing function ([‘592 claim 5: a difference between luminance of the optical area and luminance of the normal area is smaller than] the per-subpixel difference).
Relabeling the patented structure by its function is not a patentable distinction.
Instant claim 3 is anticipated by ‘592 claim 4:
the two claims are identical after the dependency recitation (differing only in “the at least one first/second subpixel” versus “the first/second subpixel”), including
the same-data-voltage condition and the recitation that [‘592 claim 4: a voltage difference between gate and source voltages of the driving transistor during a light emitting period of the first subpixel is greater than] that of the second subpixel.
‘592 claim 22 is cumulative.
Instant claim 4 is unpatentable over ‘592 claims 1 and 2 in view of Cha.
‘592 claim 1 places the first subpixel - hence at least one of its light emitting areas - [‘592 claim 1: between at least two adjacent transmission areas];
adjacency of the two transmission areas leaves no other transmission area between them.
The instant recitation that the transmitted light reaches an optical electronic device at the back side states the self-evident purpose of ‘592’s transmission areas and is, in any event, taught by Cha [Paragraph 56: a component 40, which is an electronic element, may be arranged below a display panel 10 to correspond to the component area CA].
Instant claim 5 is anticipated by ‘592 claim 1:
the patented claim places the first subpixel between at least two adjacent transmission areas - a species of the instant claim’s broader “between at least two transmission areas.”
The narrower patented claim falls wholly within, and thus renders unpatentable, the broader instant claim.
Instant claims 6 and 7 are unpatentable over ‘592 claims 1-3 in view of Cha. No ‘592 claim recites the cathode opening or the light shield layer;
Cha supplies both for the same transmission-area architecture the ‘592 claims recite - the opposite electrode (cathode) with [Paragraph 156: a transmission hole TAH corresponding to the transmission area TA], and
the bottom metal layer arranged below the pixel circuit to block light, with [Paragraph 117: there is no bottom metal layer BML in the transmission area TA].
It would have been obvious to provide the ‘592-claimed device with Cha’s cathode opening and bottom metal layer to raise transmission-area transmittance and to shield the circuit, exactly as Cha teaches for the same architecture.
Instant claim 8 is anticipated by ‘592 claim 7 (identical after the dependency recitation):
[‘592 claim 7: at the first timing, the voltage at the second node is changed according to a change in voltage of the first scan signal].
‘592 claim 13 is cumulative.
Instant claim 9 is anticipated by ‘592 claim 8 (identical after the dependency recitation):
[‘592 claim 8: the connection pattern intersects an active layer of the driving transistor and overlaps the first compensation protrusion].
Instant claim 10 is anticipated by ‘592 claim 10 (identical after the dependency recitation):
[‘592 claim 10: at the second timing, the voltage at the second node is changed according to a change in voltage of the light emitting control signal].
‘592 claim 13 is cumulative.
Instant claim 11 is anticipated by ‘592 claim 11 (identical after the dependency recitation),
which recites the connection pattern, the second compensation protrusion of the light emitting control line, the intersection with the driving transistor’s active layer, and that the connection pattern [‘592 claim 11: overlaps the second compensation protrusion].
Instant claim 12 is anticipated by ‘592 claim 18 (identical after the dependency recitation),
including the fourth, fifth, and sixth transistors and [‘592 claim 18: a storage capacitor disposed between the second node and the driving voltage line].
Instant claim 13 is not patentably distinct from ‘592 claim 19.
Both recite the same three-area configuration - a first optical area, a second optical area each comprising light emitting areas and transmission areas, and a distinct normal area - and the two density limitations are identical, including that [‘592 claim 19: a number of subpixels per unit area in the second optical area is greater than the number of subpixels per unit area in the first optical area, and is smaller than the number of subpixels per unit area in the normal area].
The instant claim’s introduction of the areas in a different order and its “further comprises” phrasing do not change the claimed subject matter.
See also ‘592 claims 20 and 21, which further claim the same two-optical-area architecture with per-area compensation capacitors [‘592 claim 20: the third subpixel comprises a third compensation capacitor between the second node and the first scan line of the third subpixel and a fourth compensation capacitor between the second node and the light emitting control line of the third subpixel] and
a first-area-greater capacitance relationship [‘592 claim 21: a capacitance of the first compensation capacitor is greater than a capacitance of the third compensation capacitor], cumulatively confirming that graded optical areas were among the patented subject matter.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12,400,592 B2 in view of Cha further in view of Kim H. (US 2021/0193781 A1).
No ‘592 claim recites the four-transmission-area surround.
Kim H. supplies it for the same alternating pixel-group/transmission-area architecture [Paragraph 237: The pixel groups Pg and the transmission areas TA may be alternately arranged or disposed; Fig. 14A: each interior pixel group - a block of adjacent emitting areas - is bounded by transmission areas on its left, right, upper, and lower sides].
It would have been obvious to arrange the ‘592-claimed optical area in Kim H.’s checkerboard, whereby at least two adjacent first light emitting areas are surrounded by four transmission areas, to obtain Kim H.’s taught balance of resolution and transmittance.
The rationale and motivation of paragraph 12 as to the base combination apply.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8, 10, and 14 are rejected under 35 U.S.C. § 102(a)(1) as anticipated by Kim S. (US 2021/0287610 A1, published 2021-09-16).
All citations are to the single embodiment of FIGS. 8-23 (Paragraphs 111-206).
Claim 1
Regarding claim 1, Kim S. discloses a display device, comprising:
a display panel comprising a plurality of subpixels, wherein the plurality of subpixels are disposed in a display area for displaying an image, the display area comprising a first optical area and a normal area surrounding the first optical area [Paragraph 88: the second display area A2 may be located inside the display area DA and may be surrounded by the first display area A1],
wherein each of the plurality of subpixels comprises: a first node, a second node, a third node, and a fourth node [Figs. 9 and 15: the first-electrode node of T1, the gate node N1, the second-electrode node of T1, and the anode node of the OLED];
a driving transistor configured to be controlled by a voltage at the second node and configured to drive a light emitting element [Paragraph 123: A gate electrode of the first transistor Tl may be connected to a first node N1];
a first transistor configured to be controlled by a first scan signal supplied through a first scan line and configured to control a connection between the second node and the third node [Paragraph 125: The third transistor T3 (a diode connection transistor) may be connected between the second electrode of the first transistor Tl and the first node N1]; [Paragraph 125: a gate electrode of the third transistor T3 may be connected to the second scan line Gi2];
a second transistor configured to be controlled by a light emitting control signal supplied through a light emitting control line and configured to control a connection between the first node and a driving voltage line [Paragraph 127: The fifth transistor T5 (a first emission transistor) may be connected between the first transistor Tl and a power line PL to which the first power ELVDD is applied]; and
a third transistor configured to be controlled by the light emitting control signal and configured to control a connection between the third node and the fourth node [Paragraph 128: The sixth transistor T6 (a second emission transistor) may be connected between the first transistor Tl and the light emitting element OLED]; [Paragraph 128: a gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei],
wherein the plurality of subpixels comprises a first plurality of subpixels disposed in the first optical area and a second plurality of subpixels disposed in the normal area [Paragraph 93: a pixel arranged in the first display area A1 is defined as the first pixel PXL1, and a pixel arranged in the second display area A2 is defined as the second pixel PXL2],
wherein the first optical area comprises a first plurality of light emitting areas disposed in the first plurality of subpixels, and a plurality of transmission areas configured to transmit light incident on a surface of the display panel through the display panel [Paragraph 92: The second display area A2 may transmit a signal (for example, ray or light) input to the sensor SR]; [Paragraph 94: A gap of the second pixels PXL2 formed at a low density may better transmit the signal (for example, ray or light) by forming a physical and/or optical aperture, for example, a transmission window],
wherein the normal area comprises a second plurality of light emitting areas disposed in the second plurality of subpixels, the normal area not comprising a transmission area [Paragraph 120: the total area of the first display area A1 and the area at which the first pixels PXL1 are arranged are the same];
the first pixels occupy the entirety of the first display area, leaving no transmission area therein, wherein at least one first subpixel among the first plurality of subpixels disposed in the first optical area comprises at least one of a first compensation capacitor disposed between the second node and the first scan line or a second compensation capacitor disposed between the second node and the light emitting control line [Paragraph 131: The first boosting capacitor Cb1 may be connected between the first node N1 and the second scan line Gi2]; [Paragraph 155: The second boosting capacitor Cb2 may be connected between the first node N1 and the emission control line Ep]; [Paragraph 154: a first boosting capacitor Cb1, and a second boosting capacitor Cb2; the optical-area subpixel comprises BOTH recited capacitors], and
wherein at least one second subpixel among the second plurality of subpixels disposed in the normal area does not comprise at least one of the first compensation capacitor or the second compensation capacitor [Paragraph 17: the plurality of first pixels may not include the one boosting capacitor]; [Paragraph 185: the first sub pixel SPI of the first pixel PXL1 may not include the second overlapping area OA2]; [Paragraph 186: each of the sub pixels SPI and SP2 of the second pixel PXL2 may include the first boosting capacitor Cb1 and the second boosting capacitor Cb2, and each of the sub pixels of the first pixel PXL1 may include the first boosting capacitor Cb1] (for example: see Paragraphs 83-206).
The anticipation holds under each construction stated in paragraph 8.
Under the broadest reasonable reading, the normal-area subpixel does not comprise the second compensation capacitor:
Kim S. states the absence expressly (Paragraphs 17, 185-186).
Kim S. further discloses that a residual fringe coupling between the first-node electrode and the emission control line remains in the first pixel notwithstanding the absent overlap [Paragraph 187: a coupling phenomenon due to a fringe phenomenon may occur between the electrode electrically connected to the first node N1 and the emission control line Ep]; [Paragraph 188: a capacitance of the first boosting capacitor Cb1 may be greater than a capacitance between the electrode electrically connected to the first node N1 and the emission control line Ep in the first pixel PXL1];
to the extent that residue is urged to be “the second compensation capacitor,” it is of different (far smaller) capacitance and lacks the recited overlap structure, so the normal-area subpixel does not comprise the second compensation capacitor under the antecedent-based construction either.
Kim S.’s own distinction between the deliberate overlap capacitor and residual fringe coupling (Paragraphs 179, 185-188) accords with the interpretation applied throughout this action.
Claim 2
Regarding claim 2, Kim S. discloses the display device of claim 1, as set forth above, wherein the at least one first subpixel disposed in the first optical area comprises a luminance difference compensation structure including the at least one of the first compensation capacitor or the second compensation capacitor, and wherein the at least one second subpixel disposed in the normal area does not have such a structure [Paragraph 142: the second pixels PXL2 may be set to emit light at a luminance greater than that of the first pixels PXL1, so that a boundary between the first display area A1 and the second display area A2 is not easily recognized]; (for example: see Paragraphs 199-206);
the Cb1 /Cb2 complement is the disclosed mechanism by which the optical-area subpixels attain the greater luminance at the same data voltage, and the normal-area subpixels lack the Cb2 member of it (for example: see Paragraphs 17, 185-186).
Claim 3
Regarding claim 3, Kim S. discloses the display device of claim 1, as set forth above, wherein: the display device is configured to apply, to the at least one first subpixel, a first
data voltage through a first data line, and to the at least one second subpixel, a second data voltage through a second data line [Paragraph 108: Each of the second pixels PXL2 may be connected to corresponding data line Dq]; (for example: see Paragraph 103); and
when the first data voltage is substantially equal to the second data voltage, a voltage difference between gate and source voltages of the driving transistor during a light emitting period of the at least one first subpixel is greater than a voltage difference between gate and source voltages of the driving transistor during a light emitting period of the at least one second subpixel [Paragraph 206: even though the data signals of the same voltage level are provided to the first pixel PXL1 and the second pixel PXL2, a current difference provided to each light emitting element OLED of the first pixel PXL1 and the second pixel PXL2 is generated]; [Paragraph 204: may maintain a relatively high voltage; Paragraph 205: may maintain a relatively low voltage; the normal-area and optical-area gates respectively; with P-type driving transistors] (Paragraph 132), the lower gate voltage of the optical-area subpixel is the greater gate-source magnitude, in the claimed direction.
Claim 4
Regarding claim 4, Kim S. discloses the display device of claim 1, as set forth above,
wherein the plurality of transmission areas are configured to allow the light incident on a front side of the display panel to be transmitted to a back side of the display panel to enable the light to be transmitted to an optical electronic device [Paragraph 92: The second display area A2 may transmit a signal (for example, ray or light) input to the sensor SR]; [Paragraph 90: The sensor SR may include, for example, a fingerprint sensor, an image sensor, a camera],
wherein at least one of the first plurality of light emitting areas is disposed between at least two transmission areas among the plurality of transmission areas, and wherein no other transmission area is present between the at least two transmission areas [Fig. 10: each interior emission-area block sits directly between the transmission-area cells on its left and right, with no transmission area between them; Paragraph 94].
Claim 5
Regarding claim 5, Kim S. discloses the display device of claim 1, as set forth above, wherein the at least one first subpixel is disposed between at least two transmission areas among the plurality of transmission areas [Fig. 10: the subpixels of each interior emission-area block lie between the flanking transmission-area cells; Paragraph 94].
Claim 8
Regarding claim 8, Kim S. discloses the display device of claim 1, as set forth above, wherein at a first timing, the first scan signal is changed from a first turn-on level voltage to a first turn-off level voltage [Paragraph 198: corresponds to a period before light emission of the light emitting element OLED starts after the data signal writing is ended; i.e., the delay period TP3, the Gi2-gated transistors being turned off at its start], and
at a second timing later than the first timing, the light emitting control signal is changed from a second turn-off level voltage to a second turn-on level voltage [Paragraph 201: The emission period TP4 corresponds to a period in which the fifth transistor T5 and the sixth transistor T6 are turned on]; [the emission control signal transitions to its turn-on level at the start of TP4, a full delay period after the scan transition; Fig. 23], and
wherein at the first timing, the voltage at the second node is changed according to a change in voltage of the first scan signal [Paragraph 199: the voltage level VTIG_PXL1 of the gate electrode of the first transistor Tl may increase by a first level V1 by an influence of the first boosting capacitor Cb1].
Claim 10
Regarding claim 10, Kim S. discloses the display device of claim 1, as set forth above, with the first and second timings as set forth for claim 8, wherein at the second timing, the voltage at the second node is changed according to a change in voltage of the light emitting control signal [Paragraph 203: may decrease by a fourth level V4 greater than the third level V3 by an influence of the first boosting capacitor Cb1 and the second boosting capacitor Cb2; the optical-area gate voltage, at the emission period].
Claim 14
Regarding claim 14, Kim S. discloses the display device of claim 1, as set forth above, wherein at least two adjacent first light emitting areas among the first plurality of light emitting areas of the first plurality of subpixels are surrounded by four transmission areas among the plurality of transmission areas in the first optical area [Fig. 10: each interior emission-area block - containing the adjacent emitting areas of subpixels SP1-SP4 (Paragraph 150) - is bounded by transmission-area cells on its left, right, upper, and lower sides].
Claim Rejections - 35 USC § 103 - Ground I
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6, 7, 9, and 12 are rejected under 35 U.S.C. § 103 as being unpatentable over Cha (US 2021/0359073 A1) in view of Nguyen (US 2017/0077199 A1) further in view of Seo (US 2022/0310736 A1).
Claim 1
Regarding claim 1, Cha discloses a display device, comprising:
a display panel comprising a plurality of subpixels, wherein the plurality of subpixels are disposed in a display area for displaying an image, the display area comprising a first optical area and a normal area surrounding the first optical area [Paragraph 53: The display area DA includes a component area CA and a main display area MDA, the main display area MDA at least partially surrounding the component area; Paragraph 81: arranged inside the display area DA and surrounded by the main display area MDA],
wherein each of the plurality of subpixels comprises: a first node, a second node, a third node, and a fourth node; a driving transistor configured to be controlled by a voltage at the second node and configured to drive a light emitting element [Paragraph 165: A gate electrode of the first transistor Tl is connected to the second node N2; Fig. 7: Tl between N1 and N3, OLED at the output node];
a first transistor configured to be controlled by a first scan signal supplied through a first scan line and configured to control a connection between the second node and the third node [Paragraph 167: The third transistor T3 (a compensation transistor); Fig. 7: T3 connected between N2 and N3, gated by SL2];
a second transistor configured to be controlled by a light emitting control signal supplied through a light emitting control line and configured to control a connection between the first node and a driving voltage line, and
a third transistor configured to be controlled by the light emitting control signal and configured to control a connection between the third node and the fourth node [Paragraph 169: The fifth transistor T5 (a first emission control transistor) is connected to the driving voltage line PL and the first node N1. The sixth transistor T6 (a second emission control transistor) is connected to the third node N3 and the organic light-emitting diode OLED; Fig. 7: T5, T6 gated by EL],
wherein the plurality of subpixels comprises a first plurality of subpixels disposed in the first optical area and a second plurality of subpixels disposed in the normal area [Paragraph 81: The plurality of auxiliary sub-pixels Pa are arranged in the component area CA; Paragraph 94: a plurality of main sub-pixels Pm may be arranged in the main display area MDA],
wherein the first optical area comprises a first plurality of light emitting areas disposed in the first plurality of subpixels, and a plurality of transmission areas configured to transmit light incident on a surface of the display panel through the display panel [Paragraph 9: auxiliary display elements and a transmission area being arranged in the component area; Paragraph 147: A light transmittance of the transmission area TA may be improved by the first to third holes HI, H2, and H3],
wherein the normal area comprises a second plurality of light emitting areas disposed in the second plurality of subpixels, the normal area not comprising a transmission area [Paragraph 9: main display elements being arranged in the main display area; the transmission area is recited as arranged in the component area only, and none is disclosed in the MDA], and
wherein at least one first subpixel among the first plurality of subpixels disposed in the first optical area comprises at least one of a first compensation capacitor disposed between the second node and the first scan line or a second compensation capacitor disposed between the second node and the light emitting control line [Paragraph 172: The third electrode CE3 is connected to the first scan line SLI and the gate electrode of the second transistor T2. The fourth electrode CE4 is connected to the gate electrode of the first transistor T1; Cbt is a capacitor between the driving-gate node N2 and a scan line, i.e., at least the recited first compensation capacitor under the alternative recitation], and
wherein at least one second subpixel among the second plurality of subpixels disposed in the normal area does not comprise at least one of the first compensation capacitor or the second compensation capacitor [Paragraph 162: a first capacitor Cst and a second capacitor Cbt; Cha’s pixel circuit contains no capacitor coupled between the gate node and the emission control line; every subpixel, including each main sub-pixel of the MDA, therefore does not comprise the recited second compensation capacitor] (for example: see Paragraphs 53-94, 160-202).
Claim construction, stated for the record. The final wherein clause is applied under its broadest reasonable interpretation: “does not comprise at least one of [A] or [B]” is satisfied where there is at least one of A and B that the subpixel lacks.
On that reading Cha’s uniform circuit meets both capacitor clauses: each component-area subpixel comprises the first compensation capacitor (Cbt), and each main-display-area subpixel lacks the second compensation capacitor (no gate-to-emission-line capacitor exists in Cha). In the alternative, “the first compensation capacitor” in the negative clause takes its antecedent from the first subpixel’s recited capacitor, such that a normal-area subpixel does not comprise that capacitor where its own capacitor differs in capacitance (or, further in the alternative, is a separate physical instance - the only construction under which incidental parasitic couplings, present at every node of every real display, cannot trivially satisfy both clauses). Under the narrowest reading - the second subpixel comprises neither capacitor while the first comprises at least one - the structural differential is supplied by Seo as set out below.
Cha does not expressly place the compensation capacitor on the same scan line that gates its N2-N3 compensation transistor (Cha’s Cbt sits on SLI while T3 is gated by SL2), and Cha does not disclose an area-to-area difference in capacitor complement.
Nguyen teaches the first compensation capacitor on the line the claim requires:
the boosting capacitor Cb is connected between the scan line and the driving gate [Paragraph 96: The scan line 151 connected with the gate electrode G2 of the switching thin film transistor T2 is connected with the other end Cb2 of the boosting capacitor Cb, and one end Cb1 of the boosting capacitor Cb is connected with the gate electrode G1 of the driving thin film transistor T1], and
that same scan line 151 gates the diode-connecting compensation transistor [Paragraph 92: A gate electrode G3 of the compensation transistor T3 is connected with the scan line 151; Paragraph 138: the scan line 151 including the switching gate electrode 155b and the compensation gate electrode 155c].
Seo teaches pixel circuits of differing capacitor complements deployed by display area:
a first pixel circuit with three capacitors [Paragraph 119: first to third storage capacitors Cst1, Cst2, and Cbt] and
a second pixel circuit with two [Paragraph 217: a fourth storage capacitor Cst4, and a fifth storage capacitor Cbt’],
in a display whose second area contains the transmission areas [Paragraph 67: the second area DA2 may include a transmission area TA arranged between adjacent second pixels P2] and
whose second-area light emitting diode is driven by the enhanced first circuit [Paragraph 118: a second organic light-emitting diode OLED2 disposed in the second area DA2].
Nguyen and Seo are analogous art to the claimed invention and to Cha, being from the same field of endeavor - OLED pixel circuits with gate-node compensation capacitors, and displays having a light-transmitting component region, respectively.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to configure Cha’s boost capacitor on the scan line gating the N2-N3 compensation transistor as taught by Nguyen - a known, interchangeable line assignment for the same kickback-management function - and to differentiate the capacitor complement between Cha’s component-area and main-area circuits as taught by Seo, in order to compensate the luminance of the sparser optical-area subpixels;
Seo teaches that increasing the total gate-node storage capacitance increases the driving current [Paragraph 132: the amount of driving current IOLED flowing through the organic light-emitting diode OLED may increase], and
the instant specification confirms the same ordinary motivation for the capacitor [Paragraph 405: in order to increase the capacitance of the second compensation capacitor C2].
The combination is the use of known elements according to their established functions with predictable results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere co., 383 U.S. 1 (1966).
Claim 2
Regarding claim 2, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above,
wherein the at least one first subpixel disposed in the first optical area comprises a luminance difference compensation structure including the at least one of the first compensation capacitor or the second compensation capacitor, and wherein the at least one second subpixel disposed in the normal area does not have a luminance difference compensation structure including the at least one of the first compensation capacitor or the second compensation capacitor [Seo Paragraph 119 versus Paragraph 217: the first pixel circuit’s Cst1+Cst2+Cbt complement versus the second circuit’s Cst4+Cbt’ complement; Seo Paragraph 132: a capacitance (a total capacitance) of the storage capacitor Cst may be increased - the enhanced complement is the luminance-compensating structure, and the other circuit does not have it].
The mapping of paragraph 14 applies: under the broadest reasonable interpretation the clause is met by the presence of the first compensation capacitor in the optical-area subpixel (Cha Paragraph 172; Nguyen Paragraph 96) and the absence of any second compensation capacitor in the normal-area subpixel (Cha Paragraph 162).
Claim 3
Regarding claim 3, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, and Cha further discloses:
the display device is configured to apply, to the at least one first subpixel, a first data voltage through a first data line; the display device is configured to apply, to the at least one second subpixel, a second data voltage through a second data line [Paragraph 166: The second transistor T2 (a switching transistor) is connected to the data line DL and the first node N1; each sub-pixel, auxiliary and main, receives its data voltage over its data line]; and
when the first data voltage is substantially equal to the second data voltage, a voltage difference between gate and source voltages of the driving transistor during a light emitting period of the at least one first subpixel is greater than a voltage difference between gate and source voltages of the driving transistor during a light emitting period of the at least one second subpixel [Seo Paragraph 132: as a capacitance value (a total capacitance value) of the storage capacitor Cst increases, the amount of driving current IOLED flowing through the organic light-emitting diode OLED may increase; Paragraph 118: a second organic light-emitting diode OLED2 disposed in the second area DA2; the DA2-side OLED is driven by the first pixel circuit having the increased total capacitance].
The recited voltage relationship is the inherent operational consequence of the combined structure and is additionally a matter of capability.
Where the prior-art device possesses the identical differential capacitor structure, the recited gate-source voltage relationship under equal data voltages necessarily follows; the burden shifts to applicant to show otherwise. MPEP § 2112.
Claim 1 is an apparatus claim; claim 3 recites how the apparatus behaves under a stated input condition, and the combined device is fully capable of the recited operation. MPEP § 2114.
It is further noted that claim 3 recites “a light emitting period of the at least one first subpixel” and, separately, “a light emitting period of the at least one second subpixel”; no simultaneity of the two periods is required, and the comparison is met by the device’s operation at any respective times.
The driving-current consequence taught at Seo Paragraph 132 is independent of transistor polarity, and Seo’s circuit is of the same hybrid semiconductor architecture as the instant device [Seo Paragraph 140: may include a semiconductor layer including an oxide, and the rest may include a semiconductor layer including silicon].
Claim 6
Regarding claim 6, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, and Cha further discloses:
wherein the at least one first subpixel disposed in the first optical area includes at least one cathode [Paragraph 152: The opposite electrode 123 is arranged on the second functional layer 122c; Paragraph 153: The layers from the first pixel electrode 121’ to the opposite electrode 123 formed in the component area CA may constitute the auxiliary organic light-emitting diode; the opposite electrode is the low-work-function common electrode, i.e., the cathode], and
wherein the at least one cathode is disposed in at least one of the first plurality of light emitting areas of the first optical area, and is not disposed in the plurality of transmission areas of the first optical area [Paragraph 156: the opposite electrode 123, and the top layer 150 may each include a transmission hole TAH corresponding to the transmission area TA; Paragraph 156: may include an opening corresponding to the transmission area TA].
Claim 7
Regarding claim 7, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, and Cha further discloses:
a light shield layer disposed on a substrate on which the at least one first subpixel is
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disposed, wherein the light shield layer is disposed in at least one of the first plurality of light emitting areas of the first optical area, and is not disposed in the plurality of transmission areas of the first optical area [Paragraph 117: The bottom
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metal layer BML may be arranged below the auxiliary pixel circuit PC’ to prevent or reduce the characteristic of the auxiliary thin film transistor TFT’ being deteriorated by light emitted from a component; Paragraph 117: there is no bottom metal layer BML in the transmission area TA].
Claim 9
Regarding claim 9, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, and Nguyen further discloses:
wherein the at least one first subpixel comprises a connection pattern corresponding to the second node [Paragraph 124: is connected with the driving gate electrode 155a through the first boosting electrode 133 and the driving connecting member 174; the 133/174 chain reaches the driving-gate node], and
the first scan line comprises a first compensation protrusion [Paragraph 126: a second boosting electrode 157 is a projection extended upward from the scan line 151], and
wherein the connection pattern intersects an active layer of the driving transistor [Paragraph 136: On the buffer layer 120, the semiconductor 130 is formed, which includes the driving channel 131a, the switching channel 131b, the compensation channel 131c, the initialization channel 131d, the operation control channel 131e, the light emission control channel 131f, the first storage electrode 132, and the first boosting electrode 133; Fig. 2: the connecting member 174 and its contact overlie the driving gate plate 155a, which overlies the serpentine driving channel 131a] and
overlaps the first compensation protrusion [Paragraph 126: The first boosting electrode 133 of the boosting capacitor Cb is an extension extended from the first storage electrode 132; the 133/157 overlap forms the boosting capacitor Cb; Fig. 2: Cb at the 157/133 overlap].
The rationale of claim 1 applies: Nguyen’s scan-line projection is the express structural implementation of the first compensation capacitor supplied to the combination, and forming Cha’s Cbt with Nguyen’s projection layout is the use of a known layout for its known purpose with predictable results. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 12
Regarding claim 12, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, and Cha further discloses that each of the plurality of subpixels further comprises:
a fourth transistor configured to control a connection between the first node and a first data line [Paragraph 166: The second transistor T2 (a switching transistor) is connected to the data line DL and the first node N1];
a fifth transistor configured to control a connection between the second node and a first initialization line [Paragraph 168: The fourth transistor T4 (a first initialization transistor) is connected to the second node N2 and the first initialization voltage line VLI];
a sixth transistor configured to control a connection between the fourth node and a second initialization line [Fig. 7: T7 connected between the OLED anode node and VL2 (Vint2), gated by SL4; Paragraph 162: The pixel circuit PC may include first to seventh transistors T1, T2, T3, T4, T5, T6, and T7]; and
a storage capacitor disposed between the second node and the driving voltage line [Paragraph 162: a first capacitor Cst and a second capacitor Cbt; Fig. 7: Cst between the ELVDD power line PL and the N2 rail (CE2/CE1)].
Claim Rejections - 35 USC § 103 - Ground II
Claims 4, 5, 13, and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over Cha in view of Nguyen further in view of Seo, as applied to claim 1 above, further in view of Kim H. (US 2021/0193781 A1).
Claim 4
Regarding claim 4, Cha in view of Nguyen further in view of Seo teaches the display device of claim 1, as set forth above, including transmission areas configured to transmit incident light through the panel to an optical electronic device [Cha Paragraph 56: a component 40, which is an electronic element, may be arranged below a display panel 10 to correspond to the component area CA].
Cha in view of Nguyen further in view of Seo does not expressly disclose the recited positional relationship of the light emitting areas to the transmission areas with the particularity recited - namely, that at least one of the first plurality of light emitting areas is disposed between at least two transmission areas among the plurality of transmission areas, and that no other transmission area is present between those two transmission areas.
It is not conceded that Seo’s arrangement, in which the transmission area surrounds the second pixels [Seo Paragraph 69: the transmission area TA may be arranged to surround the second pixels P2], falls outside the recited relationship;
the express teaching of Kim H. is relied upon in preference.
Kim H. discloses the recited relationship:
wherein at least one of the first plurality of light emitting areas is disposed between at least two transmission areas among the plurality of transmission areas, and wherein no other transmission area is present between the at least two transmission areas [Paragraph 237: transmission areas TA may be arranged or disposed between pixel groups Pg. The pixel groups Pg and the transmission areas TA may be alternately arranged or disposed; Fig. 14A: each pixel group sits immediately between the TA to its left and the TA to its right, with no intervening TA].
Kim H. is analogous art to the claimed invention and to Cha, Nguyen, and Seo, being from the same field of endeavor: display panels having a light-transmitting component area, at least partially surrounded by the display area, that overlies an optical component such as a camera or sensor [Paragraph 62: The first area CA may be at least partially surrounded by the display area DA].
It would have been obvious to a person of ordinary skill in the art before the effective filing date to arrange the transmission areas and the light emitting areas of the component area of Cha’s display, as modified, in the alternating relationship taught by Kim H., in which the transmission areas and the pixel groups succeed one another so that a pixel group — and hence its light emitting areas — lies between two transmission areas [Paragraph 90: The transmission area TA may be arranged or disposed between the first and second auxiliary pixels Pa1 and Pa2 in the first area CA; Paragraph 237].
The motivation is Kim H.’s own: interposing the transmission areas among the pixels is what secures the transmittance the underlying component requires [Paragraph 152: To secure a transmittance, the transmission area TA may include a transmission hole TAH in which some insulating layers may be removed], at the cost of resolution within that area [Paragraph 91: Since the first area CA may include the transmission area TA, the resolution of the first area CA may be less than the resolution of the display area DA] - the same transmittance-against-resolution trade that Cha’s component area exists to strike.
Distributing the transmission area among the pixel groups, rather than aggregating it at one side of the component area, obtains that transmittance while keeping the light emitting areas spread across the area, with predictable results. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere co., 383 U.S. 1 (1966).
Claim 5
Regarding claim 5, the combination teaches the display device of claim 1, as set forth above, and Kim H. further teaches:
wherein the at least one first subpixel is disposed between at least two transmission areas among the plurality of transmission areas [Paragraph 237 and Fig. 14A: the alternating checkerboard places each pixel group’s subpixels between the transmission areas on either side].
Claim 13
Regarding claim 13, the combination teaches the display device of claim 1, as set forth above. The combination as applied to claim 4 does not expressly disclose a second optical area of subpixel density intermediate between the first optical area and the normal area.
Kim H. further teaches:
wherein the display area further comprises a second optical area different from the normal area and the first optical area, wherein the second optical area comprises a plurality of light emitting areas and a plurality of transmission areas [Paragraph 240: the first area CA may be provided in plural and the first areas CA respectively may have different pixel arrangement structures],
wherein a number of subpixels per unit area in the first optical area is smaller than a number of subpixels per unit area in the normal area [Paragraph 91: the resolution of the first area CA may be less than the resolution of the display area DA], and
wherein a number of subpixels per unit area in the second optical area is greater than the number of subpixels per unit area in the first optical area, and is smaller than the number of subpixels per unit area in the normal area (for example: see Paragraphs 237-239);
[the disclosed arrangements yield resolutions of about
1
2
,
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4
.
3
8
, and
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16
of the display-area resolution, and two component areas taking different members of this menu, for example:
1
4
and
1
2
, sit in the recited ladder].
It would have been obvious to provide Cha’s display, as modified, with plural component areas of different pixel-arrangement densities as Kim H. expressly proposes, selecting different arrangements from Kim H.’s disclosed menu for the respective areas - a choice among a finite set of disclosed options, each serving the taught trade of resolution against transmittance for the particular underlying component.
Kim H. further teaches grading density within a component area [Paragraph 240: a pixel arrangement having a relatively high resolution is applied to a portion of the first area CA that may neighbor the display area DA], confirming that intermediate densities between the component area and the main display area were an expressly contemplated design variable. KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Claim 14
Regarding claim 14, the combination teaches the display device of claim 1, as set forth above.
The combination as applied to claim 4 does not expressly disclose that the recited adjacent light emitting areas are surrounded by four transmission areas.
Kim H. further teaches: wherein at least two adjacent first light emitting areas among the first plurality of light emitting areas of the first plurality of subpixels are surrounded by four transmission areas among the plurality of transmission areas in the first optical area [Fig. 14A: each interior pixel group - a block of adjacent emitting areas- is bounded by transmission areas on its left, right, upper, and lower sides in the alternating checkerboard; Paragraph 237].
Seo corroborates the surrounding arrangement [Seo Paragraph 69: the transmission area TA may be arranged to surround the second pixels P2].
Claim Rejections - 35 USC § 103 - Ground III
Claims 8, 10, and 11 are rejected under 35 U.S.C. § 103 as being unpatentable over Cha in view of Nguyen further in view of Seo, as applied to claim 1 above, and further in view of So (KR 10-2019-0010058 A; English translation of record, examiner-numbered).
So is prior art under § 102(a)(1), having published 30 January 2019, more than one year before the earliest possible effective filing date; the § 102(b)(1)(A) exception is unavailable notwithstanding the common inventive entity (So Byeong-Seong; Cho Youngsung), and KR 10-2017-0092228 is not within the instant priority chain.
Claim 8
Regarding claim 8, the combination teaches the display device of claim 1, as set forth above, including the first scan line, the light emitting control line, and the first compensation capacitor between the second node and the first scan line (paragraphs 12-14).
Cha in view of Nguyen further in view of Seo does not expressly disclose the recited relative timing of the two control signals - namely, that the light emitting control signal changes from its turn-off level to its turn-on level at a second timing later than the first timing at which the first scan signal changes from its turn-on level to its turn-off level - nor the resulting change of the second-node voltage at the first timing.
So discloses both:
wherein at a first timing, the first scan signal is changed from a first turn-on level voltage to a first turn-off level voltage [Paragraph 77: at the time point of the third period t3, the k-th scan signal scank rises from the gate-on voltage von to the gate-off voltage voff], and
at a second timing later than the first timing, the light emitting control signal is changed from a second turn-off level voltage to a second turn-on level voltage [Paragraph 78: At the end point of the third period t3, the k-th emission signal emk falls from the gate-off voltage voff to the gate-on voltage von; Fig. 4: SCANk transitions at the t2/t3 boundary; EMK transitions one full period later at the t3/t4 boundary], and
wherein at the first timing, the voltage at the second node is changed according to a change in voltage of the first scan signal [Paragraph 59: a parasitic capacitance cp may be formed between the gate electrode dg of the driving transistor dt and the kth scan line sk; Fig. 4: the driving-gate voltage VDG steps by ∆V1 at the SCANk transition].
So is analogous art, being from the same field of endeavor: OLED pixel circuits managing gate-node voltage changes coupled from the scan and emission control lines.
It would have been obvious to operate the combined device of claim 1 with So’s drive sequence - scan turn-off followed by emission turn-on, with the gate node responding to each line transition through its coupling capacitance - because that sequence is So’s expressly illustrated normal operation of the very capacitor architecture the combination employs, and because the claimed response at the second node is the inherent electrical behavior of a gate node coupled to the transitioning line. KSR, 550 U.S. 398; Graham, 383 U.S. 1. MPEP §§ 2112, 2114.
Claim 10
Regarding claim 10, the combination teaches the display device of claim 1, as set forth above, and So further teaches:
wherein at a first timing, the first scan signal is changed from a first turn-on level voltage to a first turn-off level voltage, and at a second timing later than the first timing, the light emitting control signal is changed from a second turn-off level voltage to a second turn-on level voltage [Paragraphs 77-78; Fig. 4 - as set forth for claim 8], and
wherein at the second timing, the voltage at the second node is changed according to a change in voltage of the light emitting control signal [Paragraph 58: The second capacitor c2 may be formed between the gate electrode dg of the driving transistor dt and the kth emission control line ek; Fig. 4: the driving-gate voltage VDG steps by AV2 at the EMK transition at the t3/t4 boundary]. The rationale applied to claim 8 applies.
Claim 11
Regarding claim 11, the combination teaches the display device of claim 1, as set forth above, and So further teaches:
wherein the at least one first subpixel comprises a connection pattern corresponding to the second node [Paragraph 97: The gate electrode dg of the driving transistor dt includes a gate metal pattern gp and a data metal pattern dp; the data metal pattern dp is a pattern of, and connected to, the driving-gate node], and
the light emitting control line comprises a second compensation protrusion [Fig. 8 (A-A’ section): the emission control line 140(Ek) is drawn wider at its base than at its top, its base extending laterally beyond the footprint of its narrower top - a protrusion of the line under the ordinary meaning of the term, which the claim does not limit by direction, dimension, or discreteness], and
wherein the connection pattern intersects an active layer of the driving transistor [Fig. 7: the dp column (layer 180) crosses the region where the driving transistor’s gate metal (140, carrying contact hole CHI per Paragraph 97) overlies the active layer (120), the superposition rendered as cross-hatch; corroborated in Fig. 8, where 180(dp) spans the section over the 120 layer] and
overlaps the second compensation protrusion [Paragraph 98: The second capacitor c2 is formed in an overlapping region between the data metal pattern dp of the driving transistor dt and the k-th light emitting line ek; Paragraph 100: The capacitance of the second capacitor c2 may be changed by adjusting the size of the overlapping region of the data metal pattern dp and the k-th emission line ek].
The rationale applied to claim 8 applies.
Alternatively and additionally, to the extent the flared base of So’s emission control line is argued not to be a “protrusion,” it would have been obvious to enlarge the dp/ek overlap that So expressly teaches adjusting (Paragraph 100) by widening the line locally at the crossing - a projecting part on a signal line overlapping a driving-gate pattern to form a capacitor being a known expedient, see Choi (US 2018/0212014 A1) at Paragraph 9 (an extending part extending from the driving voltage line and overlapping the driving gate electrode to form a capacitor), cited as evidence of the level of ordinary skill (MPEP § 2144.03).
The result - increased second-capacitor capacitance - is exactly the predictable consequence So attributes to a larger overlap. KSR, 550 U.S. 398.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
US 2017/0345367 A1 (per-region boost-capacitance differential with express brightness-difference-compensation motive);
US 2012/0062545 A1 (Paragraph 145: the switching transistor and the threshold voltage compensation transistor receive the same scan signal at their gates - single-line gating of both functions);
US 2022/0044634 A1 (two separately tuned gate-node coupling capacitors on two control lines; line-width tuning);
US 2023/0162676 A1 (protruded part sized to control luminance difference);
US 2021/0241689 A1 (capacitor electrode formed as a part of the scan line);
US 2014/0320544 A1 (boosting plate of hammer shape);
KR 10-2018-0025488 A (the four-node architecture and the coupling problem addressed).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
16 August 2026
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