DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 7, 12 – 14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US Publication Number 2014/0314076, hereinafter “Guo”) in view of Kumar et al. (US Publication Number 2015/0036536, hereinafter “Kumar”) in view of Fleming, JR. et al. (US Publication Number 2019/0205269, hereinafter “Fleming”) further in view of Kibardin et al. (US Publication Number 2023/0071424, hereinafter “Kibardin”).
4. As per claims 1, 13, and 20, Guo teaches a method, system, and a non-transitory computer-readable storage medium comprising: wherein the cost estimation tool is configured to: in response to determining that the physical consumer unit (downstream router 650 with VC storage 655, figure 6) is end-to-end credit-controlled (upstream router 605 reduces credit count 625 by one for each flit send and will not forward any flits while count zero, downstream router 650 returns a credit over credit channel 635 s each flit leaves storage, figures 5 and 6, paragraphs 51 – 54): determine a first latency (credit round trip delay Tcrt, figure 9) that is indicative of a first distance between the physical producer unit (upstream router 605, figure 6) and the physical consumer unit (Tcrt includes a round trip wire delay and the processing time at the downstream and upstream routers and router pipeline configurations range from highest to lowest hop latency figures 8 and 9, paragraphs 74 and 76), and determine the end-to-end bandwidth between the physical producer unit and the physical consumer unit based on dividing a predetermined first- in first-out buffer depth (VC storage 655, figure 6) with a sum of the first and second latencies (credit round trip delay may be used to determine the maximum throughput a flow control mechanism supports, the flit buffers required per VC are sized from Tcrt times channel bandwidth over flit length and when storage meets that relation the maximum channel bandwidth is not limited by buffer size, Tcrt built by adding component delays t1…t4, figure 9, paragraphs 75 – 77).
Guo does not appear to explicitly disclose a cost estimation tool for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor, receive a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor; determine whether an end-to-end bandwidth between the physical producer unit and the physical consumer unit is end-to-end credit-controlled; in response to determining that the physical consumer unit is not end-to-end credit-controlled: determine the end-to-end bandwidth to be 100 percent; determine a second latency that is indicative of a second distance between the physical producer unit and the physical consumer unit and between the physical producer unit and any other placed physical consumer unit ; and determine a realized bandwidth consumption of the tentative assignment based on the end-to-end bandwidth
However, Kumar discloses receive a tentative assignment (proposed new position of port x1, figure 6, step 606, paragraph 70) of the logical edge, the logical producer unit, and the logical consumer unit to a physical link (NoC channel between routers, paragraph 16), a physical producer unit, and a physical consumer unit (hosts CPU1 and MEM1 placed in mesh cells, figure 4b, paragraph 24) of the reconfigurable processor (cost function computed for port at initial position and proposed new position and relocation accepted/rejected on old cost, new cost and probability function, traffic flows are mapped to routes over channel, figures 6 and 8, paragraphs 70 – 72, 88 and 89); and determine a realized bandwidth consumption of the tentative assignment based on the end-to-end bandwidth (bandwidth requirement at channel is determined by flows that traverse it and their bandwidth values, the cost for proposed position computed from latency/bandwidth, channel bandwidth tracked as flows mapped, paragraphs 16, 70, and 92).
Guo and Kumar are analogous art because they are from the same field of endeavor of latency handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Guo and Kumar before him or her, to modify the mechanism of Guo to include the bandwidth handling of Kumar because it would enhance realized requirements of the system.
One of ordinary skill would be motivated to make such modification in order to enhance packet handling (paragraphs 6 – 9). Therefore, it would have been obvious to combine Kumar with Guo to obtain the invention as specified in the instant claim(s).
Guo/Kumar does not appear to explicitly disclose a cost estimation tool for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor, determine whether an end-to-end bandwidth between the physical producer unit and the physical consumer unit is end-to-end credit-controlled; in response to determining that the physical consumer unit is not end-to-end credit-controlled: determine the end-to-end bandwidth to be 100 percent; determine a second latency that is indicative of a second distance between the physical producer unit and the physical consumer unit and between the physical producer unit and any other placed physical consumer unit
However, Fleming discloses determine whether an end-to-end bandwidth between the physical producer unit and the physical consumer unit is end-to-end credit-controlled (consumer Pes 1005/1007, figure 10a); in response to determining that the physical consumer unit is not end-to-end credit-controlled (local network provides point to point flow controlled communications channels where buffer-less and data moves between producer and consumer in a single cycle with inter-PE latency as low as zero cycles, paragraphs 134, 155): determine the end-to-end bandwidth to be 100 percent (a channel that moves one value per cycle between producer and consumer runs at full rate, paragraphs 162 - 164); determine a second latency that is indicative of a second distance between the physical producer unit (producer PE 1003, figures 10a/b) and the physical consumer unit (first consumer PE 1005, figure 10a) and between the physical producer unit and any other placed physical consumer unit (second consumer PE 1007, figure 10a, a multicast requires all of the consumer Pes to be ready before the producer PE begins a broadcast and the flow control path in network 1001 of figure 10b aggregates ready values of consumer Pes 1005/1007 and sends to 1003)
Guo/Kumar and Fleming are analogous art because they are from the same field of endeavor latency handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Guo/Kumar and Fleming before him or her, to modify the mechanism of Guo/Kumar to include the producer/consumer of Fleming because it would allow for robustness in the system.
One of ordinary skill would be motivated to make such modification in order to enhance processing efficiency (paragraphs 115 and 116). Therefore, it would have been obvious to combine Fleming with Guo/Kumar to obtain the invention as specified in the instant claims.
Guo/Kumar/Fleming does not appear to explicitly disclose a cost estimation tool for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor,
However, Kibardin discloses a cost estimation tool (placements server 150 with neuron to PE mapping SW 212 in CRM 152 executed by 151, figures 1 and 2) for routing a logical edge between a logical producer unit and a logical consumer unit onto a reconfigurable processor (array of processing elements with configurable routers, the placement server runs mapping software that determines placement of computer and memory onto the processing elements, evaluating candidate placements by a wire cost based on Manhattan distance, and placement configures routers, EC109, figures 58, 59, and 612).
Guo/Kumar/Fleming and Kibardin are analogous art because they are from the same field of endeavor of latency handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Guo/Kumar/Fleming and Kibardin before him or her, to modify the mechanism of Guo/Kumar/Fleming to include the cost estimation of Kibardin because it would enhance latency handling.
One of ordinary skill would be motivated to make such modification in order to enhance efficiency in the interconnected system (paragraph 132). Therefore, it would have been obvious to combine Kibardin with Guo/Kumar/Fleming to obtain the invention as specified in the instant claims.
5. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claim 2, Fleming teaches a method, wherein the reconfigurable processor (accelerator tile 100, figure 1) comprises arrays of coarse-grained reconfigurable (CGR) units (integer arithmetic PEs and floating point arithmetic Pes of accelerator tile 100, the configurable spatial accelerator includes integer and floating point PEs mapped to data flow graphs, figures 3b/c and 4).
6. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claim 3, Fleming teaches a method, wherein the logical consumer unit (consumer PEs 1005/1007, figure 10a) comprises a compute unit or a memory unit (consumer of multicast are processing elements where tile includes in fabric storage and memory interface 102, figures 1 and 3c).
7. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claim 4, Kumar teaches a method, further comprising: providing the realized bandwidth consumption of the tentative assignment as a cost estimation to a placement and routing tool (relocation check at step 607, figure 6, route selection at step 806, figure 8, cost computed for the proposed position in input to the check to accept/reject relocation and eligible route’s cost function decides which route a flow is mapped to, paragraphs 70 – 72 and 89).
8. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claims 5, 6, and 14, Kumar teaches a method and system, wherein, for determining the first latency, the cost estimation tool is further configured to: determine a number of hops between the physical producer unit (host CPU1, figure 4b) and the physical consumer unit (host MEM1, figure 4b, placements are compared by structural latency in number of hops and a route’s cost function can be based on the number of hops, paragraphs 24, 25, and 89); and determine the first latency by multiplying the number of hops with a hop-to-hop latency (number of hops, paragraphs 24, 25, and 89, also seen in Guo: router pipeline configuration sets hop latency, paragraphs 40 and 74).
9. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claim 7, Kibardin teaches a method, wherein determining the second latency further comprises: determining a maximum Manhattan distance between the physical producer unit and the physical consumer unit (processing elements placed by Neuron to PE mapping SW 212, candidate placements evaluated by wire costs based on Manhattan distance, EC 109, figure 61) and between the physical producer unit and any other placed physical consumer unit (Fleming: second consumer PE 1007 figure 10a, producer’s multicast waits on the aggregated ready values of every consumer PE).
10. Guo modified by the teachings Kumar/Fleming/Kibardin as seen in claim 1 above, as per claims 12 and 18, Kumar teaches a method and system, wherein the cost estimation tool is further configured to: determine a sum of realized average bandwidths of all the logical edges that are assigned to use the physical link (NoC channel, paragraph 16) to determine a congestion estimation of the physical link (channels see different levels of load and congestion depending on the routes taken, the bandwidth requirement at a channel is determined by the flows that traverse it and their bandwidth values, and data structures track the bandwidth of the channels as flows are mapped, paragraphs 16 and 92); and determine the realized bandwidth consumption of the tentative assignment based on the end-to-end bandwidth and the congestion estimation of the physical link (route is considered only where bandwidth for the flow is available with load balancing in terms of bandwidth, paragraph 92).
Allowable Subject Matter
11. Claims 8 – 11, 15 – 17, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dielissen/Etsion/Guttag/Huggett/Parker/Puranik/Shihada/Tran/Fleming/Kumar have teachings relevant to cost estimation and latency management.
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/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
